|LED_hello_world
CLK => PLL:inst1.inclk0
RESET => CORE_SOPC:inst.reset_n
EPCS_DATA0 => CORE_SOPC:inst.data0_to_the_epcs
MISO_to_the_spi_touch => CORE_SOPC:inst.MISO_to_the_spi_touch
in_port_to_the_touch_irq => CORE_SOPC:inst.in_port_to_the_touch_irq
bidir_port_to_and_from_the_lcd32_data[0] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[0]
bidir_port_to_and_from_the_lcd32_data[1] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[1]
bidir_port_to_and_from_the_lcd32_data[2] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[2]
bidir_port_to_and_from_the_lcd32_data[3] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[3]
bidir_port_to_and_from_the_lcd32_data[4] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[4]
bidir_port_to_and_from_the_lcd32_data[5] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[5]
bidir_port_to_and_from_the_lcd32_data[6] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[6]
bidir_port_to_and_from_the_lcd32_data[7] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[7]
bidir_port_to_and_from_the_lcd32_data[8] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[8]
bidir_port_to_and_from_the_lcd32_data[9] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[9]
bidir_port_to_and_from_the_lcd32_data[10] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[10]
bidir_port_to_and_from_the_lcd32_data[11] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[11]
bidir_port_to_and_from_the_lcd32_data[12] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[12]
bidir_port_to_and_from_the_lcd32_data[13] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[13]
bidir_port_to_and_from_the_lcd32_data[14] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[14]
bidir_port_to_and_from_the_lcd32_data[15] <> CORE_SOPC:inst.bidir_port_to_and_from_the_lcd32_data[15]
DQ[0] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[0]
DQ[1] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[1]
DQ[2] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[2]
DQ[3] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[3]
DQ[4] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[4]
DQ[5] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[5]
DQ[6] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[6]
DQ[7] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[7]
DQ[8] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[8]
DQ[9] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[9]
DQ[10] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[10]
DQ[11] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[11]
DQ[12] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[12]
DQ[13] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[13]
DQ[14] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[14]
DQ[15] <> CORE_SOPC:inst.zs_dq_to_and_from_the_sdram[15]


|LED_hello_world|PLL:inst1
inclk0 => sub_wire4[0].IN1


|LED_hello_world|PLL:inst1|altpll:altpll_component
inclk[0] => PLL_altpll:auto_generated.inclk[0]
inclk[1] => PLL_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>


|LED_hello_world|PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1


|LED_hello_world|CORE_SOPC:inst
clk => clk.IN34
reset_n => reset_n_sources.IN1
data0_to_the_epcs => data0_to_the_epcs.IN1
bidir_port_to_and_from_the_lcd32_data[0] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[1] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[2] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[3] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[4] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[5] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[6] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[7] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[8] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[9] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[10] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[11] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[12] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[13] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[14] <> lcd32_data:the_lcd32_data.bidir_port
bidir_port_to_and_from_the_lcd32_data[15] <> lcd32_data:the_lcd32_data.bidir_port
zs_dq_to_and_from_the_sdram[0] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[1] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[2] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[3] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[4] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[5] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[6] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[7] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[8] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[9] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[10] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[11] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[12] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[13] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[14] <> sdram:the_sdram.zs_dq
zs_dq_to_and_from_the_sdram[15] <> sdram:the_sdram.zs_dq
MISO_to_the_spi_touch => MISO_to_the_spi_touch.IN1
in_port_to_the_touch_irq => in_port_to_the_touch_irq.IN1


|LED_hello_world|CORE_SOPC:inst|bl_n_s1_arbitrator:the_bl_n_s1
bl_n_s1_readdata[0] => bl_n_s1_readdata_from_sa[0].DATAIN
bl_n_s1_readdata[1] => bl_n_s1_readdata_from_sa[1].DATAIN
bl_n_s1_readdata[2] => bl_n_s1_readdata_from_sa[2].DATAIN
bl_n_s1_readdata[3] => bl_n_s1_readdata_from_sa[3].DATAIN
bl_n_s1_readdata[4] => bl_n_s1_readdata_from_sa[4].DATAIN
bl_n_s1_readdata[5] => bl_n_s1_readdata_from_sa[5].DATAIN
bl_n_s1_readdata[6] => bl_n_s1_readdata_from_sa[6].DATAIN
bl_n_s1_readdata[7] => bl_n_s1_readdata_from_sa[7].DATAIN
bl_n_s1_readdata[8] => bl_n_s1_readdata_from_sa[8].DATAIN
bl_n_s1_readdata[9] => bl_n_s1_readdata_from_sa[9].DATAIN
bl_n_s1_readdata[10] => bl_n_s1_readdata_from_sa[10].DATAIN
bl_n_s1_readdata[11] => bl_n_s1_readdata_from_sa[11].DATAIN
bl_n_s1_readdata[12] => bl_n_s1_readdata_from_sa[12].DATAIN
bl_n_s1_readdata[13] => bl_n_s1_readdata_from_sa[13].DATAIN
bl_n_s1_readdata[14] => bl_n_s1_readdata_from_sa[14].DATAIN
bl_n_s1_readdata[15] => bl_n_s1_readdata_from_sa[15].DATAIN
bl_n_s1_readdata[16] => bl_n_s1_readdata_from_sa[16].DATAIN
bl_n_s1_readdata[17] => bl_n_s1_readdata_from_sa[17].DATAIN
bl_n_s1_readdata[18] => bl_n_s1_readdata_from_sa[18].DATAIN
bl_n_s1_readdata[19] => bl_n_s1_readdata_from_sa[19].DATAIN
bl_n_s1_readdata[20] => bl_n_s1_readdata_from_sa[20].DATAIN
bl_n_s1_readdata[21] => bl_n_s1_readdata_from_sa[21].DATAIN
bl_n_s1_readdata[22] => bl_n_s1_readdata_from_sa[22].DATAIN
bl_n_s1_readdata[23] => bl_n_s1_readdata_from_sa[23].DATAIN
bl_n_s1_readdata[24] => bl_n_s1_readdata_from_sa[24].DATAIN
bl_n_s1_readdata[25] => bl_n_s1_readdata_from_sa[25].DATAIN
bl_n_s1_readdata[26] => bl_n_s1_readdata_from_sa[26].DATAIN
bl_n_s1_readdata[27] => bl_n_s1_readdata_from_sa[27].DATAIN
bl_n_s1_readdata[28] => bl_n_s1_readdata_from_sa[28].DATAIN
bl_n_s1_readdata[29] => bl_n_s1_readdata_from_sa[29].DATAIN
bl_n_s1_readdata[30] => bl_n_s1_readdata_from_sa[30].DATAIN
bl_n_s1_readdata[31] => bl_n_s1_readdata_from_sa[31].DATAIN
clk => d1_bl_n_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => bl_n_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => bl_n_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN4
cpu_data_master_address_to_slave[5] => Equal0.IN3
cpu_data_master_address_to_slave[6] => Equal0.IN22
cpu_data_master_address_to_slave[7] => Equal0.IN2
cpu_data_master_address_to_slave[8] => Equal0.IN21
cpu_data_master_address_to_slave[9] => Equal0.IN20
cpu_data_master_address_to_slave[10] => Equal0.IN19
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN18
cpu_data_master_address_to_slave[14] => Equal0.IN17
cpu_data_master_address_to_slave[15] => Equal0.IN16
cpu_data_master_address_to_slave[16] => Equal0.IN15
cpu_data_master_address_to_slave[17] => Equal0.IN14
cpu_data_master_address_to_slave[18] => Equal0.IN13
cpu_data_master_address_to_slave[19] => Equal0.IN12
cpu_data_master_address_to_slave[20] => Equal0.IN11
cpu_data_master_address_to_slave[21] => Equal0.IN10
cpu_data_master_address_to_slave[22] => Equal0.IN9
cpu_data_master_address_to_slave[23] => Equal0.IN8
cpu_data_master_address_to_slave[24] => Equal0.IN7
cpu_data_master_address_to_slave[25] => Equal0.IN6
cpu_data_master_address_to_slave[26] => Equal0.IN5
cpu_data_master_read => cpu_data_master_requests_bl_n_s1.IN0
cpu_data_master_read => bl_n_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_bl_n_s1.IN0
cpu_data_master_write => cpu_data_master_requests_bl_n_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_bl_n_s1.IN1
cpu_data_master_write => bl_n_s1_write_n.IN1
cpu_data_master_writedata[0] => bl_n_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => bl_n_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => bl_n_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => bl_n_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => bl_n_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => bl_n_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => bl_n_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => bl_n_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => bl_n_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => bl_n_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => bl_n_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => bl_n_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => bl_n_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => bl_n_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => bl_n_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => bl_n_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => bl_n_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => bl_n_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => bl_n_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => bl_n_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => bl_n_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => bl_n_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => bl_n_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => bl_n_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => bl_n_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => bl_n_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => bl_n_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => bl_n_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => bl_n_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => bl_n_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => bl_n_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => bl_n_s1_writedata[31].DATAIN
reset_n => bl_n_s1_reset_n.DATAIN
reset_n => d1_bl_n_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR


|LED_hello_world|CORE_SOPC:inst|bl_n:the_bl_n
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|bl_p_s1_arbitrator:the_bl_p_s1
bl_p_s1_readdata[0] => bl_p_s1_readdata_from_sa[0].DATAIN
bl_p_s1_readdata[1] => bl_p_s1_readdata_from_sa[1].DATAIN
bl_p_s1_readdata[2] => bl_p_s1_readdata_from_sa[2].DATAIN
bl_p_s1_readdata[3] => bl_p_s1_readdata_from_sa[3].DATAIN
bl_p_s1_readdata[4] => bl_p_s1_readdata_from_sa[4].DATAIN
bl_p_s1_readdata[5] => bl_p_s1_readdata_from_sa[5].DATAIN
bl_p_s1_readdata[6] => bl_p_s1_readdata_from_sa[6].DATAIN
bl_p_s1_readdata[7] => bl_p_s1_readdata_from_sa[7].DATAIN
bl_p_s1_readdata[8] => bl_p_s1_readdata_from_sa[8].DATAIN
bl_p_s1_readdata[9] => bl_p_s1_readdata_from_sa[9].DATAIN
bl_p_s1_readdata[10] => bl_p_s1_readdata_from_sa[10].DATAIN
bl_p_s1_readdata[11] => bl_p_s1_readdata_from_sa[11].DATAIN
bl_p_s1_readdata[12] => bl_p_s1_readdata_from_sa[12].DATAIN
bl_p_s1_readdata[13] => bl_p_s1_readdata_from_sa[13].DATAIN
bl_p_s1_readdata[14] => bl_p_s1_readdata_from_sa[14].DATAIN
bl_p_s1_readdata[15] => bl_p_s1_readdata_from_sa[15].DATAIN
bl_p_s1_readdata[16] => bl_p_s1_readdata_from_sa[16].DATAIN
bl_p_s1_readdata[17] => bl_p_s1_readdata_from_sa[17].DATAIN
bl_p_s1_readdata[18] => bl_p_s1_readdata_from_sa[18].DATAIN
bl_p_s1_readdata[19] => bl_p_s1_readdata_from_sa[19].DATAIN
bl_p_s1_readdata[20] => bl_p_s1_readdata_from_sa[20].DATAIN
bl_p_s1_readdata[21] => bl_p_s1_readdata_from_sa[21].DATAIN
bl_p_s1_readdata[22] => bl_p_s1_readdata_from_sa[22].DATAIN
bl_p_s1_readdata[23] => bl_p_s1_readdata_from_sa[23].DATAIN
bl_p_s1_readdata[24] => bl_p_s1_readdata_from_sa[24].DATAIN
bl_p_s1_readdata[25] => bl_p_s1_readdata_from_sa[25].DATAIN
bl_p_s1_readdata[26] => bl_p_s1_readdata_from_sa[26].DATAIN
bl_p_s1_readdata[27] => bl_p_s1_readdata_from_sa[27].DATAIN
bl_p_s1_readdata[28] => bl_p_s1_readdata_from_sa[28].DATAIN
bl_p_s1_readdata[29] => bl_p_s1_readdata_from_sa[29].DATAIN
bl_p_s1_readdata[30] => bl_p_s1_readdata_from_sa[30].DATAIN
bl_p_s1_readdata[31] => bl_p_s1_readdata_from_sa[31].DATAIN
clk => d1_bl_p_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => bl_p_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => bl_p_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN22
cpu_data_master_address_to_slave[5] => Equal0.IN3
cpu_data_master_address_to_slave[6] => Equal0.IN21
cpu_data_master_address_to_slave[7] => Equal0.IN2
cpu_data_master_address_to_slave[8] => Equal0.IN20
cpu_data_master_address_to_slave[9] => Equal0.IN19
cpu_data_master_address_to_slave[10] => Equal0.IN18
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN17
cpu_data_master_address_to_slave[14] => Equal0.IN16
cpu_data_master_address_to_slave[15] => Equal0.IN15
cpu_data_master_address_to_slave[16] => Equal0.IN14
cpu_data_master_address_to_slave[17] => Equal0.IN13
cpu_data_master_address_to_slave[18] => Equal0.IN12
cpu_data_master_address_to_slave[19] => Equal0.IN11
cpu_data_master_address_to_slave[20] => Equal0.IN10
cpu_data_master_address_to_slave[21] => Equal0.IN9
cpu_data_master_address_to_slave[22] => Equal0.IN8
cpu_data_master_address_to_slave[23] => Equal0.IN7
cpu_data_master_address_to_slave[24] => Equal0.IN6
cpu_data_master_address_to_slave[25] => Equal0.IN5
cpu_data_master_address_to_slave[26] => Equal0.IN4
cpu_data_master_read => cpu_data_master_requests_bl_p_s1.IN0
cpu_data_master_read => bl_p_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_bl_p_s1.IN0
cpu_data_master_write => cpu_data_master_requests_bl_p_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_bl_p_s1.IN1
cpu_data_master_write => bl_p_s1_write_n.IN1
cpu_data_master_writedata[0] => bl_p_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => bl_p_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => bl_p_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => bl_p_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => bl_p_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => bl_p_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => bl_p_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => bl_p_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => bl_p_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => bl_p_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => bl_p_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => bl_p_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => bl_p_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => bl_p_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => bl_p_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => bl_p_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => bl_p_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => bl_p_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => bl_p_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => bl_p_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => bl_p_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => bl_p_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => bl_p_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => bl_p_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => bl_p_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => bl_p_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => bl_p_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => bl_p_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => bl_p_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => bl_p_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => bl_p_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => bl_p_s1_writedata[31].DATAIN
reset_n => bl_p_s1_reset_n.DATAIN
reset_n => d1_bl_p_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR


|LED_hello_world|CORE_SOPC:inst|bl_p:the_bl_p
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module
clk => d1_cpu_jtag_debug_module_end_xfer~reg0.CLK
clk => cpu_jtag_debug_module_reg_firsttransfer.CLK
clk => cpu_jtag_debug_module_arb_addend[0].CLK
clk => cpu_jtag_debug_module_arb_addend[1].CLK
clk => cpu_jtag_debug_module_saved_chosen_master_vector[0].CLK
clk => cpu_jtag_debug_module_saved_chosen_master_vector[1].CLK
clk => last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module.CLK
clk => last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module.CLK
clk => cpu_jtag_debug_module_slavearbiterlockenable.CLK
clk => cpu_jtag_debug_module_arb_share_counter[0].CLK
clk => cpu_jtag_debug_module_arb_share_counter[1].CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[3] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[4] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[5] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[6] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[7] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[8] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[9] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[10] => cpu_jtag_debug_module_address.DATAB
cpu_data_master_address_to_slave[11] => Equal0.IN14
cpu_data_master_address_to_slave[12] => Equal0.IN37
cpu_data_master_address_to_slave[13] => Equal0.IN13
cpu_data_master_address_to_slave[14] => Equal0.IN12
cpu_data_master_address_to_slave[15] => Equal0.IN11
cpu_data_master_address_to_slave[16] => Equal0.IN10
cpu_data_master_address_to_slave[17] => Equal0.IN9
cpu_data_master_address_to_slave[18] => Equal0.IN8
cpu_data_master_address_to_slave[19] => Equal0.IN7
cpu_data_master_address_to_slave[20] => Equal0.IN6
cpu_data_master_address_to_slave[21] => Equal0.IN5
cpu_data_master_address_to_slave[22] => Equal0.IN4
cpu_data_master_address_to_slave[23] => Equal0.IN3
cpu_data_master_address_to_slave[24] => Equal0.IN2
cpu_data_master_address_to_slave[25] => Equal0.IN1
cpu_data_master_address_to_slave[26] => Equal0.IN0
cpu_data_master_byteenable[0] => cpu_jtag_debug_module_byteenable.DATAB
cpu_data_master_byteenable[1] => cpu_jtag_debug_module_byteenable.DATAB
cpu_data_master_byteenable[2] => cpu_jtag_debug_module_byteenable.DATAB
cpu_data_master_byteenable[3] => cpu_jtag_debug_module_byteenable.DATAB
cpu_data_master_debugaccess => cpu_jtag_debug_module_debugaccess.DATAB
cpu_data_master_read => cpu_data_master_requests_cpu_jtag_debug_module.IN0
cpu_data_master_read => cpu_jtag_debug_module_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_cpu_jtag_debug_module.IN0
cpu_data_master_write => cpu_data_master_requests_cpu_jtag_debug_module.IN1
cpu_data_master_write => cpu_data_master_qualified_request_cpu_jtag_debug_module.IN1
cpu_data_master_write => cpu_jtag_debug_module_write.IN1
cpu_data_master_writedata[0] => cpu_jtag_debug_module_writedata[0].DATAIN
cpu_data_master_writedata[1] => cpu_jtag_debug_module_writedata[1].DATAIN
cpu_data_master_writedata[2] => cpu_jtag_debug_module_writedata[2].DATAIN
cpu_data_master_writedata[3] => cpu_jtag_debug_module_writedata[3].DATAIN
cpu_data_master_writedata[4] => cpu_jtag_debug_module_writedata[4].DATAIN
cpu_data_master_writedata[5] => cpu_jtag_debug_module_writedata[5].DATAIN
cpu_data_master_writedata[6] => cpu_jtag_debug_module_writedata[6].DATAIN
cpu_data_master_writedata[7] => cpu_jtag_debug_module_writedata[7].DATAIN
cpu_data_master_writedata[8] => cpu_jtag_debug_module_writedata[8].DATAIN
cpu_data_master_writedata[9] => cpu_jtag_debug_module_writedata[9].DATAIN
cpu_data_master_writedata[10] => cpu_jtag_debug_module_writedata[10].DATAIN
cpu_data_master_writedata[11] => cpu_jtag_debug_module_writedata[11].DATAIN
cpu_data_master_writedata[12] => cpu_jtag_debug_module_writedata[12].DATAIN
cpu_data_master_writedata[13] => cpu_jtag_debug_module_writedata[13].DATAIN
cpu_data_master_writedata[14] => cpu_jtag_debug_module_writedata[14].DATAIN
cpu_data_master_writedata[15] => cpu_jtag_debug_module_writedata[15].DATAIN
cpu_data_master_writedata[16] => cpu_jtag_debug_module_writedata[16].DATAIN
cpu_data_master_writedata[17] => cpu_jtag_debug_module_writedata[17].DATAIN
cpu_data_master_writedata[18] => cpu_jtag_debug_module_writedata[18].DATAIN
cpu_data_master_writedata[19] => cpu_jtag_debug_module_writedata[19].DATAIN
cpu_data_master_writedata[20] => cpu_jtag_debug_module_writedata[20].DATAIN
cpu_data_master_writedata[21] => cpu_jtag_debug_module_writedata[21].DATAIN
cpu_data_master_writedata[22] => cpu_jtag_debug_module_writedata[22].DATAIN
cpu_data_master_writedata[23] => cpu_jtag_debug_module_writedata[23].DATAIN
cpu_data_master_writedata[24] => cpu_jtag_debug_module_writedata[24].DATAIN
cpu_data_master_writedata[25] => cpu_jtag_debug_module_writedata[25].DATAIN
cpu_data_master_writedata[26] => cpu_jtag_debug_module_writedata[26].DATAIN
cpu_data_master_writedata[27] => cpu_jtag_debug_module_writedata[27].DATAIN
cpu_data_master_writedata[28] => cpu_jtag_debug_module_writedata[28].DATAIN
cpu_data_master_writedata[29] => cpu_jtag_debug_module_writedata[29].DATAIN
cpu_data_master_writedata[30] => cpu_jtag_debug_module_writedata[30].DATAIN
cpu_data_master_writedata[31] => cpu_jtag_debug_module_writedata[31].DATAIN
cpu_instruction_master_address_to_slave[0] => ~NO_FANOUT~
cpu_instruction_master_address_to_slave[1] => ~NO_FANOUT~
cpu_instruction_master_address_to_slave[2] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[3] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[4] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[5] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[6] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[7] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[8] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[9] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[10] => cpu_jtag_debug_module_address.DATAA
cpu_instruction_master_address_to_slave[11] => Equal1.IN14
cpu_instruction_master_address_to_slave[12] => Equal1.IN37
cpu_instruction_master_address_to_slave[13] => Equal1.IN13
cpu_instruction_master_address_to_slave[14] => Equal1.IN12
cpu_instruction_master_address_to_slave[15] => Equal1.IN11
cpu_instruction_master_address_to_slave[16] => Equal1.IN10
cpu_instruction_master_address_to_slave[17] => Equal1.IN9
cpu_instruction_master_address_to_slave[18] => Equal1.IN8
cpu_instruction_master_address_to_slave[19] => Equal1.IN7
cpu_instruction_master_address_to_slave[20] => Equal1.IN6
cpu_instruction_master_address_to_slave[21] => Equal1.IN5
cpu_instruction_master_address_to_slave[22] => Equal1.IN4
cpu_instruction_master_address_to_slave[23] => Equal1.IN3
cpu_instruction_master_address_to_slave[24] => Equal1.IN2
cpu_instruction_master_address_to_slave[25] => Equal1.IN1
cpu_instruction_master_address_to_slave[26] => Equal1.IN0
cpu_instruction_master_latency_counter => cpu_instruction_master_qualified_request_cpu_jtag_debug_module.IN0
cpu_instruction_master_read => cpu_instruction_master_requests_cpu_jtag_debug_module.IN1
cpu_instruction_master_read => cpu_instruction_master_requests_cpu_jtag_debug_module.IN1
cpu_instruction_master_read => cpu_instruction_master_qualified_request_cpu_jtag_debug_module.IN1
cpu_instruction_master_read => cpu_jtag_debug_module_in_a_read_cycle.IN1
cpu_instruction_master_read_data_valid_sdram_s1_shift_register => cpu_instruction_master_qualified_request_cpu_jtag_debug_module.IN1
cpu_jtag_debug_module_readdata[0] => cpu_jtag_debug_module_readdata_from_sa[0].DATAIN
cpu_jtag_debug_module_readdata[1] => cpu_jtag_debug_module_readdata_from_sa[1].DATAIN
cpu_jtag_debug_module_readdata[2] => cpu_jtag_debug_module_readdata_from_sa[2].DATAIN
cpu_jtag_debug_module_readdata[3] => cpu_jtag_debug_module_readdata_from_sa[3].DATAIN
cpu_jtag_debug_module_readdata[4] => cpu_jtag_debug_module_readdata_from_sa[4].DATAIN
cpu_jtag_debug_module_readdata[5] => cpu_jtag_debug_module_readdata_from_sa[5].DATAIN
cpu_jtag_debug_module_readdata[6] => cpu_jtag_debug_module_readdata_from_sa[6].DATAIN
cpu_jtag_debug_module_readdata[7] => cpu_jtag_debug_module_readdata_from_sa[7].DATAIN
cpu_jtag_debug_module_readdata[8] => cpu_jtag_debug_module_readdata_from_sa[8].DATAIN
cpu_jtag_debug_module_readdata[9] => cpu_jtag_debug_module_readdata_from_sa[9].DATAIN
cpu_jtag_debug_module_readdata[10] => cpu_jtag_debug_module_readdata_from_sa[10].DATAIN
cpu_jtag_debug_module_readdata[11] => cpu_jtag_debug_module_readdata_from_sa[11].DATAIN
cpu_jtag_debug_module_readdata[12] => cpu_jtag_debug_module_readdata_from_sa[12].DATAIN
cpu_jtag_debug_module_readdata[13] => cpu_jtag_debug_module_readdata_from_sa[13].DATAIN
cpu_jtag_debug_module_readdata[14] => cpu_jtag_debug_module_readdata_from_sa[14].DATAIN
cpu_jtag_debug_module_readdata[15] => cpu_jtag_debug_module_readdata_from_sa[15].DATAIN
cpu_jtag_debug_module_readdata[16] => cpu_jtag_debug_module_readdata_from_sa[16].DATAIN
cpu_jtag_debug_module_readdata[17] => cpu_jtag_debug_module_readdata_from_sa[17].DATAIN
cpu_jtag_debug_module_readdata[18] => cpu_jtag_debug_module_readdata_from_sa[18].DATAIN
cpu_jtag_debug_module_readdata[19] => cpu_jtag_debug_module_readdata_from_sa[19].DATAIN
cpu_jtag_debug_module_readdata[20] => cpu_jtag_debug_module_readdata_from_sa[20].DATAIN
cpu_jtag_debug_module_readdata[21] => cpu_jtag_debug_module_readdata_from_sa[21].DATAIN
cpu_jtag_debug_module_readdata[22] => cpu_jtag_debug_module_readdata_from_sa[22].DATAIN
cpu_jtag_debug_module_readdata[23] => cpu_jtag_debug_module_readdata_from_sa[23].DATAIN
cpu_jtag_debug_module_readdata[24] => cpu_jtag_debug_module_readdata_from_sa[24].DATAIN
cpu_jtag_debug_module_readdata[25] => cpu_jtag_debug_module_readdata_from_sa[25].DATAIN
cpu_jtag_debug_module_readdata[26] => cpu_jtag_debug_module_readdata_from_sa[26].DATAIN
cpu_jtag_debug_module_readdata[27] => cpu_jtag_debug_module_readdata_from_sa[27].DATAIN
cpu_jtag_debug_module_readdata[28] => cpu_jtag_debug_module_readdata_from_sa[28].DATAIN
cpu_jtag_debug_module_readdata[29] => cpu_jtag_debug_module_readdata_from_sa[29].DATAIN
cpu_jtag_debug_module_readdata[30] => cpu_jtag_debug_module_readdata_from_sa[30].DATAIN
cpu_jtag_debug_module_readdata[31] => cpu_jtag_debug_module_readdata_from_sa[31].DATAIN
cpu_jtag_debug_module_resetrequest => cpu_jtag_debug_module_resetrequest_from_sa.DATAIN
reset_n => cpu_jtag_debug_module_reset_n.DATAIN
reset_n => d1_cpu_jtag_debug_module_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR
reset_n => cpu_jtag_debug_module_arb_share_counter[0].ACLR
reset_n => cpu_jtag_debug_module_arb_share_counter[1].ACLR
reset_n => cpu_jtag_debug_module_slavearbiterlockenable.ACLR
reset_n => last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module.ACLR
reset_n => last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module.ACLR
reset_n => cpu_jtag_debug_module_saved_chosen_master_vector[0].ACLR
reset_n => cpu_jtag_debug_module_saved_chosen_master_vector[1].ACLR
reset_n => cpu_jtag_debug_module_arb_addend[0].PRESET
reset_n => cpu_jtag_debug_module_arb_addend[1].ACLR
reset_n => cpu_jtag_debug_module_reg_firsttransfer.PRESET


|LED_hello_world|CORE_SOPC:inst|cpu_data_master_arbitrator:the_cpu_data_master
bl_n_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN0
bl_n_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN0
bl_p_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN0
clk => cpu_data_master_dbs_address[0]~reg0.CLK
clk => cpu_data_master_dbs_address[1]~reg0.CLK
clk => dbs_16_reg_segment_0[0].CLK
clk => dbs_16_reg_segment_0[1].CLK
clk => dbs_16_reg_segment_0[2].CLK
clk => dbs_16_reg_segment_0[3].CLK
clk => dbs_16_reg_segment_0[4].CLK
clk => dbs_16_reg_segment_0[5].CLK
clk => dbs_16_reg_segment_0[6].CLK
clk => dbs_16_reg_segment_0[7].CLK
clk => dbs_16_reg_segment_0[8].CLK
clk => dbs_16_reg_segment_0[9].CLK
clk => dbs_16_reg_segment_0[10].CLK
clk => dbs_16_reg_segment_0[11].CLK
clk => dbs_16_reg_segment_0[12].CLK
clk => dbs_16_reg_segment_0[13].CLK
clk => dbs_16_reg_segment_0[14].CLK
clk => dbs_16_reg_segment_0[15].CLK
clk => cpu_data_master_no_byte_enables_and_last_term~reg0.CLK
clk => registered_cpu_data_master_readdata[0].CLK
clk => registered_cpu_data_master_readdata[1].CLK
clk => registered_cpu_data_master_readdata[2].CLK
clk => registered_cpu_data_master_readdata[3].CLK
clk => registered_cpu_data_master_readdata[4].CLK
clk => registered_cpu_data_master_readdata[5].CLK
clk => registered_cpu_data_master_readdata[6].CLK
clk => registered_cpu_data_master_readdata[7].CLK
clk => registered_cpu_data_master_readdata[8].CLK
clk => registered_cpu_data_master_readdata[9].CLK
clk => registered_cpu_data_master_readdata[10].CLK
clk => registered_cpu_data_master_readdata[11].CLK
clk => registered_cpu_data_master_readdata[12].CLK
clk => registered_cpu_data_master_readdata[13].CLK
clk => registered_cpu_data_master_readdata[14].CLK
clk => registered_cpu_data_master_readdata[15].CLK
clk => registered_cpu_data_master_readdata[16].CLK
clk => registered_cpu_data_master_readdata[17].CLK
clk => registered_cpu_data_master_readdata[18].CLK
clk => registered_cpu_data_master_readdata[19].CLK
clk => registered_cpu_data_master_readdata[20].CLK
clk => registered_cpu_data_master_readdata[21].CLK
clk => registered_cpu_data_master_readdata[22].CLK
clk => registered_cpu_data_master_readdata[23].CLK
clk => registered_cpu_data_master_readdata[24].CLK
clk => registered_cpu_data_master_readdata[25].CLK
clk => registered_cpu_data_master_readdata[26].CLK
clk => registered_cpu_data_master_readdata[27].CLK
clk => registered_cpu_data_master_readdata[28].CLK
clk => registered_cpu_data_master_readdata[29].CLK
clk => registered_cpu_data_master_readdata[30].CLK
clk => registered_cpu_data_master_readdata[31].CLK
clk => cpu_data_master_waitrequest~reg0.CLK
cpu_data_master_address[0] => cpu_data_master_address_to_slave[0].DATAIN
cpu_data_master_address[1] => cpu_data_master_address_to_slave[1].DATAIN
cpu_data_master_address[2] => cpu_data_master_address_to_slave[2].DATAIN
cpu_data_master_address[3] => cpu_data_master_address_to_slave[3].DATAIN
cpu_data_master_address[4] => cpu_data_master_address_to_slave[4].DATAIN
cpu_data_master_address[5] => cpu_data_master_address_to_slave[5].DATAIN
cpu_data_master_address[6] => cpu_data_master_address_to_slave[6].DATAIN
cpu_data_master_address[7] => cpu_data_master_address_to_slave[7].DATAIN
cpu_data_master_address[8] => cpu_data_master_address_to_slave[8].DATAIN
cpu_data_master_address[9] => cpu_data_master_address_to_slave[9].DATAIN
cpu_data_master_address[10] => cpu_data_master_address_to_slave[10].DATAIN
cpu_data_master_address[11] => cpu_data_master_address_to_slave[11].DATAIN
cpu_data_master_address[12] => cpu_data_master_address_to_slave[12].DATAIN
cpu_data_master_address[13] => cpu_data_master_address_to_slave[13].DATAIN
cpu_data_master_address[14] => cpu_data_master_address_to_slave[14].DATAIN
cpu_data_master_address[15] => cpu_data_master_address_to_slave[15].DATAIN
cpu_data_master_address[16] => cpu_data_master_address_to_slave[16].DATAIN
cpu_data_master_address[17] => cpu_data_master_address_to_slave[17].DATAIN
cpu_data_master_address[18] => cpu_data_master_address_to_slave[18].DATAIN
cpu_data_master_address[19] => cpu_data_master_address_to_slave[19].DATAIN
cpu_data_master_address[20] => cpu_data_master_address_to_slave[20].DATAIN
cpu_data_master_address[21] => cpu_data_master_address_to_slave[21].DATAIN
cpu_data_master_address[22] => cpu_data_master_address_to_slave[22].DATAIN
cpu_data_master_address[23] => cpu_data_master_address_to_slave[23].DATAIN
cpu_data_master_address[24] => cpu_data_master_address_to_slave[24].DATAIN
cpu_data_master_address[25] => ~NO_FANOUT~
cpu_data_master_address[26] => cpu_data_master_address_to_slave[26].DATAIN
cpu_data_master_byteenable_sdram_s1[0] => WideNor0.IN0
cpu_data_master_byteenable_sdram_s1[1] => WideNor0.IN1
cpu_data_master_granted_bl_n_s1 => ~NO_FANOUT~
cpu_data_master_granted_bl_p_s1 => ~NO_FANOUT~
cpu_data_master_granted_cpu_jtag_debug_module => r_0.IN0
cpu_data_master_granted_epcs_epcs_control_port => r_0.IN0
cpu_data_master_granted_jtag_uart_avalon_jtag_slave => ~NO_FANOUT~
cpu_data_master_granted_lcd32_data_s1 => ~NO_FANOUT~
cpu_data_master_granted_lcd_cs_s1 => ~NO_FANOUT~
cpu_data_master_granted_lcd_rd_s1 => ~NO_FANOUT~
cpu_data_master_granted_lcd_rs_s1 => ~NO_FANOUT~
cpu_data_master_granted_lcd_wr_s1 => ~NO_FANOUT~
cpu_data_master_granted_reset_s1 => ~NO_FANOUT~
cpu_data_master_granted_sdram_s1 => r_2.IN0
cpu_data_master_granted_sdram_s1 => pre_dbs_count_enable.IN0
cpu_data_master_granted_spi_touch_spi_control_port => ~NO_FANOUT~
cpu_data_master_granted_sysid_control_slave => ~NO_FANOUT~
cpu_data_master_granted_touch_cs_s1 => ~NO_FANOUT~
cpu_data_master_granted_touch_irq_s1 => ~NO_FANOUT~
cpu_data_master_qualified_request_bl_n_s1 => r_0.IN0
cpu_data_master_qualified_request_bl_n_s1 => r_0.IN0
cpu_data_master_qualified_request_bl_n_s1 => r_0.IN0
cpu_data_master_qualified_request_bl_p_s1 => r_0.IN0
cpu_data_master_qualified_request_bl_p_s1 => r_0.IN0
cpu_data_master_qualified_request_bl_p_s1 => r_0.IN0
cpu_data_master_qualified_request_cpu_jtag_debug_module => r_0.IN0
cpu_data_master_qualified_request_cpu_jtag_debug_module => r_0.IN0
cpu_data_master_qualified_request_cpu_jtag_debug_module => r_0.IN0
cpu_data_master_qualified_request_cpu_jtag_debug_module => r_0.IN1
cpu_data_master_qualified_request_epcs_epcs_control_port => r_0.IN0
cpu_data_master_qualified_request_epcs_epcs_control_port => r_0.IN1
cpu_data_master_qualified_request_epcs_epcs_control_port => r_0.IN1
cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave => r_0.IN0
cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave => r_1.IN1
cpu_data_master_qualified_request_lcd32_data_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd32_data_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd32_data_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_cs_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_cs_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_cs_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_rd_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_rd_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_rd_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_rs_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_rs_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_rs_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_wr_s1 => r_1.IN0
cpu_data_master_qualified_request_lcd_wr_s1 => r_2.IN0
cpu_data_master_qualified_request_lcd_wr_s1 => r_2.IN0
cpu_data_master_qualified_request_reset_s1 => r_2.IN0
cpu_data_master_qualified_request_reset_s1 => r_2.IN0
cpu_data_master_qualified_request_reset_s1 => r_2.IN0
cpu_data_master_qualified_request_sdram_s1 => r_2.IN1
cpu_data_master_qualified_request_sdram_s1 => r_2.IN0
cpu_data_master_qualified_request_sdram_s1 => r_2.IN0
cpu_data_master_qualified_request_sdram_s1 => r_2.IN1
cpu_data_master_qualified_request_spi_touch_spi_control_port => r_2.IN1
cpu_data_master_qualified_request_sysid_control_slave => r_2.IN0
cpu_data_master_qualified_request_sysid_control_slave => r_2.IN0
cpu_data_master_qualified_request_touch_cs_s1 => r_2.IN0
cpu_data_master_qualified_request_touch_cs_s1 => r_3.IN0
cpu_data_master_qualified_request_touch_cs_s1 => r_2.IN0
cpu_data_master_qualified_request_touch_irq_s1 => r_3.IN0
cpu_data_master_qualified_request_touch_irq_s1 => r_3.IN0
cpu_data_master_read => r_0.IN1
cpu_data_master_read => r_0.IN1
cpu_data_master_read => r_0.IN1
cpu_data_master_read => r_1.IN1
cpu_data_master_read => r_1.IN1
cpu_data_master_read => r_1.IN1
cpu_data_master_read => r_1.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_2.IN0
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_3.IN1
cpu_data_master_read => r_3.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_2.IN1
cpu_data_master_read => r_1.IN1
cpu_data_master_read => r_1.IN1
cpu_data_master_read => r_1.IN1
cpu_data_master_read => r_1.IN1
cpu_data_master_read => r_0.IN1
cpu_data_master_read => r_0.IN1
cpu_data_master_read => r_0.IN1
cpu_data_master_read_data_valid_bl_n_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_bl_p_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_cpu_jtag_debug_module => ~NO_FANOUT~
cpu_data_master_read_data_valid_epcs_epcs_control_port => ~NO_FANOUT~
cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave => ~NO_FANOUT~
cpu_data_master_read_data_valid_lcd32_data_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_lcd_cs_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_lcd_rd_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_lcd_rs_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_lcd_wr_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_reset_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_sdram_s1 => r_2.IN1
cpu_data_master_read_data_valid_sdram_s1 => pre_dbs_count_enable.IN1
cpu_data_master_read_data_valid_sdram_s1_shift_register => ~NO_FANOUT~
cpu_data_master_read_data_valid_spi_touch_spi_control_port => ~NO_FANOUT~
cpu_data_master_read_data_valid_sysid_control_slave => ~NO_FANOUT~
cpu_data_master_read_data_valid_touch_cs_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_touch_irq_s1 => ~NO_FANOUT~
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_n_s1 => r_0.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_bl_p_s1 => r_0.IN1
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => cpu_data_master_readdata.IN0
cpu_data_master_requests_cpu_jtag_debug_module => r_0.IN1
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_epcs_epcs_control_port => r_0.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => cpu_data_master_readdata.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => r_0.IN1
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_jtag_uart_avalon_jtag_slave => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd32_data_s1 => r_1.IN1
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_cs_s1 => r_1.IN1
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rd_s1 => r_1.IN1
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_rs_s1 => r_1.IN1
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_lcd_wr_s1 => r_1.IN1
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_reset_s1 => r_2.IN1
cpu_data_master_requests_sdram_s1 => pre_dbs_count_enable.IN1
cpu_data_master_requests_sdram_s1 => dbs_count_enable.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => r_2.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN1
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => p1_registered_cpu_data_master_readdata.IN0
cpu_data_master_requests_sdram_s1 => Add0.IN4
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN0
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_spi_touch_spi_control_port => cpu_data_master_readdata.IN1
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_sysid_control_slave => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_cs_s1 => r_2.IN1
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_requests_touch_irq_s1 => cpu_data_master_readdata.IN0
cpu_data_master_write => r_0.IN1
cpu_data_master_write => r_0.IN1
cpu_data_master_write => r_0.IN1
cpu_data_master_write => r_1.IN1
cpu_data_master_write => r_1.IN1
cpu_data_master_write => r_1.IN1
cpu_data_master_write => r_1.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_3.IN1
cpu_data_master_write => r_3.IN1
cpu_data_master_write => last_dbs_term_and_run.IN1
cpu_data_master_write => pre_dbs_count_enable.IN1
cpu_data_master_write => pre_dbs_count_enable.IN1
cpu_data_master_write => r_3.IN1
cpu_data_master_write => r_3.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_2.IN1
cpu_data_master_write => r_1.IN1
cpu_data_master_write => r_1.IN1
cpu_data_master_write => r_1.IN1
cpu_data_master_write => r_1.IN1
cpu_data_master_write => r_0.IN1
cpu_data_master_write => r_0.IN1
cpu_data_master_write => r_0.IN1
cpu_data_master_writedata[0] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[1] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[2] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[3] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[4] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[5] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[6] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[7] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[8] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[9] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[10] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[11] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[12] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[13] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[14] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[15] => cpu_data_master_dbs_write_16.DATAA
cpu_data_master_writedata[16] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[17] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[18] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[19] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[20] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[21] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[22] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[23] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[24] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[25] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[26] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[27] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[28] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[29] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[30] => cpu_data_master_dbs_write_16.DATAB
cpu_data_master_writedata[31] => cpu_data_master_dbs_write_16.DATAB
cpu_jtag_debug_module_readdata_from_sa[0] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[1] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[2] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[3] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[4] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[5] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[6] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[7] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[8] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[9] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[10] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[11] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[12] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[13] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[14] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[15] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[16] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[17] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[18] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[19] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[20] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[21] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[22] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[23] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[24] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[25] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[26] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[27] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[28] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[29] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[30] => cpu_data_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[31] => cpu_data_master_readdata.IN1
d1_bl_n_s1_end_xfer => ~NO_FANOUT~
d1_bl_p_s1_end_xfer => ~NO_FANOUT~
d1_cpu_jtag_debug_module_end_xfer => ~NO_FANOUT~
d1_epcs_epcs_control_port_end_xfer => ~NO_FANOUT~
d1_jtag_uart_avalon_jtag_slave_end_xfer => ~NO_FANOUT~
d1_lcd32_data_s1_end_xfer => ~NO_FANOUT~
d1_lcd_cs_s1_end_xfer => ~NO_FANOUT~
d1_lcd_rd_s1_end_xfer => ~NO_FANOUT~
d1_lcd_rs_s1_end_xfer => ~NO_FANOUT~
d1_lcd_wr_s1_end_xfer => ~NO_FANOUT~
d1_reset_s1_end_xfer => ~NO_FANOUT~
d1_sdram_s1_end_xfer => ~NO_FANOUT~
d1_spi_touch_spi_control_port_end_xfer => ~NO_FANOUT~
d1_sysid_control_slave_end_xfer => ~NO_FANOUT~
d1_touch_cs_s1_end_xfer => ~NO_FANOUT~
d1_touch_irq_s1_end_xfer => ~NO_FANOUT~
epcs_epcs_control_port_irq_from_sa => cpu_data_master_irq[0].DATAIN
epcs_epcs_control_port_readdata_from_sa[0] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[1] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[2] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[3] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[4] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[5] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[6] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[7] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[8] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[9] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[10] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[11] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[12] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[13] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[14] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[15] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[16] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[17] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[18] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[19] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[20] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[21] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[22] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[23] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[24] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[25] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[26] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[27] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[28] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[29] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[30] => cpu_data_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[31] => cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_irq_from_sa => cpu_data_master_irq[1].DATAIN
jtag_uart_avalon_jtag_slave_readdata_from_sa[0] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[1] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[2] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[3] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[4] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[5] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[6] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[7] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[8] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[9] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[10] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[11] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[12] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[13] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[14] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[15] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[16] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[17] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[18] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[19] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[20] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[21] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[22] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[23] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[24] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[25] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[26] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[27] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[28] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[29] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[30] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_readdata_from_sa[31] => p1_registered_cpu_data_master_readdata.IN1
jtag_uart_avalon_jtag_slave_waitrequest_from_sa => r_1.IN1
lcd32_data_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN1
lcd32_data_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN1
lcd_cs_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN1
lcd_rd_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN1
lcd_rs_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN1
lcd_wr_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN1
reset_n => registered_cpu_data_master_readdata[0].ACLR
reset_n => registered_cpu_data_master_readdata[1].ACLR
reset_n => registered_cpu_data_master_readdata[2].ACLR
reset_n => registered_cpu_data_master_readdata[3].ACLR
reset_n => registered_cpu_data_master_readdata[4].ACLR
reset_n => registered_cpu_data_master_readdata[5].ACLR
reset_n => registered_cpu_data_master_readdata[6].ACLR
reset_n => registered_cpu_data_master_readdata[7].ACLR
reset_n => registered_cpu_data_master_readdata[8].ACLR
reset_n => registered_cpu_data_master_readdata[9].ACLR
reset_n => registered_cpu_data_master_readdata[10].ACLR
reset_n => registered_cpu_data_master_readdata[11].ACLR
reset_n => registered_cpu_data_master_readdata[12].ACLR
reset_n => registered_cpu_data_master_readdata[13].ACLR
reset_n => registered_cpu_data_master_readdata[14].ACLR
reset_n => registered_cpu_data_master_readdata[15].ACLR
reset_n => registered_cpu_data_master_readdata[16].ACLR
reset_n => registered_cpu_data_master_readdata[17].ACLR
reset_n => registered_cpu_data_master_readdata[18].ACLR
reset_n => registered_cpu_data_master_readdata[19].ACLR
reset_n => registered_cpu_data_master_readdata[20].ACLR
reset_n => registered_cpu_data_master_readdata[21].ACLR
reset_n => registered_cpu_data_master_readdata[22].ACLR
reset_n => registered_cpu_data_master_readdata[23].ACLR
reset_n => registered_cpu_data_master_readdata[24].ACLR
reset_n => registered_cpu_data_master_readdata[25].ACLR
reset_n => registered_cpu_data_master_readdata[26].ACLR
reset_n => registered_cpu_data_master_readdata[27].ACLR
reset_n => registered_cpu_data_master_readdata[28].ACLR
reset_n => registered_cpu_data_master_readdata[29].ACLR
reset_n => registered_cpu_data_master_readdata[30].ACLR
reset_n => registered_cpu_data_master_readdata[31].ACLR
reset_n => cpu_data_master_dbs_address[0]~reg0.ACLR
reset_n => cpu_data_master_dbs_address[1]~reg0.ACLR
reset_n => cpu_data_master_no_byte_enables_and_last_term~reg0.ACLR
reset_n => cpu_data_master_waitrequest~reg0.PRESET
reset_n => dbs_16_reg_segment_0[0].ACLR
reset_n => dbs_16_reg_segment_0[1].ACLR
reset_n => dbs_16_reg_segment_0[2].ACLR
reset_n => dbs_16_reg_segment_0[3].ACLR
reset_n => dbs_16_reg_segment_0[4].ACLR
reset_n => dbs_16_reg_segment_0[5].ACLR
reset_n => dbs_16_reg_segment_0[6].ACLR
reset_n => dbs_16_reg_segment_0[7].ACLR
reset_n => dbs_16_reg_segment_0[8].ACLR
reset_n => dbs_16_reg_segment_0[9].ACLR
reset_n => dbs_16_reg_segment_0[10].ACLR
reset_n => dbs_16_reg_segment_0[11].ACLR
reset_n => dbs_16_reg_segment_0[12].ACLR
reset_n => dbs_16_reg_segment_0[13].ACLR
reset_n => dbs_16_reg_segment_0[14].ACLR
reset_n => dbs_16_reg_segment_0[15].ACLR
reset_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN1
reset_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[0] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[0] => dbs_16_reg_segment_0[0].DATAIN
sdram_s1_readdata_from_sa[1] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[1] => dbs_16_reg_segment_0[1].DATAIN
sdram_s1_readdata_from_sa[2] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[2] => dbs_16_reg_segment_0[2].DATAIN
sdram_s1_readdata_from_sa[3] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[3] => dbs_16_reg_segment_0[3].DATAIN
sdram_s1_readdata_from_sa[4] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[4] => dbs_16_reg_segment_0[4].DATAIN
sdram_s1_readdata_from_sa[5] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[5] => dbs_16_reg_segment_0[5].DATAIN
sdram_s1_readdata_from_sa[6] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[6] => dbs_16_reg_segment_0[6].DATAIN
sdram_s1_readdata_from_sa[7] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[7] => dbs_16_reg_segment_0[7].DATAIN
sdram_s1_readdata_from_sa[8] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[8] => dbs_16_reg_segment_0[8].DATAIN
sdram_s1_readdata_from_sa[9] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[9] => dbs_16_reg_segment_0[9].DATAIN
sdram_s1_readdata_from_sa[10] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[10] => dbs_16_reg_segment_0[10].DATAIN
sdram_s1_readdata_from_sa[11] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[11] => dbs_16_reg_segment_0[11].DATAIN
sdram_s1_readdata_from_sa[12] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[12] => dbs_16_reg_segment_0[12].DATAIN
sdram_s1_readdata_from_sa[13] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[13] => dbs_16_reg_segment_0[13].DATAIN
sdram_s1_readdata_from_sa[14] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[14] => dbs_16_reg_segment_0[14].DATAIN
sdram_s1_readdata_from_sa[15] => p1_registered_cpu_data_master_readdata.IN1
sdram_s1_readdata_from_sa[15] => dbs_16_reg_segment_0[15].DATAIN
sdram_s1_waitrequest_from_sa => pre_dbs_count_enable.IN1
sdram_s1_waitrequest_from_sa => r_2.IN1
spi_touch_spi_control_port_irq_from_sa => cpu_data_master_irq[2].DATAIN
spi_touch_spi_control_port_readdata_from_sa[0] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[1] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[2] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[3] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[4] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[5] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[6] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[7] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[8] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[9] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[10] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[11] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[12] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[13] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[14] => cpu_data_master_readdata.IN1
spi_touch_spi_control_port_readdata_from_sa[15] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[0] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[1] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[2] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[3] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[4] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[5] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[6] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[7] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[8] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[9] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[10] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[11] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[12] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[13] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[14] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[15] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[16] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[17] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[18] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[19] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[20] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[21] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[22] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[23] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[24] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[25] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[26] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[27] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[28] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[29] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[30] => cpu_data_master_readdata.IN1
sysid_control_slave_readdata_from_sa[31] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN1
touch_cs_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[0] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[1] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[2] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[3] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[4] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[5] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[6] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[7] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[8] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[9] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[10] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[11] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[12] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[13] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[14] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[15] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[16] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[17] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[18] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[19] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[20] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[21] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[22] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[23] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[24] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[25] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[26] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[27] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[28] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[29] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[30] => cpu_data_master_readdata.IN1
touch_irq_s1_readdata_from_sa[31] => cpu_data_master_readdata.IN1


|LED_hello_world|CORE_SOPC:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master
clk => cpu_instruction_master_dbs_rdv_counter[0].CLK
clk => cpu_instruction_master_dbs_rdv_counter[1].CLK
clk => cpu_instruction_master_dbs_address[0]~reg0.CLK
clk => cpu_instruction_master_dbs_address[1]~reg0.CLK
clk => dbs_latent_16_reg_segment_0[0].CLK
clk => dbs_latent_16_reg_segment_0[1].CLK
clk => dbs_latent_16_reg_segment_0[2].CLK
clk => dbs_latent_16_reg_segment_0[3].CLK
clk => dbs_latent_16_reg_segment_0[4].CLK
clk => dbs_latent_16_reg_segment_0[5].CLK
clk => dbs_latent_16_reg_segment_0[6].CLK
clk => dbs_latent_16_reg_segment_0[7].CLK
clk => dbs_latent_16_reg_segment_0[8].CLK
clk => dbs_latent_16_reg_segment_0[9].CLK
clk => dbs_latent_16_reg_segment_0[10].CLK
clk => dbs_latent_16_reg_segment_0[11].CLK
clk => dbs_latent_16_reg_segment_0[12].CLK
clk => dbs_latent_16_reg_segment_0[13].CLK
clk => dbs_latent_16_reg_segment_0[14].CLK
clk => dbs_latent_16_reg_segment_0[15].CLK
clk => cpu_instruction_master_latency_counter~reg0.CLK
clk => cpu_instruction_master_read_but_no_slave_selected.CLK
cpu_instruction_master_address[0] => cpu_instruction_master_address_to_slave[0].DATAIN
cpu_instruction_master_address[1] => cpu_instruction_master_address_to_slave[1].DATAIN
cpu_instruction_master_address[2] => cpu_instruction_master_address_to_slave[2].DATAIN
cpu_instruction_master_address[3] => cpu_instruction_master_address_to_slave[3].DATAIN
cpu_instruction_master_address[4] => cpu_instruction_master_address_to_slave[4].DATAIN
cpu_instruction_master_address[5] => cpu_instruction_master_address_to_slave[5].DATAIN
cpu_instruction_master_address[6] => cpu_instruction_master_address_to_slave[6].DATAIN
cpu_instruction_master_address[7] => cpu_instruction_master_address_to_slave[7].DATAIN
cpu_instruction_master_address[8] => cpu_instruction_master_address_to_slave[8].DATAIN
cpu_instruction_master_address[9] => cpu_instruction_master_address_to_slave[9].DATAIN
cpu_instruction_master_address[10] => cpu_instruction_master_address_to_slave[10].DATAIN
cpu_instruction_master_address[11] => cpu_instruction_master_address_to_slave[11].DATAIN
cpu_instruction_master_address[12] => cpu_instruction_master_address_to_slave[12].DATAIN
cpu_instruction_master_address[13] => cpu_instruction_master_address_to_slave[13].DATAIN
cpu_instruction_master_address[14] => cpu_instruction_master_address_to_slave[14].DATAIN
cpu_instruction_master_address[15] => cpu_instruction_master_address_to_slave[15].DATAIN
cpu_instruction_master_address[16] => cpu_instruction_master_address_to_slave[16].DATAIN
cpu_instruction_master_address[17] => cpu_instruction_master_address_to_slave[17].DATAIN
cpu_instruction_master_address[18] => cpu_instruction_master_address_to_slave[18].DATAIN
cpu_instruction_master_address[19] => cpu_instruction_master_address_to_slave[19].DATAIN
cpu_instruction_master_address[20] => cpu_instruction_master_address_to_slave[20].DATAIN
cpu_instruction_master_address[21] => cpu_instruction_master_address_to_slave[21].DATAIN
cpu_instruction_master_address[22] => cpu_instruction_master_address_to_slave[22].DATAIN
cpu_instruction_master_address[23] => cpu_instruction_master_address_to_slave[23].DATAIN
cpu_instruction_master_address[24] => cpu_instruction_master_address_to_slave[24].DATAIN
cpu_instruction_master_address[25] => ~NO_FANOUT~
cpu_instruction_master_address[26] => cpu_instruction_master_address_to_slave[26].DATAIN
cpu_instruction_master_granted_cpu_jtag_debug_module => r_0.IN0
cpu_instruction_master_granted_cpu_jtag_debug_module => cpu_instruction_master_is_granted_some_slave.IN0
cpu_instruction_master_granted_epcs_epcs_control_port => r_0.IN0
cpu_instruction_master_granted_epcs_epcs_control_port => cpu_instruction_master_is_granted_some_slave.IN1
cpu_instruction_master_granted_sdram_s1 => r_2.IN0
cpu_instruction_master_granted_sdram_s1 => cpu_instruction_master_is_granted_some_slave.IN1
cpu_instruction_master_granted_sdram_s1 => pre_dbs_count_enable.IN0
cpu_instruction_master_qualified_request_cpu_jtag_debug_module => r_0.IN0
cpu_instruction_master_qualified_request_cpu_jtag_debug_module => cpu_instruction_master_readdata.IN0
cpu_instruction_master_qualified_request_cpu_jtag_debug_module => r_0.IN0
cpu_instruction_master_qualified_request_cpu_jtag_debug_module => r_0.IN1
cpu_instruction_master_qualified_request_epcs_epcs_control_port => r_0.IN0
cpu_instruction_master_qualified_request_epcs_epcs_control_port => cpu_instruction_master_readdata.IN0
cpu_instruction_master_qualified_request_epcs_epcs_control_port => r_0.IN0
cpu_instruction_master_qualified_request_epcs_epcs_control_port => r_0.IN1
cpu_instruction_master_qualified_request_sdram_s1 => r_2.IN0
cpu_instruction_master_qualified_request_sdram_s1 => r_2.IN0
cpu_instruction_master_qualified_request_sdram_s1 => r_2.IN1
cpu_instruction_master_read => r_0.IN0
cpu_instruction_master_read => r_0.IN0
cpu_instruction_master_read => r_2.IN1
cpu_instruction_master_read => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read => p1_cpu_instruction_master_latency_counter.IN1
cpu_instruction_master_read => pre_dbs_count_enable.IN1
cpu_instruction_master_read => r_2.IN1
cpu_instruction_master_read => r_0.IN1
cpu_instruction_master_read => r_0.IN1
cpu_instruction_master_read_data_valid_cpu_jtag_debug_module => cpu_instruction_master_readdatavalid.IN1
cpu_instruction_master_read_data_valid_epcs_epcs_control_port => cpu_instruction_master_readdatavalid.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => always2.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => pre_flush_cpu_instruction_master_readdatavalid.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN1
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_readdata.IN0
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_dbs_rdv_counter[0].ENA
cpu_instruction_master_read_data_valid_sdram_s1 => cpu_instruction_master_dbs_rdv_counter[1].ENA
cpu_instruction_master_read_data_valid_sdram_s1_shift_register => ~NO_FANOUT~
cpu_instruction_master_requests_cpu_jtag_debug_module => r_0.IN1
cpu_instruction_master_requests_epcs_epcs_control_port => r_0.IN1
cpu_instruction_master_requests_sdram_s1 => r_2.IN1
cpu_instruction_master_requests_sdram_s1 => Add1.IN4
cpu_jtag_debug_module_readdata_from_sa[0] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[1] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[2] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[3] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[4] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[5] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[6] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[7] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[8] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[9] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[10] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[11] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[12] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[13] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[14] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[15] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[16] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[17] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[18] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[19] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[20] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[21] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[22] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[23] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[24] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[25] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[26] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[27] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[28] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[29] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[30] => cpu_instruction_master_readdata.IN1
cpu_jtag_debug_module_readdata_from_sa[31] => cpu_instruction_master_readdata.IN1
d1_cpu_jtag_debug_module_end_xfer => r_0.IN1
d1_epcs_epcs_control_port_end_xfer => r_0.IN1
d1_sdram_s1_end_xfer => ~NO_FANOUT~
epcs_epcs_control_port_readdata_from_sa[0] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[1] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[2] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[3] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[4] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[5] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[6] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[7] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[8] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[9] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[10] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[11] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[12] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[13] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[14] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[15] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[16] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[17] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[18] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[19] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[20] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[21] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[22] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[23] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[24] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[25] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[26] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[27] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[28] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[29] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[30] => cpu_instruction_master_readdata.IN1
epcs_epcs_control_port_readdata_from_sa[31] => cpu_instruction_master_readdata.IN1
reset_n => dbs_latent_16_reg_segment_0[0].ACLR
reset_n => dbs_latent_16_reg_segment_0[1].ACLR
reset_n => dbs_latent_16_reg_segment_0[2].ACLR
reset_n => dbs_latent_16_reg_segment_0[3].ACLR
reset_n => dbs_latent_16_reg_segment_0[4].ACLR
reset_n => dbs_latent_16_reg_segment_0[5].ACLR
reset_n => dbs_latent_16_reg_segment_0[6].ACLR
reset_n => dbs_latent_16_reg_segment_0[7].ACLR
reset_n => dbs_latent_16_reg_segment_0[8].ACLR
reset_n => dbs_latent_16_reg_segment_0[9].ACLR
reset_n => dbs_latent_16_reg_segment_0[10].ACLR
reset_n => dbs_latent_16_reg_segment_0[11].ACLR
reset_n => dbs_latent_16_reg_segment_0[12].ACLR
reset_n => dbs_latent_16_reg_segment_0[13].ACLR
reset_n => dbs_latent_16_reg_segment_0[14].ACLR
reset_n => dbs_latent_16_reg_segment_0[15].ACLR
reset_n => cpu_instruction_master_dbs_address[0]~reg0.ACLR
reset_n => cpu_instruction_master_dbs_address[1]~reg0.ACLR
reset_n => cpu_instruction_master_latency_counter~reg0.ACLR
reset_n => cpu_instruction_master_read_but_no_slave_selected.ACLR
reset_n => cpu_instruction_master_dbs_rdv_counter[0].ACLR
reset_n => cpu_instruction_master_dbs_rdv_counter[1].ACLR
sdram_s1_readdata_from_sa[0] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[0] => dbs_latent_16_reg_segment_0[0].DATAIN
sdram_s1_readdata_from_sa[1] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[1] => dbs_latent_16_reg_segment_0[1].DATAIN
sdram_s1_readdata_from_sa[2] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[2] => dbs_latent_16_reg_segment_0[2].DATAIN
sdram_s1_readdata_from_sa[3] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[3] => dbs_latent_16_reg_segment_0[3].DATAIN
sdram_s1_readdata_from_sa[4] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[4] => dbs_latent_16_reg_segment_0[4].DATAIN
sdram_s1_readdata_from_sa[5] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[5] => dbs_latent_16_reg_segment_0[5].DATAIN
sdram_s1_readdata_from_sa[6] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[6] => dbs_latent_16_reg_segment_0[6].DATAIN
sdram_s1_readdata_from_sa[7] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[7] => dbs_latent_16_reg_segment_0[7].DATAIN
sdram_s1_readdata_from_sa[8] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[8] => dbs_latent_16_reg_segment_0[8].DATAIN
sdram_s1_readdata_from_sa[9] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[9] => dbs_latent_16_reg_segment_0[9].DATAIN
sdram_s1_readdata_from_sa[10] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[10] => dbs_latent_16_reg_segment_0[10].DATAIN
sdram_s1_readdata_from_sa[11] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[11] => dbs_latent_16_reg_segment_0[11].DATAIN
sdram_s1_readdata_from_sa[12] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[12] => dbs_latent_16_reg_segment_0[12].DATAIN
sdram_s1_readdata_from_sa[13] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[13] => dbs_latent_16_reg_segment_0[13].DATAIN
sdram_s1_readdata_from_sa[14] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[14] => dbs_latent_16_reg_segment_0[14].DATAIN
sdram_s1_readdata_from_sa[15] => cpu_instruction_master_readdata.IN1
sdram_s1_readdata_from_sa[15] => dbs_latent_16_reg_segment_0[15].DATAIN
sdram_s1_waitrequest_from_sa => pre_dbs_count_enable.IN1
sdram_s1_waitrequest_from_sa => r_2.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu
clk => clk.IN8
d_irq[0] => A_ipending_reg_irq0_nxt.IN0
d_irq[1] => A_ipending_reg_irq1_nxt.IN0
d_irq[2] => A_ipending_reg_irq2_nxt.IN0
d_irq[3] => ~NO_FANOUT~
d_irq[4] => ~NO_FANOUT~
d_irq[5] => ~NO_FANOUT~
d_irq[6] => ~NO_FANOUT~
d_irq[7] => ~NO_FANOUT~
d_irq[8] => ~NO_FANOUT~
d_irq[9] => ~NO_FANOUT~
d_irq[10] => ~NO_FANOUT~
d_irq[11] => ~NO_FANOUT~
d_irq[12] => ~NO_FANOUT~
d_irq[13] => ~NO_FANOUT~
d_irq[14] => ~NO_FANOUT~
d_irq[15] => ~NO_FANOUT~
d_irq[16] => ~NO_FANOUT~
d_irq[17] => ~NO_FANOUT~
d_irq[18] => ~NO_FANOUT~
d_irq[19] => ~NO_FANOUT~
d_irq[20] => ~NO_FANOUT~
d_irq[21] => ~NO_FANOUT~
d_irq[22] => ~NO_FANOUT~
d_irq[23] => ~NO_FANOUT~
d_irq[24] => ~NO_FANOUT~
d_irq[25] => ~NO_FANOUT~
d_irq[26] => ~NO_FANOUT~
d_irq[27] => ~NO_FANOUT~
d_irq[28] => ~NO_FANOUT~
d_irq[29] => ~NO_FANOUT~
d_irq[30] => ~NO_FANOUT~
d_irq[31] => ~NO_FANOUT~
d_readdata[0] => A_slow_inst_result_nxt[0].DATAB
d_readdata[0] => d_readdata_d1[0].DATAIN
d_readdata[1] => A_slow_inst_result_nxt[1].DATAB
d_readdata[1] => d_readdata_d1[1].DATAIN
d_readdata[2] => A_slow_inst_result_nxt[2].DATAB
d_readdata[2] => d_readdata_d1[2].DATAIN
d_readdata[3] => A_slow_inst_result_nxt[3].DATAB
d_readdata[3] => d_readdata_d1[3].DATAIN
d_readdata[4] => A_slow_inst_result_nxt[4].DATAB
d_readdata[4] => d_readdata_d1[4].DATAIN
d_readdata[5] => A_slow_inst_result_nxt[5].DATAB
d_readdata[5] => d_readdata_d1[5].DATAIN
d_readdata[6] => A_slow_inst_result_nxt[6].DATAB
d_readdata[6] => d_readdata_d1[6].DATAIN
d_readdata[7] => A_slow_inst_result_nxt[7].DATAB
d_readdata[7] => d_readdata_d1[7].DATAIN
d_readdata[8] => A_slow_inst_result_nxt[8].DATAB
d_readdata[8] => d_readdata_d1[8].DATAIN
d_readdata[9] => A_slow_inst_result_nxt[9].DATAB
d_readdata[9] => d_readdata_d1[9].DATAIN
d_readdata[10] => A_slow_inst_result_nxt[10].DATAB
d_readdata[10] => d_readdata_d1[10].DATAIN
d_readdata[11] => A_slow_inst_result_nxt[11].DATAB
d_readdata[11] => d_readdata_d1[11].DATAIN
d_readdata[12] => A_slow_inst_result_nxt[12].DATAB
d_readdata[12] => d_readdata_d1[12].DATAIN
d_readdata[13] => A_slow_inst_result_nxt[13].DATAB
d_readdata[13] => d_readdata_d1[13].DATAIN
d_readdata[14] => A_slow_inst_result_nxt[14].DATAB
d_readdata[14] => d_readdata_d1[14].DATAIN
d_readdata[15] => A_slow_inst_result_nxt[15].DATAB
d_readdata[15] => d_readdata_d1[15].DATAIN
d_readdata[16] => A_slow_inst_result_nxt[16].DATAB
d_readdata[16] => d_readdata_d1[16].DATAIN
d_readdata[17] => A_slow_inst_result_nxt[17].DATAB
d_readdata[17] => d_readdata_d1[17].DATAIN
d_readdata[18] => A_slow_inst_result_nxt[18].DATAB
d_readdata[18] => d_readdata_d1[18].DATAIN
d_readdata[19] => A_slow_inst_result_nxt[19].DATAB
d_readdata[19] => d_readdata_d1[19].DATAIN
d_readdata[20] => A_slow_inst_result_nxt[20].DATAB
d_readdata[20] => d_readdata_d1[20].DATAIN
d_readdata[21] => A_slow_inst_result_nxt[21].DATAB
d_readdata[21] => d_readdata_d1[21].DATAIN
d_readdata[22] => A_slow_inst_result_nxt[22].DATAB
d_readdata[22] => d_readdata_d1[22].DATAIN
d_readdata[23] => A_slow_inst_result_nxt[23].DATAB
d_readdata[23] => d_readdata_d1[23].DATAIN
d_readdata[24] => A_slow_inst_result_nxt[24].DATAB
d_readdata[24] => d_readdata_d1[24].DATAIN
d_readdata[25] => A_slow_inst_result_nxt[25].DATAB
d_readdata[25] => d_readdata_d1[25].DATAIN
d_readdata[26] => A_slow_inst_result_nxt[26].DATAB
d_readdata[26] => d_readdata_d1[26].DATAIN
d_readdata[27] => A_slow_inst_result_nxt[27].DATAB
d_readdata[27] => d_readdata_d1[27].DATAIN
d_readdata[28] => A_slow_inst_result_nxt[28].DATAB
d_readdata[28] => d_readdata_d1[28].DATAIN
d_readdata[29] => A_slow_inst_result_nxt[29].DATAB
d_readdata[29] => d_readdata_d1[29].DATAIN
d_readdata[30] => A_slow_inst_result_nxt[30].DATAB
d_readdata[30] => d_readdata_d1[30].DATAIN
d_readdata[31] => A_slow_inst_result_nxt[31].DATAB
d_readdata[31] => d_readdata_d1[31].DATAIN
d_waitrequest => d_read_nxt.IN0
d_waitrequest => d_write_nxt.IN0
d_waitrequest => A_mem_stall_stop_nxt.DATAB
d_waitrequest => av_rd_data_transfer.IN0
i_readdata[0] => i_readdata_d1[0].DATAIN
i_readdata[1] => i_readdata_d1[1].DATAIN
i_readdata[2] => i_readdata_d1[2].DATAIN
i_readdata[3] => i_readdata_d1[3].DATAIN
i_readdata[4] => i_readdata_d1[4].DATAIN
i_readdata[5] => i_readdata_d1[5].DATAIN
i_readdata[6] => i_readdata_d1[6].DATAIN
i_readdata[7] => i_readdata_d1[7].DATAIN
i_readdata[8] => i_readdata_d1[8].DATAIN
i_readdata[9] => i_readdata_d1[9].DATAIN
i_readdata[10] => i_readdata_d1[10].DATAIN
i_readdata[11] => i_readdata_d1[11].DATAIN
i_readdata[12] => i_readdata_d1[12].DATAIN
i_readdata[13] => i_readdata_d1[13].DATAIN
i_readdata[14] => i_readdata_d1[14].DATAIN
i_readdata[15] => i_readdata_d1[15].DATAIN
i_readdata[16] => i_readdata_d1[16].DATAIN
i_readdata[17] => i_readdata_d1[17].DATAIN
i_readdata[18] => i_readdata_d1[18].DATAIN
i_readdata[19] => i_readdata_d1[19].DATAIN
i_readdata[20] => i_readdata_d1[20].DATAIN
i_readdata[21] => i_readdata_d1[21].DATAIN
i_readdata[22] => i_readdata_d1[22].DATAIN
i_readdata[23] => i_readdata_d1[23].DATAIN
i_readdata[24] => i_readdata_d1[24].DATAIN
i_readdata[25] => i_readdata_d1[25].DATAIN
i_readdata[26] => i_readdata_d1[26].DATAIN
i_readdata[27] => i_readdata_d1[27].DATAIN
i_readdata[28] => i_readdata_d1[28].DATAIN
i_readdata[29] => i_readdata_d1[29].DATAIN
i_readdata[30] => i_readdata_d1[30].DATAIN
i_readdata[31] => i_readdata_d1[31].DATAIN
i_readdatavalid => i_readdatavalid.IN1
i_waitrequest => i_read_nxt.IN1
i_waitrequest => ic_fill_req_accepted.IN0
jtag_debug_module_address[0] => jtag_debug_module_address[0].IN1
jtag_debug_module_address[1] => jtag_debug_module_address[1].IN1
jtag_debug_module_address[2] => jtag_debug_module_address[2].IN1
jtag_debug_module_address[3] => jtag_debug_module_address[3].IN1
jtag_debug_module_address[4] => jtag_debug_module_address[4].IN1
jtag_debug_module_address[5] => jtag_debug_module_address[5].IN1
jtag_debug_module_address[6] => jtag_debug_module_address[6].IN1
jtag_debug_module_address[7] => jtag_debug_module_address[7].IN1
jtag_debug_module_address[8] => jtag_debug_module_address[8].IN1
jtag_debug_module_begintransfer => jtag_debug_module_begintransfer.IN1
jtag_debug_module_byteenable[0] => jtag_debug_module_byteenable[0].IN1
jtag_debug_module_byteenable[1] => jtag_debug_module_byteenable[1].IN1
jtag_debug_module_byteenable[2] => jtag_debug_module_byteenable[2].IN1
jtag_debug_module_byteenable[3] => jtag_debug_module_byteenable[3].IN1
jtag_debug_module_debugaccess => jtag_debug_module_debugaccess.IN1
jtag_debug_module_select => jtag_debug_module_select.IN1
jtag_debug_module_write => jtag_debug_module_write.IN1
jtag_debug_module_writedata[0] => jtag_debug_module_writedata[0].IN1
jtag_debug_module_writedata[1] => jtag_debug_module_writedata[1].IN1
jtag_debug_module_writedata[2] => jtag_debug_module_writedata[2].IN1
jtag_debug_module_writedata[3] => jtag_debug_module_writedata[3].IN1
jtag_debug_module_writedata[4] => jtag_debug_module_writedata[4].IN1
jtag_debug_module_writedata[5] => jtag_debug_module_writedata[5].IN1
jtag_debug_module_writedata[6] => jtag_debug_module_writedata[6].IN1
jtag_debug_module_writedata[7] => jtag_debug_module_writedata[7].IN1
jtag_debug_module_writedata[8] => jtag_debug_module_writedata[8].IN1
jtag_debug_module_writedata[9] => jtag_debug_module_writedata[9].IN1
jtag_debug_module_writedata[10] => jtag_debug_module_writedata[10].IN1
jtag_debug_module_writedata[11] => jtag_debug_module_writedata[11].IN1
jtag_debug_module_writedata[12] => jtag_debug_module_writedata[12].IN1
jtag_debug_module_writedata[13] => jtag_debug_module_writedata[13].IN1
jtag_debug_module_writedata[14] => jtag_debug_module_writedata[14].IN1
jtag_debug_module_writedata[15] => jtag_debug_module_writedata[15].IN1
jtag_debug_module_writedata[16] => jtag_debug_module_writedata[16].IN1
jtag_debug_module_writedata[17] => jtag_debug_module_writedata[17].IN1
jtag_debug_module_writedata[18] => jtag_debug_module_writedata[18].IN1
jtag_debug_module_writedata[19] => jtag_debug_module_writedata[19].IN1
jtag_debug_module_writedata[20] => jtag_debug_module_writedata[20].IN1
jtag_debug_module_writedata[21] => jtag_debug_module_writedata[21].IN1
jtag_debug_module_writedata[22] => jtag_debug_module_writedata[22].IN1
jtag_debug_module_writedata[23] => jtag_debug_module_writedata[23].IN1
jtag_debug_module_writedata[24] => jtag_debug_module_writedata[24].IN1
jtag_debug_module_writedata[25] => jtag_debug_module_writedata[25].IN1
jtag_debug_module_writedata[26] => jtag_debug_module_writedata[26].IN1
jtag_debug_module_writedata[27] => jtag_debug_module_writedata[27].IN1
jtag_debug_module_writedata[28] => jtag_debug_module_writedata[28].IN1
jtag_debug_module_writedata[29] => jtag_debug_module_writedata[29].IN1
jtag_debug_module_writedata[30] => jtag_debug_module_writedata[30].IN1
jtag_debug_module_writedata[31] => jtag_debug_module_writedata[31].IN1
reset_n => reset_n.IN3


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench
A_bstatus_reg[0] => ~NO_FANOUT~
A_bstatus_reg[1] => ~NO_FANOUT~
A_bstatus_reg[2] => ~NO_FANOUT~
A_bstatus_reg[3] => ~NO_FANOUT~
A_bstatus_reg[4] => ~NO_FANOUT~
A_bstatus_reg[5] => ~NO_FANOUT~
A_bstatus_reg[6] => ~NO_FANOUT~
A_bstatus_reg[7] => ~NO_FANOUT~
A_bstatus_reg[8] => ~NO_FANOUT~
A_bstatus_reg[9] => ~NO_FANOUT~
A_bstatus_reg[10] => ~NO_FANOUT~
A_bstatus_reg[11] => ~NO_FANOUT~
A_bstatus_reg[12] => ~NO_FANOUT~
A_bstatus_reg[13] => ~NO_FANOUT~
A_bstatus_reg[14] => ~NO_FANOUT~
A_bstatus_reg[15] => ~NO_FANOUT~
A_bstatus_reg[16] => ~NO_FANOUT~
A_bstatus_reg[17] => ~NO_FANOUT~
A_bstatus_reg[18] => ~NO_FANOUT~
A_bstatus_reg[19] => ~NO_FANOUT~
A_bstatus_reg[20] => ~NO_FANOUT~
A_bstatus_reg[21] => ~NO_FANOUT~
A_bstatus_reg[22] => ~NO_FANOUT~
A_bstatus_reg[23] => ~NO_FANOUT~
A_bstatus_reg[24] => ~NO_FANOUT~
A_bstatus_reg[25] => ~NO_FANOUT~
A_bstatus_reg[26] => ~NO_FANOUT~
A_bstatus_reg[27] => ~NO_FANOUT~
A_bstatus_reg[28] => ~NO_FANOUT~
A_bstatus_reg[29] => ~NO_FANOUT~
A_bstatus_reg[30] => ~NO_FANOUT~
A_bstatus_reg[31] => ~NO_FANOUT~
A_cmp_result => ~NO_FANOUT~
A_ctrl_exception => ~NO_FANOUT~
A_ctrl_ld_non_io => ~NO_FANOUT~
A_dst_regnum[0] => ~NO_FANOUT~
A_dst_regnum[1] => ~NO_FANOUT~
A_dst_regnum[2] => ~NO_FANOUT~
A_dst_regnum[3] => ~NO_FANOUT~
A_dst_regnum[4] => ~NO_FANOUT~
A_en => ~NO_FANOUT~
A_estatus_reg[0] => ~NO_FANOUT~
A_estatus_reg[1] => ~NO_FANOUT~
A_estatus_reg[2] => ~NO_FANOUT~
A_estatus_reg[3] => ~NO_FANOUT~
A_estatus_reg[4] => ~NO_FANOUT~
A_estatus_reg[5] => ~NO_FANOUT~
A_estatus_reg[6] => ~NO_FANOUT~
A_estatus_reg[7] => ~NO_FANOUT~
A_estatus_reg[8] => ~NO_FANOUT~
A_estatus_reg[9] => ~NO_FANOUT~
A_estatus_reg[10] => ~NO_FANOUT~
A_estatus_reg[11] => ~NO_FANOUT~
A_estatus_reg[12] => ~NO_FANOUT~
A_estatus_reg[13] => ~NO_FANOUT~
A_estatus_reg[14] => ~NO_FANOUT~
A_estatus_reg[15] => ~NO_FANOUT~
A_estatus_reg[16] => ~NO_FANOUT~
A_estatus_reg[17] => ~NO_FANOUT~
A_estatus_reg[18] => ~NO_FANOUT~
A_estatus_reg[19] => ~NO_FANOUT~
A_estatus_reg[20] => ~NO_FANOUT~
A_estatus_reg[21] => ~NO_FANOUT~
A_estatus_reg[22] => ~NO_FANOUT~
A_estatus_reg[23] => ~NO_FANOUT~
A_estatus_reg[24] => ~NO_FANOUT~
A_estatus_reg[25] => ~NO_FANOUT~
A_estatus_reg[26] => ~NO_FANOUT~
A_estatus_reg[27] => ~NO_FANOUT~
A_estatus_reg[28] => ~NO_FANOUT~
A_estatus_reg[29] => ~NO_FANOUT~
A_estatus_reg[30] => ~NO_FANOUT~
A_estatus_reg[31] => ~NO_FANOUT~
A_ienable_reg[0] => ~NO_FANOUT~
A_ienable_reg[1] => ~NO_FANOUT~
A_ienable_reg[2] => ~NO_FANOUT~
A_ienable_reg[3] => ~NO_FANOUT~
A_ienable_reg[4] => ~NO_FANOUT~
A_ienable_reg[5] => ~NO_FANOUT~
A_ienable_reg[6] => ~NO_FANOUT~
A_ienable_reg[7] => ~NO_FANOUT~
A_ienable_reg[8] => ~NO_FANOUT~
A_ienable_reg[9] => ~NO_FANOUT~
A_ienable_reg[10] => ~NO_FANOUT~
A_ienable_reg[11] => ~NO_FANOUT~
A_ienable_reg[12] => ~NO_FANOUT~
A_ienable_reg[13] => ~NO_FANOUT~
A_ienable_reg[14] => ~NO_FANOUT~
A_ienable_reg[15] => ~NO_FANOUT~
A_ienable_reg[16] => ~NO_FANOUT~
A_ienable_reg[17] => ~NO_FANOUT~
A_ienable_reg[18] => ~NO_FANOUT~
A_ienable_reg[19] => ~NO_FANOUT~
A_ienable_reg[20] => ~NO_FANOUT~
A_ienable_reg[21] => ~NO_FANOUT~
A_ienable_reg[22] => ~NO_FANOUT~
A_ienable_reg[23] => ~NO_FANOUT~
A_ienable_reg[24] => ~NO_FANOUT~
A_ienable_reg[25] => ~NO_FANOUT~
A_ienable_reg[26] => ~NO_FANOUT~
A_ienable_reg[27] => ~NO_FANOUT~
A_ienable_reg[28] => ~NO_FANOUT~
A_ienable_reg[29] => ~NO_FANOUT~
A_ienable_reg[30] => ~NO_FANOUT~
A_ienable_reg[31] => ~NO_FANOUT~
A_ipending_reg[0] => ~NO_FANOUT~
A_ipending_reg[1] => ~NO_FANOUT~
A_ipending_reg[2] => ~NO_FANOUT~
A_ipending_reg[3] => ~NO_FANOUT~
A_ipending_reg[4] => ~NO_FANOUT~
A_ipending_reg[5] => ~NO_FANOUT~
A_ipending_reg[6] => ~NO_FANOUT~
A_ipending_reg[7] => ~NO_FANOUT~
A_ipending_reg[8] => ~NO_FANOUT~
A_ipending_reg[9] => ~NO_FANOUT~
A_ipending_reg[10] => ~NO_FANOUT~
A_ipending_reg[11] => ~NO_FANOUT~
A_ipending_reg[12] => ~NO_FANOUT~
A_ipending_reg[13] => ~NO_FANOUT~
A_ipending_reg[14] => ~NO_FANOUT~
A_ipending_reg[15] => ~NO_FANOUT~
A_ipending_reg[16] => ~NO_FANOUT~
A_ipending_reg[17] => ~NO_FANOUT~
A_ipending_reg[18] => ~NO_FANOUT~
A_ipending_reg[19] => ~NO_FANOUT~
A_ipending_reg[20] => ~NO_FANOUT~
A_ipending_reg[21] => ~NO_FANOUT~
A_ipending_reg[22] => ~NO_FANOUT~
A_ipending_reg[23] => ~NO_FANOUT~
A_ipending_reg[24] => ~NO_FANOUT~
A_ipending_reg[25] => ~NO_FANOUT~
A_ipending_reg[26] => ~NO_FANOUT~
A_ipending_reg[27] => ~NO_FANOUT~
A_ipending_reg[28] => ~NO_FANOUT~
A_ipending_reg[29] => ~NO_FANOUT~
A_ipending_reg[30] => ~NO_FANOUT~
A_ipending_reg[31] => ~NO_FANOUT~
A_iw[0] => ~NO_FANOUT~
A_iw[1] => ~NO_FANOUT~
A_iw[2] => ~NO_FANOUT~
A_iw[3] => ~NO_FANOUT~
A_iw[4] => ~NO_FANOUT~
A_iw[5] => ~NO_FANOUT~
A_iw[6] => ~NO_FANOUT~
A_iw[7] => ~NO_FANOUT~
A_iw[8] => ~NO_FANOUT~
A_iw[9] => ~NO_FANOUT~
A_iw[10] => ~NO_FANOUT~
A_iw[11] => ~NO_FANOUT~
A_iw[12] => ~NO_FANOUT~
A_iw[13] => ~NO_FANOUT~
A_iw[14] => ~NO_FANOUT~
A_iw[15] => ~NO_FANOUT~
A_iw[16] => ~NO_FANOUT~
A_iw[17] => ~NO_FANOUT~
A_iw[18] => ~NO_FANOUT~
A_iw[19] => ~NO_FANOUT~
A_iw[20] => ~NO_FANOUT~
A_iw[21] => ~NO_FANOUT~
A_iw[22] => ~NO_FANOUT~
A_iw[23] => ~NO_FANOUT~
A_iw[24] => ~NO_FANOUT~
A_iw[25] => ~NO_FANOUT~
A_iw[26] => ~NO_FANOUT~
A_iw[27] => ~NO_FANOUT~
A_iw[28] => ~NO_FANOUT~
A_iw[29] => ~NO_FANOUT~
A_iw[30] => ~NO_FANOUT~
A_iw[31] => ~NO_FANOUT~
A_mem_byte_en[0] => ~NO_FANOUT~
A_mem_byte_en[1] => ~NO_FANOUT~
A_mem_byte_en[2] => ~NO_FANOUT~
A_mem_byte_en[3] => ~NO_FANOUT~
A_op_hbreak => ~NO_FANOUT~
A_op_intr => ~NO_FANOUT~
A_pcb[0] => ~NO_FANOUT~
A_pcb[1] => ~NO_FANOUT~
A_pcb[2] => ~NO_FANOUT~
A_pcb[3] => ~NO_FANOUT~
A_pcb[4] => ~NO_FANOUT~
A_pcb[5] => ~NO_FANOUT~
A_pcb[6] => ~NO_FANOUT~
A_pcb[7] => ~NO_FANOUT~
A_pcb[8] => ~NO_FANOUT~
A_pcb[9] => ~NO_FANOUT~
A_pcb[10] => ~NO_FANOUT~
A_pcb[11] => ~NO_FANOUT~
A_pcb[12] => ~NO_FANOUT~
A_pcb[13] => ~NO_FANOUT~
A_pcb[14] => ~NO_FANOUT~
A_pcb[15] => ~NO_FANOUT~
A_pcb[16] => ~NO_FANOUT~
A_pcb[17] => ~NO_FANOUT~
A_pcb[18] => ~NO_FANOUT~
A_pcb[19] => ~NO_FANOUT~
A_pcb[20] => ~NO_FANOUT~
A_pcb[21] => ~NO_FANOUT~
A_pcb[22] => ~NO_FANOUT~
A_pcb[23] => ~NO_FANOUT~
A_pcb[24] => ~NO_FANOUT~
A_pcb[25] => ~NO_FANOUT~
A_pcb[26] => ~NO_FANOUT~
A_st_data[0] => ~NO_FANOUT~
A_st_data[1] => ~NO_FANOUT~
A_st_data[2] => ~NO_FANOUT~
A_st_data[3] => ~NO_FANOUT~
A_st_data[4] => ~NO_FANOUT~
A_st_data[5] => ~NO_FANOUT~
A_st_data[6] => ~NO_FANOUT~
A_st_data[7] => ~NO_FANOUT~
A_st_data[8] => ~NO_FANOUT~
A_st_data[9] => ~NO_FANOUT~
A_st_data[10] => ~NO_FANOUT~
A_st_data[11] => ~NO_FANOUT~
A_st_data[12] => ~NO_FANOUT~
A_st_data[13] => ~NO_FANOUT~
A_st_data[14] => ~NO_FANOUT~
A_st_data[15] => ~NO_FANOUT~
A_st_data[16] => ~NO_FANOUT~
A_st_data[17] => ~NO_FANOUT~
A_st_data[18] => ~NO_FANOUT~
A_st_data[19] => ~NO_FANOUT~
A_st_data[20] => ~NO_FANOUT~
A_st_data[21] => ~NO_FANOUT~
A_st_data[22] => ~NO_FANOUT~
A_st_data[23] => ~NO_FANOUT~
A_st_data[24] => ~NO_FANOUT~
A_st_data[25] => ~NO_FANOUT~
A_st_data[26] => ~NO_FANOUT~
A_st_data[27] => ~NO_FANOUT~
A_st_data[28] => ~NO_FANOUT~
A_st_data[29] => ~NO_FANOUT~
A_st_data[30] => ~NO_FANOUT~
A_st_data[31] => ~NO_FANOUT~
A_status_reg[0] => ~NO_FANOUT~
A_status_reg[1] => ~NO_FANOUT~
A_status_reg[2] => ~NO_FANOUT~
A_status_reg[3] => ~NO_FANOUT~
A_status_reg[4] => ~NO_FANOUT~
A_status_reg[5] => ~NO_FANOUT~
A_status_reg[6] => ~NO_FANOUT~
A_status_reg[7] => ~NO_FANOUT~
A_status_reg[8] => ~NO_FANOUT~
A_status_reg[9] => ~NO_FANOUT~
A_status_reg[10] => ~NO_FANOUT~
A_status_reg[11] => ~NO_FANOUT~
A_status_reg[12] => ~NO_FANOUT~
A_status_reg[13] => ~NO_FANOUT~
A_status_reg[14] => ~NO_FANOUT~
A_status_reg[15] => ~NO_FANOUT~
A_status_reg[16] => ~NO_FANOUT~
A_status_reg[17] => ~NO_FANOUT~
A_status_reg[18] => ~NO_FANOUT~
A_status_reg[19] => ~NO_FANOUT~
A_status_reg[20] => ~NO_FANOUT~
A_status_reg[21] => ~NO_FANOUT~
A_status_reg[22] => ~NO_FANOUT~
A_status_reg[23] => ~NO_FANOUT~
A_status_reg[24] => ~NO_FANOUT~
A_status_reg[25] => ~NO_FANOUT~
A_status_reg[26] => ~NO_FANOUT~
A_status_reg[27] => ~NO_FANOUT~
A_status_reg[28] => ~NO_FANOUT~
A_status_reg[29] => ~NO_FANOUT~
A_status_reg[30] => ~NO_FANOUT~
A_status_reg[31] => ~NO_FANOUT~
A_valid => ~NO_FANOUT~
A_wr_data_unfiltered[0] => A_wr_data_filtered[0].DATAIN
A_wr_data_unfiltered[1] => A_wr_data_filtered[1].DATAIN
A_wr_data_unfiltered[2] => A_wr_data_filtered[2].DATAIN
A_wr_data_unfiltered[3] => A_wr_data_filtered[3].DATAIN
A_wr_data_unfiltered[4] => A_wr_data_filtered[4].DATAIN
A_wr_data_unfiltered[5] => A_wr_data_filtered[5].DATAIN
A_wr_data_unfiltered[6] => A_wr_data_filtered[6].DATAIN
A_wr_data_unfiltered[7] => A_wr_data_filtered[7].DATAIN
A_wr_data_unfiltered[8] => A_wr_data_filtered[8].DATAIN
A_wr_data_unfiltered[9] => A_wr_data_filtered[9].DATAIN
A_wr_data_unfiltered[10] => A_wr_data_filtered[10].DATAIN
A_wr_data_unfiltered[11] => A_wr_data_filtered[11].DATAIN
A_wr_data_unfiltered[12] => A_wr_data_filtered[12].DATAIN
A_wr_data_unfiltered[13] => A_wr_data_filtered[13].DATAIN
A_wr_data_unfiltered[14] => A_wr_data_filtered[14].DATAIN
A_wr_data_unfiltered[15] => A_wr_data_filtered[15].DATAIN
A_wr_data_unfiltered[16] => A_wr_data_filtered[16].DATAIN
A_wr_data_unfiltered[17] => A_wr_data_filtered[17].DATAIN
A_wr_data_unfiltered[18] => A_wr_data_filtered[18].DATAIN
A_wr_data_unfiltered[19] => A_wr_data_filtered[19].DATAIN
A_wr_data_unfiltered[20] => A_wr_data_filtered[20].DATAIN
A_wr_data_unfiltered[21] => A_wr_data_filtered[21].DATAIN
A_wr_data_unfiltered[22] => A_wr_data_filtered[22].DATAIN
A_wr_data_unfiltered[23] => A_wr_data_filtered[23].DATAIN
A_wr_data_unfiltered[24] => A_wr_data_filtered[24].DATAIN
A_wr_data_unfiltered[25] => A_wr_data_filtered[25].DATAIN
A_wr_data_unfiltered[26] => A_wr_data_filtered[26].DATAIN
A_wr_data_unfiltered[27] => A_wr_data_filtered[27].DATAIN
A_wr_data_unfiltered[28] => A_wr_data_filtered[28].DATAIN
A_wr_data_unfiltered[29] => A_wr_data_filtered[29].DATAIN
A_wr_data_unfiltered[30] => A_wr_data_filtered[30].DATAIN
A_wr_data_unfiltered[31] => A_wr_data_filtered[31].DATAIN
A_wr_dst_reg => ~NO_FANOUT~
E_add_br_to_taken_history_unfiltered => E_add_br_to_taken_history_filtered.DATAIN
E_logic_result[0] => Equal0.IN31
E_logic_result[1] => Equal0.IN30
E_logic_result[2] => Equal0.IN29
E_logic_result[3] => Equal0.IN28
E_logic_result[4] => Equal0.IN27
E_logic_result[5] => Equal0.IN26
E_logic_result[6] => Equal0.IN25
E_logic_result[7] => Equal0.IN24
E_logic_result[8] => Equal0.IN23
E_logic_result[9] => Equal0.IN22
E_logic_result[10] => Equal0.IN21
E_logic_result[11] => Equal0.IN20
E_logic_result[12] => Equal0.IN19
E_logic_result[13] => Equal0.IN18
E_logic_result[14] => Equal0.IN17
E_logic_result[15] => Equal0.IN16
E_logic_result[16] => Equal0.IN15
E_logic_result[17] => Equal0.IN14
E_logic_result[18] => Equal0.IN13
E_logic_result[19] => Equal0.IN12
E_logic_result[20] => Equal0.IN11
E_logic_result[21] => Equal0.IN10
E_logic_result[22] => Equal0.IN9
E_logic_result[23] => Equal0.IN8
E_logic_result[24] => Equal0.IN7
E_logic_result[25] => Equal0.IN6
E_logic_result[26] => Equal0.IN5
E_logic_result[27] => Equal0.IN4
E_logic_result[28] => Equal0.IN3
E_logic_result[29] => Equal0.IN2
E_logic_result[30] => Equal0.IN1
E_logic_result[31] => Equal0.IN0
E_valid => ~NO_FANOUT~
M_bht_ptr_unfiltered[0] => M_bht_ptr_filtered[0].DATAIN
M_bht_ptr_unfiltered[1] => M_bht_ptr_filtered[1].DATAIN
M_bht_ptr_unfiltered[2] => M_bht_ptr_filtered[2].DATAIN
M_bht_ptr_unfiltered[3] => M_bht_ptr_filtered[3].DATAIN
M_bht_ptr_unfiltered[4] => M_bht_ptr_filtered[4].DATAIN
M_bht_ptr_unfiltered[5] => M_bht_ptr_filtered[5].DATAIN
M_bht_ptr_unfiltered[6] => M_bht_ptr_filtered[6].DATAIN
M_bht_ptr_unfiltered[7] => M_bht_ptr_filtered[7].DATAIN
M_bht_wr_data_unfiltered[0] => M_bht_wr_data_filtered[0].DATAIN
M_bht_wr_data_unfiltered[1] => M_bht_wr_data_filtered[1].DATAIN
M_bht_wr_en_unfiltered => M_bht_wr_en_filtered.DATAIN
M_mem_baddr[0] => ~NO_FANOUT~
M_mem_baddr[1] => ~NO_FANOUT~
M_mem_baddr[2] => ~NO_FANOUT~
M_mem_baddr[3] => ~NO_FANOUT~
M_mem_baddr[4] => ~NO_FANOUT~
M_mem_baddr[5] => ~NO_FANOUT~
M_mem_baddr[6] => ~NO_FANOUT~
M_mem_baddr[7] => ~NO_FANOUT~
M_mem_baddr[8] => ~NO_FANOUT~
M_mem_baddr[9] => ~NO_FANOUT~
M_mem_baddr[10] => ~NO_FANOUT~
M_mem_baddr[11] => ~NO_FANOUT~
M_mem_baddr[12] => ~NO_FANOUT~
M_mem_baddr[13] => ~NO_FANOUT~
M_mem_baddr[14] => ~NO_FANOUT~
M_mem_baddr[15] => ~NO_FANOUT~
M_mem_baddr[16] => ~NO_FANOUT~
M_mem_baddr[17] => ~NO_FANOUT~
M_mem_baddr[18] => ~NO_FANOUT~
M_mem_baddr[19] => ~NO_FANOUT~
M_mem_baddr[20] => ~NO_FANOUT~
M_mem_baddr[21] => ~NO_FANOUT~
M_mem_baddr[22] => ~NO_FANOUT~
M_mem_baddr[23] => ~NO_FANOUT~
M_mem_baddr[24] => ~NO_FANOUT~
M_mem_baddr[25] => ~NO_FANOUT~
M_mem_baddr[26] => ~NO_FANOUT~
M_target_pcb[0] => ~NO_FANOUT~
M_target_pcb[1] => ~NO_FANOUT~
M_target_pcb[2] => ~NO_FANOUT~
M_target_pcb[3] => ~NO_FANOUT~
M_target_pcb[4] => ~NO_FANOUT~
M_target_pcb[5] => ~NO_FANOUT~
M_target_pcb[6] => ~NO_FANOUT~
M_target_pcb[7] => ~NO_FANOUT~
M_target_pcb[8] => ~NO_FANOUT~
M_target_pcb[9] => ~NO_FANOUT~
M_target_pcb[10] => ~NO_FANOUT~
M_target_pcb[11] => ~NO_FANOUT~
M_target_pcb[12] => ~NO_FANOUT~
M_target_pcb[13] => ~NO_FANOUT~
M_target_pcb[14] => ~NO_FANOUT~
M_target_pcb[15] => ~NO_FANOUT~
M_target_pcb[16] => ~NO_FANOUT~
M_target_pcb[17] => ~NO_FANOUT~
M_target_pcb[18] => ~NO_FANOUT~
M_target_pcb[19] => ~NO_FANOUT~
M_target_pcb[20] => ~NO_FANOUT~
M_target_pcb[21] => ~NO_FANOUT~
M_target_pcb[22] => ~NO_FANOUT~
M_target_pcb[23] => ~NO_FANOUT~
M_target_pcb[24] => ~NO_FANOUT~
M_target_pcb[25] => ~NO_FANOUT~
M_target_pcb[26] => ~NO_FANOUT~
M_valid => ~NO_FANOUT~
W_dst_regnum[0] => ~NO_FANOUT~
W_dst_regnum[1] => ~NO_FANOUT~
W_dst_regnum[2] => ~NO_FANOUT~
W_dst_regnum[3] => ~NO_FANOUT~
W_dst_regnum[4] => ~NO_FANOUT~
W_iw[0] => ~NO_FANOUT~
W_iw[1] => ~NO_FANOUT~
W_iw[2] => ~NO_FANOUT~
W_iw[3] => ~NO_FANOUT~
W_iw[4] => ~NO_FANOUT~
W_iw[5] => ~NO_FANOUT~
W_iw[6] => ~NO_FANOUT~
W_iw[7] => ~NO_FANOUT~
W_iw[8] => ~NO_FANOUT~
W_iw[9] => ~NO_FANOUT~
W_iw[10] => ~NO_FANOUT~
W_iw[11] => ~NO_FANOUT~
W_iw[12] => ~NO_FANOUT~
W_iw[13] => ~NO_FANOUT~
W_iw[14] => ~NO_FANOUT~
W_iw[15] => ~NO_FANOUT~
W_iw[16] => ~NO_FANOUT~
W_iw[17] => ~NO_FANOUT~
W_iw[18] => ~NO_FANOUT~
W_iw[19] => ~NO_FANOUT~
W_iw[20] => ~NO_FANOUT~
W_iw[21] => ~NO_FANOUT~
W_iw[22] => ~NO_FANOUT~
W_iw[23] => ~NO_FANOUT~
W_iw[24] => ~NO_FANOUT~
W_iw[25] => ~NO_FANOUT~
W_iw[26] => ~NO_FANOUT~
W_iw[27] => ~NO_FANOUT~
W_iw[28] => ~NO_FANOUT~
W_iw[29] => ~NO_FANOUT~
W_iw[30] => ~NO_FANOUT~
W_iw[31] => ~NO_FANOUT~
W_iw_op[0] => ~NO_FANOUT~
W_iw_op[1] => ~NO_FANOUT~
W_iw_op[2] => ~NO_FANOUT~
W_iw_op[3] => ~NO_FANOUT~
W_iw_op[4] => ~NO_FANOUT~
W_iw_op[5] => ~NO_FANOUT~
W_iw_opx[0] => ~NO_FANOUT~
W_iw_opx[1] => ~NO_FANOUT~
W_iw_opx[2] => ~NO_FANOUT~
W_iw_opx[3] => ~NO_FANOUT~
W_iw_opx[4] => ~NO_FANOUT~
W_iw_opx[5] => ~NO_FANOUT~
W_pcb[0] => ~NO_FANOUT~
W_pcb[1] => ~NO_FANOUT~
W_pcb[2] => ~NO_FANOUT~
W_pcb[3] => ~NO_FANOUT~
W_pcb[4] => ~NO_FANOUT~
W_pcb[5] => ~NO_FANOUT~
W_pcb[6] => ~NO_FANOUT~
W_pcb[7] => ~NO_FANOUT~
W_pcb[8] => ~NO_FANOUT~
W_pcb[9] => ~NO_FANOUT~
W_pcb[10] => ~NO_FANOUT~
W_pcb[11] => ~NO_FANOUT~
W_pcb[12] => ~NO_FANOUT~
W_pcb[13] => ~NO_FANOUT~
W_pcb[14] => ~NO_FANOUT~
W_pcb[15] => ~NO_FANOUT~
W_pcb[16] => ~NO_FANOUT~
W_pcb[17] => ~NO_FANOUT~
W_pcb[18] => ~NO_FANOUT~
W_pcb[19] => ~NO_FANOUT~
W_pcb[20] => ~NO_FANOUT~
W_pcb[21] => ~NO_FANOUT~
W_pcb[22] => ~NO_FANOUT~
W_pcb[23] => ~NO_FANOUT~
W_pcb[24] => ~NO_FANOUT~
W_pcb[25] => ~NO_FANOUT~
W_pcb[26] => ~NO_FANOUT~
W_valid => ~NO_FANOUT~
W_vinst[0] => ~NO_FANOUT~
W_vinst[1] => ~NO_FANOUT~
W_vinst[2] => ~NO_FANOUT~
W_vinst[3] => ~NO_FANOUT~
W_vinst[4] => ~NO_FANOUT~
W_vinst[5] => ~NO_FANOUT~
W_vinst[6] => ~NO_FANOUT~
W_vinst[7] => ~NO_FANOUT~
W_vinst[8] => ~NO_FANOUT~
W_vinst[9] => ~NO_FANOUT~
W_vinst[10] => ~NO_FANOUT~
W_vinst[11] => ~NO_FANOUT~
W_vinst[12] => ~NO_FANOUT~
W_vinst[13] => ~NO_FANOUT~
W_vinst[14] => ~NO_FANOUT~
W_vinst[15] => ~NO_FANOUT~
W_vinst[16] => ~NO_FANOUT~
W_vinst[17] => ~NO_FANOUT~
W_vinst[18] => ~NO_FANOUT~
W_vinst[19] => ~NO_FANOUT~
W_vinst[20] => ~NO_FANOUT~
W_vinst[21] => ~NO_FANOUT~
W_vinst[22] => ~NO_FANOUT~
W_vinst[23] => ~NO_FANOUT~
W_vinst[24] => ~NO_FANOUT~
W_vinst[25] => ~NO_FANOUT~
W_vinst[26] => ~NO_FANOUT~
W_vinst[27] => ~NO_FANOUT~
W_vinst[28] => ~NO_FANOUT~
W_vinst[29] => ~NO_FANOUT~
W_vinst[30] => ~NO_FANOUT~
W_vinst[31] => ~NO_FANOUT~
W_vinst[32] => ~NO_FANOUT~
W_vinst[33] => ~NO_FANOUT~
W_vinst[34] => ~NO_FANOUT~
W_vinst[35] => ~NO_FANOUT~
W_vinst[36] => ~NO_FANOUT~
W_vinst[37] => ~NO_FANOUT~
W_vinst[38] => ~NO_FANOUT~
W_vinst[39] => ~NO_FANOUT~
W_vinst[40] => ~NO_FANOUT~
W_vinst[41] => ~NO_FANOUT~
W_vinst[42] => ~NO_FANOUT~
W_vinst[43] => ~NO_FANOUT~
W_vinst[44] => ~NO_FANOUT~
W_vinst[45] => ~NO_FANOUT~
W_vinst[46] => ~NO_FANOUT~
W_vinst[47] => ~NO_FANOUT~
W_vinst[48] => ~NO_FANOUT~
W_vinst[49] => ~NO_FANOUT~
W_vinst[50] => ~NO_FANOUT~
W_vinst[51] => ~NO_FANOUT~
W_vinst[52] => ~NO_FANOUT~
W_vinst[53] => ~NO_FANOUT~
W_vinst[54] => ~NO_FANOUT~
W_vinst[55] => ~NO_FANOUT~
W_wr_dst_reg => ~NO_FANOUT~
clk => ~NO_FANOUT~
d_address[0] => ~NO_FANOUT~
d_address[1] => ~NO_FANOUT~
d_address[2] => ~NO_FANOUT~
d_address[3] => ~NO_FANOUT~
d_address[4] => ~NO_FANOUT~
d_address[5] => ~NO_FANOUT~
d_address[6] => ~NO_FANOUT~
d_address[7] => ~NO_FANOUT~
d_address[8] => ~NO_FANOUT~
d_address[9] => ~NO_FANOUT~
d_address[10] => ~NO_FANOUT~
d_address[11] => ~NO_FANOUT~
d_address[12] => ~NO_FANOUT~
d_address[13] => ~NO_FANOUT~
d_address[14] => ~NO_FANOUT~
d_address[15] => ~NO_FANOUT~
d_address[16] => ~NO_FANOUT~
d_address[17] => ~NO_FANOUT~
d_address[18] => ~NO_FANOUT~
d_address[19] => ~NO_FANOUT~
d_address[20] => ~NO_FANOUT~
d_address[21] => ~NO_FANOUT~
d_address[22] => ~NO_FANOUT~
d_address[23] => ~NO_FANOUT~
d_address[24] => ~NO_FANOUT~
d_address[25] => ~NO_FANOUT~
d_address[26] => ~NO_FANOUT~
d_byteenable[0] => ~NO_FANOUT~
d_byteenable[1] => ~NO_FANOUT~
d_byteenable[2] => ~NO_FANOUT~
d_byteenable[3] => ~NO_FANOUT~
d_read => ~NO_FANOUT~
d_write => ~NO_FANOUT~
i_address[0] => ~NO_FANOUT~
i_address[1] => ~NO_FANOUT~
i_address[2] => ~NO_FANOUT~
i_address[3] => ~NO_FANOUT~
i_address[4] => ~NO_FANOUT~
i_address[5] => ~NO_FANOUT~
i_address[6] => ~NO_FANOUT~
i_address[7] => ~NO_FANOUT~
i_address[8] => ~NO_FANOUT~
i_address[9] => ~NO_FANOUT~
i_address[10] => ~NO_FANOUT~
i_address[11] => ~NO_FANOUT~
i_address[12] => ~NO_FANOUT~
i_address[13] => ~NO_FANOUT~
i_address[14] => ~NO_FANOUT~
i_address[15] => ~NO_FANOUT~
i_address[16] => ~NO_FANOUT~
i_address[17] => ~NO_FANOUT~
i_address[18] => ~NO_FANOUT~
i_address[19] => ~NO_FANOUT~
i_address[20] => ~NO_FANOUT~
i_address[21] => ~NO_FANOUT~
i_address[22] => ~NO_FANOUT~
i_address[23] => ~NO_FANOUT~
i_address[24] => ~NO_FANOUT~
i_address[25] => ~NO_FANOUT~
i_address[26] => ~NO_FANOUT~
i_read => ~NO_FANOUT~
i_readdatavalid => ~NO_FANOUT~
reset_n => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
data[8] => data[8].IN1
data[9] => data[9].IN1
data[10] => data[10].IN1
data[11] => data[11].IN1
data[12] => data[12].IN1
data[13] => data[13].IN1
data[14] => data[14].IN1
data[15] => data[15].IN1
data[16] => data[16].IN1
data[17] => data[17].IN1
data[18] => data[18].IN1
data[19] => data[19].IN1
data[20] => data[20].IN1
data[21] => data[21].IN1
data[22] => data[22].IN1
data[23] => data[23].IN1
data[24] => data[24].IN1
data[25] => data[25].IN1
data[26] => data[26].IN1
data[27] => data[27].IN1
data[28] => data[28].IN1
data[29] => data[29].IN1
data[30] => data[30].IN1
data[31] => data[31].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
rdaddress[5] => rdaddress[5].IN1
rdaddress[6] => rdaddress[6].IN1
rdaddress[7] => rdaddress[7].IN1
rdaddress[8] => rdaddress[8].IN1
rden => rden.IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wraddress[5] => wraddress[5].IN1
wraddress[6] => wraddress[6].IN1
wraddress[7] => wraddress[7].IN1
wraddress[8] => wraddress[8].IN1
wren => wren.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram
wren_a => altsyncram_udd1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => altsyncram_udd1:auto_generated.rden_b
data_a[0] => altsyncram_udd1:auto_generated.data_a[0]
data_a[1] => altsyncram_udd1:auto_generated.data_a[1]
data_a[2] => altsyncram_udd1:auto_generated.data_a[2]
data_a[3] => altsyncram_udd1:auto_generated.data_a[3]
data_a[4] => altsyncram_udd1:auto_generated.data_a[4]
data_a[5] => altsyncram_udd1:auto_generated.data_a[5]
data_a[6] => altsyncram_udd1:auto_generated.data_a[6]
data_a[7] => altsyncram_udd1:auto_generated.data_a[7]
data_a[8] => altsyncram_udd1:auto_generated.data_a[8]
data_a[9] => altsyncram_udd1:auto_generated.data_a[9]
data_a[10] => altsyncram_udd1:auto_generated.data_a[10]
data_a[11] => altsyncram_udd1:auto_generated.data_a[11]
data_a[12] => altsyncram_udd1:auto_generated.data_a[12]
data_a[13] => altsyncram_udd1:auto_generated.data_a[13]
data_a[14] => altsyncram_udd1:auto_generated.data_a[14]
data_a[15] => altsyncram_udd1:auto_generated.data_a[15]
data_a[16] => altsyncram_udd1:auto_generated.data_a[16]
data_a[17] => altsyncram_udd1:auto_generated.data_a[17]
data_a[18] => altsyncram_udd1:auto_generated.data_a[18]
data_a[19] => altsyncram_udd1:auto_generated.data_a[19]
data_a[20] => altsyncram_udd1:auto_generated.data_a[20]
data_a[21] => altsyncram_udd1:auto_generated.data_a[21]
data_a[22] => altsyncram_udd1:auto_generated.data_a[22]
data_a[23] => altsyncram_udd1:auto_generated.data_a[23]
data_a[24] => altsyncram_udd1:auto_generated.data_a[24]
data_a[25] => altsyncram_udd1:auto_generated.data_a[25]
data_a[26] => altsyncram_udd1:auto_generated.data_a[26]
data_a[27] => altsyncram_udd1:auto_generated.data_a[27]
data_a[28] => altsyncram_udd1:auto_generated.data_a[28]
data_a[29] => altsyncram_udd1:auto_generated.data_a[29]
data_a[30] => altsyncram_udd1:auto_generated.data_a[30]
data_a[31] => altsyncram_udd1:auto_generated.data_a[31]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
data_b[16] => ~NO_FANOUT~
data_b[17] => ~NO_FANOUT~
data_b[18] => ~NO_FANOUT~
data_b[19] => ~NO_FANOUT~
data_b[20] => ~NO_FANOUT~
data_b[21] => ~NO_FANOUT~
data_b[22] => ~NO_FANOUT~
data_b[23] => ~NO_FANOUT~
data_b[24] => ~NO_FANOUT~
data_b[25] => ~NO_FANOUT~
data_b[26] => ~NO_FANOUT~
data_b[27] => ~NO_FANOUT~
data_b[28] => ~NO_FANOUT~
data_b[29] => ~NO_FANOUT~
data_b[30] => ~NO_FANOUT~
data_b[31] => ~NO_FANOUT~
address_a[0] => altsyncram_udd1:auto_generated.address_a[0]
address_a[1] => altsyncram_udd1:auto_generated.address_a[1]
address_a[2] => altsyncram_udd1:auto_generated.address_a[2]
address_a[3] => altsyncram_udd1:auto_generated.address_a[3]
address_a[4] => altsyncram_udd1:auto_generated.address_a[4]
address_a[5] => altsyncram_udd1:auto_generated.address_a[5]
address_a[6] => altsyncram_udd1:auto_generated.address_a[6]
address_a[7] => altsyncram_udd1:auto_generated.address_a[7]
address_a[8] => altsyncram_udd1:auto_generated.address_a[8]
address_b[0] => altsyncram_udd1:auto_generated.address_b[0]
address_b[1] => altsyncram_udd1:auto_generated.address_b[1]
address_b[2] => altsyncram_udd1:auto_generated.address_b[2]
address_b[3] => altsyncram_udd1:auto_generated.address_b[3]
address_b[4] => altsyncram_udd1:auto_generated.address_b[4]
address_b[5] => altsyncram_udd1:auto_generated.address_b[5]
address_b[6] => altsyncram_udd1:auto_generated.address_b[6]
address_b[7] => altsyncram_udd1:auto_generated.address_b[7]
address_b[8] => altsyncram_udd1:auto_generated.address_b[8]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_udd1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_udd1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[0] => ram_block1a23.PORTBADDR
address_b[0] => ram_block1a24.PORTBADDR
address_b[0] => ram_block1a25.PORTBADDR
address_b[0] => ram_block1a26.PORTBADDR
address_b[0] => ram_block1a27.PORTBADDR
address_b[0] => ram_block1a28.PORTBADDR
address_b[0] => ram_block1a29.PORTBADDR
address_b[0] => ram_block1a30.PORTBADDR
address_b[0] => ram_block1a31.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[1] => ram_block1a23.PORTBADDR1
address_b[1] => ram_block1a24.PORTBADDR1
address_b[1] => ram_block1a25.PORTBADDR1
address_b[1] => ram_block1a26.PORTBADDR1
address_b[1] => ram_block1a27.PORTBADDR1
address_b[1] => ram_block1a28.PORTBADDR1
address_b[1] => ram_block1a29.PORTBADDR1
address_b[1] => ram_block1a30.PORTBADDR1
address_b[1] => ram_block1a31.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[2] => ram_block1a23.PORTBADDR2
address_b[2] => ram_block1a24.PORTBADDR2
address_b[2] => ram_block1a25.PORTBADDR2
address_b[2] => ram_block1a26.PORTBADDR2
address_b[2] => ram_block1a27.PORTBADDR2
address_b[2] => ram_block1a28.PORTBADDR2
address_b[2] => ram_block1a29.PORTBADDR2
address_b[2] => ram_block1a30.PORTBADDR2
address_b[2] => ram_block1a31.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[3] => ram_block1a23.PORTBADDR3
address_b[3] => ram_block1a24.PORTBADDR3
address_b[3] => ram_block1a25.PORTBADDR3
address_b[3] => ram_block1a26.PORTBADDR3
address_b[3] => ram_block1a27.PORTBADDR3
address_b[3] => ram_block1a28.PORTBADDR3
address_b[3] => ram_block1a29.PORTBADDR3
address_b[3] => ram_block1a30.PORTBADDR3
address_b[3] => ram_block1a31.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[4] => ram_block1a24.PORTBADDR4
address_b[4] => ram_block1a25.PORTBADDR4
address_b[4] => ram_block1a26.PORTBADDR4
address_b[4] => ram_block1a27.PORTBADDR4
address_b[4] => ram_block1a28.PORTBADDR4
address_b[4] => ram_block1a29.PORTBADDR4
address_b[4] => ram_block1a30.PORTBADDR4
address_b[4] => ram_block1a31.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[5] => ram_block1a16.PORTBADDR5
address_b[5] => ram_block1a17.PORTBADDR5
address_b[5] => ram_block1a18.PORTBADDR5
address_b[5] => ram_block1a19.PORTBADDR5
address_b[5] => ram_block1a20.PORTBADDR5
address_b[5] => ram_block1a21.PORTBADDR5
address_b[5] => ram_block1a22.PORTBADDR5
address_b[5] => ram_block1a23.PORTBADDR5
address_b[5] => ram_block1a24.PORTBADDR5
address_b[5] => ram_block1a25.PORTBADDR5
address_b[5] => ram_block1a26.PORTBADDR5
address_b[5] => ram_block1a27.PORTBADDR5
address_b[5] => ram_block1a28.PORTBADDR5
address_b[5] => ram_block1a29.PORTBADDR5
address_b[5] => ram_block1a30.PORTBADDR5
address_b[5] => ram_block1a31.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[6] => ram_block1a16.PORTBADDR6
address_b[6] => ram_block1a17.PORTBADDR6
address_b[6] => ram_block1a18.PORTBADDR6
address_b[6] => ram_block1a19.PORTBADDR6
address_b[6] => ram_block1a20.PORTBADDR6
address_b[6] => ram_block1a21.PORTBADDR6
address_b[6] => ram_block1a22.PORTBADDR6
address_b[6] => ram_block1a23.PORTBADDR6
address_b[6] => ram_block1a24.PORTBADDR6
address_b[6] => ram_block1a25.PORTBADDR6
address_b[6] => ram_block1a26.PORTBADDR6
address_b[6] => ram_block1a27.PORTBADDR6
address_b[6] => ram_block1a28.PORTBADDR6
address_b[6] => ram_block1a29.PORTBADDR6
address_b[6] => ram_block1a30.PORTBADDR6
address_b[6] => ram_block1a31.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[7] => ram_block1a16.PORTBADDR7
address_b[7] => ram_block1a17.PORTBADDR7
address_b[7] => ram_block1a18.PORTBADDR7
address_b[7] => ram_block1a19.PORTBADDR7
address_b[7] => ram_block1a20.PORTBADDR7
address_b[7] => ram_block1a21.PORTBADDR7
address_b[7] => ram_block1a22.PORTBADDR7
address_b[7] => ram_block1a23.PORTBADDR7
address_b[7] => ram_block1a24.PORTBADDR7
address_b[7] => ram_block1a25.PORTBADDR7
address_b[7] => ram_block1a26.PORTBADDR7
address_b[7] => ram_block1a27.PORTBADDR7
address_b[7] => ram_block1a28.PORTBADDR7
address_b[7] => ram_block1a29.PORTBADDR7
address_b[7] => ram_block1a30.PORTBADDR7
address_b[7] => ram_block1a31.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[8] => ram_block1a8.PORTBADDR8
address_b[8] => ram_block1a9.PORTBADDR8
address_b[8] => ram_block1a10.PORTBADDR8
address_b[8] => ram_block1a11.PORTBADDR8
address_b[8] => ram_block1a12.PORTBADDR8
address_b[8] => ram_block1a13.PORTBADDR8
address_b[8] => ram_block1a14.PORTBADDR8
address_b[8] => ram_block1a15.PORTBADDR8
address_b[8] => ram_block1a16.PORTBADDR8
address_b[8] => ram_block1a17.PORTBADDR8
address_b[8] => ram_block1a18.PORTBADDR8
address_b[8] => ram_block1a19.PORTBADDR8
address_b[8] => ram_block1a20.PORTBADDR8
address_b[8] => ram_block1a21.PORTBADDR8
address_b[8] => ram_block1a22.PORTBADDR8
address_b[8] => ram_block1a23.PORTBADDR8
address_b[8] => ram_block1a24.PORTBADDR8
address_b[8] => ram_block1a25.PORTBADDR8
address_b[8] => ram_block1a26.PORTBADDR8
address_b[8] => ram_block1a27.PORTBADDR8
address_b[8] => ram_block1a28.PORTBADDR8
address_b[8] => ram_block1a29.PORTBADDR8
address_b[8] => ram_block1a30.PORTBADDR8
address_b[8] => ram_block1a31.PORTBADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a0.CLK1
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a1.CLK1
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a2.CLK1
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a3.CLK1
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a4.CLK1
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a5.CLK1
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a6.CLK1
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a7.CLK1
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a8.CLK1
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a9.CLK1
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a10.CLK1
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a11.CLK1
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a12.CLK1
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a13.CLK1
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a14.CLK1
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a15.CLK1
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a16.CLK1
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a17.CLK1
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a18.CLK1
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a19.CLK1
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a20.CLK1
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a21.CLK1
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a22.CLK1
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a23.CLK1
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a24.CLK1
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a25.CLK1
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a26.CLK1
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a27.CLK1
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a28.CLK1
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a29.CLK1
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a30.CLK1
clock0 => ram_block1a31.CLK0
clock0 => ram_block1a31.CLK1
clock0 => rden_b_store.CLK
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
data_a[24] => ram_block1a24.PORTADATAIN
data_a[25] => ram_block1a25.PORTADATAIN
data_a[26] => ram_block1a26.PORTADATAIN
data_a[27] => ram_block1a27.PORTADATAIN
data_a[28] => ram_block1a28.PORTADATAIN
data_a[29] => ram_block1a29.PORTADATAIN
data_a[30] => ram_block1a30.PORTADATAIN
data_a[31] => ram_block1a31.PORTADATAIN
rden_b => ram_block1a0.IN1
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
rden_b => ram_block1a2.PORTBRE
rden_b => ram_block1a3.PORTBRE
rden_b => ram_block1a4.PORTBRE
rden_b => ram_block1a5.PORTBRE
rden_b => ram_block1a6.PORTBRE
rden_b => ram_block1a7.PORTBRE
rden_b => ram_block1a8.PORTBRE
rden_b => ram_block1a9.PORTBRE
rden_b => ram_block1a10.PORTBRE
rden_b => ram_block1a11.PORTBRE
rden_b => ram_block1a12.PORTBRE
rden_b => ram_block1a13.PORTBRE
rden_b => ram_block1a14.PORTBRE
rden_b => ram_block1a15.PORTBRE
rden_b => ram_block1a16.PORTBRE
rden_b => ram_block1a17.PORTBRE
rden_b => ram_block1a18.PORTBRE
rden_b => ram_block1a19.PORTBRE
rden_b => ram_block1a20.PORTBRE
rden_b => ram_block1a21.PORTBRE
rden_b => ram_block1a22.PORTBRE
rden_b => ram_block1a23.PORTBRE
rden_b => ram_block1a24.PORTBRE
rden_b => ram_block1a25.PORTBRE
rden_b => ram_block1a26.PORTBRE
rden_b => ram_block1a27.PORTBRE
rden_b => ram_block1a28.PORTBRE
rden_b => ram_block1a29.PORTBRE
rden_b => ram_block1a30.PORTBRE
rden_b => ram_block1a31.PORTBRE
rden_b => rden_b_store.DATAIN
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a7.ENA0
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a8.ENA0
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a9.ENA0
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a10.ENA0
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a11.ENA0
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a12.ENA0
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a13.ENA0
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a14.ENA0
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a15.ENA0
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a16.ENA0
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a17.ENA0
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a18.ENA0
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a19.ENA0
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a20.ENA0
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a21.ENA0
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a22.ENA0
wren_a => ram_block1a23.PORTAWE
wren_a => ram_block1a23.ENA0
wren_a => ram_block1a24.PORTAWE
wren_a => ram_block1a24.ENA0
wren_a => ram_block1a25.PORTAWE
wren_a => ram_block1a25.ENA0
wren_a => ram_block1a26.PORTAWE
wren_a => ram_block1a26.ENA0
wren_a => ram_block1a27.PORTAWE
wren_a => ram_block1a27.ENA0
wren_a => ram_block1a28.PORTAWE
wren_a => ram_block1a28.ENA0
wren_a => ram_block1a29.PORTAWE
wren_a => ram_block1a29.ENA0
wren_a => ram_block1a30.PORTAWE
wren_a => ram_block1a30.ENA0
wren_a => ram_block1a31.PORTAWE
wren_a => ram_block1a31.ENA0


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
data[8] => data[8].IN1
data[9] => data[9].IN1
data[10] => data[10].IN1
data[11] => data[11].IN1
data[12] => data[12].IN1
data[13] => data[13].IN1
data[14] => data[14].IN1
data[15] => data[15].IN1
data[16] => data[16].IN1
data[17] => data[17].IN1
data[18] => data[18].IN1
data[19] => data[19].IN1
data[20] => data[20].IN1
data[21] => data[21].IN1
data[22] => data[22].IN1
data[23] => data[23].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
rdaddress[5] => rdaddress[5].IN1
rden => rden.IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wraddress[5] => wraddress[5].IN1
wren => wren.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram
wren_a => altsyncram_i2g1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => altsyncram_i2g1:auto_generated.rden_b
data_a[0] => altsyncram_i2g1:auto_generated.data_a[0]
data_a[1] => altsyncram_i2g1:auto_generated.data_a[1]
data_a[2] => altsyncram_i2g1:auto_generated.data_a[2]
data_a[3] => altsyncram_i2g1:auto_generated.data_a[3]
data_a[4] => altsyncram_i2g1:auto_generated.data_a[4]
data_a[5] => altsyncram_i2g1:auto_generated.data_a[5]
data_a[6] => altsyncram_i2g1:auto_generated.data_a[6]
data_a[7] => altsyncram_i2g1:auto_generated.data_a[7]
data_a[8] => altsyncram_i2g1:auto_generated.data_a[8]
data_a[9] => altsyncram_i2g1:auto_generated.data_a[9]
data_a[10] => altsyncram_i2g1:auto_generated.data_a[10]
data_a[11] => altsyncram_i2g1:auto_generated.data_a[11]
data_a[12] => altsyncram_i2g1:auto_generated.data_a[12]
data_a[13] => altsyncram_i2g1:auto_generated.data_a[13]
data_a[14] => altsyncram_i2g1:auto_generated.data_a[14]
data_a[15] => altsyncram_i2g1:auto_generated.data_a[15]
data_a[16] => altsyncram_i2g1:auto_generated.data_a[16]
data_a[17] => altsyncram_i2g1:auto_generated.data_a[17]
data_a[18] => altsyncram_i2g1:auto_generated.data_a[18]
data_a[19] => altsyncram_i2g1:auto_generated.data_a[19]
data_a[20] => altsyncram_i2g1:auto_generated.data_a[20]
data_a[21] => altsyncram_i2g1:auto_generated.data_a[21]
data_a[22] => altsyncram_i2g1:auto_generated.data_a[22]
data_a[23] => altsyncram_i2g1:auto_generated.data_a[23]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
data_b[16] => ~NO_FANOUT~
data_b[17] => ~NO_FANOUT~
data_b[18] => ~NO_FANOUT~
data_b[19] => ~NO_FANOUT~
data_b[20] => ~NO_FANOUT~
data_b[21] => ~NO_FANOUT~
data_b[22] => ~NO_FANOUT~
data_b[23] => ~NO_FANOUT~
address_a[0] => altsyncram_i2g1:auto_generated.address_a[0]
address_a[1] => altsyncram_i2g1:auto_generated.address_a[1]
address_a[2] => altsyncram_i2g1:auto_generated.address_a[2]
address_a[3] => altsyncram_i2g1:auto_generated.address_a[3]
address_a[4] => altsyncram_i2g1:auto_generated.address_a[4]
address_a[5] => altsyncram_i2g1:auto_generated.address_a[5]
address_b[0] => altsyncram_i2g1:auto_generated.address_b[0]
address_b[1] => altsyncram_i2g1:auto_generated.address_b[1]
address_b[2] => altsyncram_i2g1:auto_generated.address_b[2]
address_b[3] => altsyncram_i2g1:auto_generated.address_b[3]
address_b[4] => altsyncram_i2g1:auto_generated.address_b[4]
address_b[5] => altsyncram_i2g1:auto_generated.address_b[5]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_i2g1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_i2g1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[0] => ram_block1a23.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[1] => ram_block1a23.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[2] => ram_block1a23.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[3] => ram_block1a23.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[5] => ram_block1a16.PORTBADDR5
address_b[5] => ram_block1a17.PORTBADDR5
address_b[5] => ram_block1a18.PORTBADDR5
address_b[5] => ram_block1a19.PORTBADDR5
address_b[5] => ram_block1a20.PORTBADDR5
address_b[5] => ram_block1a21.PORTBADDR5
address_b[5] => ram_block1a22.PORTBADDR5
address_b[5] => ram_block1a23.PORTBADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
rden_b => ram_block1a2.PORTBRE
rden_b => ram_block1a3.PORTBRE
rden_b => ram_block1a4.PORTBRE
rden_b => ram_block1a5.PORTBRE
rden_b => ram_block1a6.PORTBRE
rden_b => ram_block1a7.PORTBRE
rden_b => ram_block1a8.PORTBRE
rden_b => ram_block1a9.PORTBRE
rden_b => ram_block1a10.PORTBRE
rden_b => ram_block1a11.PORTBRE
rden_b => ram_block1a12.PORTBRE
rden_b => ram_block1a13.PORTBRE
rden_b => ram_block1a14.PORTBRE
rden_b => ram_block1a15.PORTBRE
rden_b => ram_block1a16.PORTBRE
rden_b => ram_block1a17.PORTBRE
rden_b => ram_block1a18.PORTBRE
rden_b => ram_block1a19.PORTBRE
rden_b => ram_block1a20.PORTBRE
rden_b => ram_block1a21.PORTBRE
rden_b => ram_block1a22.PORTBRE
rden_b => ram_block1a23.PORTBRE
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a23.PORTAWE


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
rdaddress[5] => rdaddress[5].IN1
rdaddress[6] => rdaddress[6].IN1
rdaddress[7] => rdaddress[7].IN1
rden => rden.IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wraddress[5] => wraddress[5].IN1
wraddress[6] => wraddress[6].IN1
wraddress[7] => wraddress[7].IN1
wren => wren.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram
wren_a => altsyncram_bpf1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => altsyncram_bpf1:auto_generated.rden_b
data_a[0] => altsyncram_bpf1:auto_generated.data_a[0]
data_a[1] => altsyncram_bpf1:auto_generated.data_a[1]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
address_a[0] => altsyncram_bpf1:auto_generated.address_a[0]
address_a[1] => altsyncram_bpf1:auto_generated.address_a[1]
address_a[2] => altsyncram_bpf1:auto_generated.address_a[2]
address_a[3] => altsyncram_bpf1:auto_generated.address_a[3]
address_a[4] => altsyncram_bpf1:auto_generated.address_a[4]
address_a[5] => altsyncram_bpf1:auto_generated.address_a[5]
address_a[6] => altsyncram_bpf1:auto_generated.address_a[6]
address_a[7] => altsyncram_bpf1:auto_generated.address_a[7]
address_b[0] => altsyncram_bpf1:auto_generated.address_b[0]
address_b[1] => altsyncram_bpf1:auto_generated.address_b[1]
address_b[2] => altsyncram_bpf1:auto_generated.address_b[2]
address_b[3] => altsyncram_bpf1:auto_generated.address_b[3]
address_b[4] => altsyncram_bpf1:auto_generated.address_b[4]
address_b[5] => altsyncram_bpf1:auto_generated.address_b[5]
address_b[6] => altsyncram_bpf1:auto_generated.address_b[6]
address_b[7] => altsyncram_bpf1:auto_generated.address_b[7]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_bpf1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_bpf1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
data[8] => data[8].IN1
data[9] => data[9].IN1
data[10] => data[10].IN1
data[11] => data[11].IN1
data[12] => data[12].IN1
data[13] => data[13].IN1
data[14] => data[14].IN1
data[15] => data[15].IN1
data[16] => data[16].IN1
data[17] => data[17].IN1
data[18] => data[18].IN1
data[19] => data[19].IN1
data[20] => data[20].IN1
data[21] => data[21].IN1
data[22] => data[22].IN1
data[23] => data[23].IN1
data[24] => data[24].IN1
data[25] => data[25].IN1
data[26] => data[26].IN1
data[27] => data[27].IN1
data[28] => data[28].IN1
data[29] => data[29].IN1
data[30] => data[30].IN1
data[31] => data[31].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wren => wren.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram
wren_a => altsyncram_b7f1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_b7f1:auto_generated.data_a[0]
data_a[1] => altsyncram_b7f1:auto_generated.data_a[1]
data_a[2] => altsyncram_b7f1:auto_generated.data_a[2]
data_a[3] => altsyncram_b7f1:auto_generated.data_a[3]
data_a[4] => altsyncram_b7f1:auto_generated.data_a[4]
data_a[5] => altsyncram_b7f1:auto_generated.data_a[5]
data_a[6] => altsyncram_b7f1:auto_generated.data_a[6]
data_a[7] => altsyncram_b7f1:auto_generated.data_a[7]
data_a[8] => altsyncram_b7f1:auto_generated.data_a[8]
data_a[9] => altsyncram_b7f1:auto_generated.data_a[9]
data_a[10] => altsyncram_b7f1:auto_generated.data_a[10]
data_a[11] => altsyncram_b7f1:auto_generated.data_a[11]
data_a[12] => altsyncram_b7f1:auto_generated.data_a[12]
data_a[13] => altsyncram_b7f1:auto_generated.data_a[13]
data_a[14] => altsyncram_b7f1:auto_generated.data_a[14]
data_a[15] => altsyncram_b7f1:auto_generated.data_a[15]
data_a[16] => altsyncram_b7f1:auto_generated.data_a[16]
data_a[17] => altsyncram_b7f1:auto_generated.data_a[17]
data_a[18] => altsyncram_b7f1:auto_generated.data_a[18]
data_a[19] => altsyncram_b7f1:auto_generated.data_a[19]
data_a[20] => altsyncram_b7f1:auto_generated.data_a[20]
data_a[21] => altsyncram_b7f1:auto_generated.data_a[21]
data_a[22] => altsyncram_b7f1:auto_generated.data_a[22]
data_a[23] => altsyncram_b7f1:auto_generated.data_a[23]
data_a[24] => altsyncram_b7f1:auto_generated.data_a[24]
data_a[25] => altsyncram_b7f1:auto_generated.data_a[25]
data_a[26] => altsyncram_b7f1:auto_generated.data_a[26]
data_a[27] => altsyncram_b7f1:auto_generated.data_a[27]
data_a[28] => altsyncram_b7f1:auto_generated.data_a[28]
data_a[29] => altsyncram_b7f1:auto_generated.data_a[29]
data_a[30] => altsyncram_b7f1:auto_generated.data_a[30]
data_a[31] => altsyncram_b7f1:auto_generated.data_a[31]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
data_b[16] => ~NO_FANOUT~
data_b[17] => ~NO_FANOUT~
data_b[18] => ~NO_FANOUT~
data_b[19] => ~NO_FANOUT~
data_b[20] => ~NO_FANOUT~
data_b[21] => ~NO_FANOUT~
data_b[22] => ~NO_FANOUT~
data_b[23] => ~NO_FANOUT~
data_b[24] => ~NO_FANOUT~
data_b[25] => ~NO_FANOUT~
data_b[26] => ~NO_FANOUT~
data_b[27] => ~NO_FANOUT~
data_b[28] => ~NO_FANOUT~
data_b[29] => ~NO_FANOUT~
data_b[30] => ~NO_FANOUT~
data_b[31] => ~NO_FANOUT~
address_a[0] => altsyncram_b7f1:auto_generated.address_a[0]
address_a[1] => altsyncram_b7f1:auto_generated.address_a[1]
address_a[2] => altsyncram_b7f1:auto_generated.address_a[2]
address_a[3] => altsyncram_b7f1:auto_generated.address_a[3]
address_a[4] => altsyncram_b7f1:auto_generated.address_a[4]
address_b[0] => altsyncram_b7f1:auto_generated.address_b[0]
address_b[1] => altsyncram_b7f1:auto_generated.address_b[1]
address_b[2] => altsyncram_b7f1:auto_generated.address_b[2]
address_b[3] => altsyncram_b7f1:auto_generated.address_b[3]
address_b[4] => altsyncram_b7f1:auto_generated.address_b[4]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_b7f1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b7f1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[0] => ram_block1a23.PORTBADDR
address_b[0] => ram_block1a24.PORTBADDR
address_b[0] => ram_block1a25.PORTBADDR
address_b[0] => ram_block1a26.PORTBADDR
address_b[0] => ram_block1a27.PORTBADDR
address_b[0] => ram_block1a28.PORTBADDR
address_b[0] => ram_block1a29.PORTBADDR
address_b[0] => ram_block1a30.PORTBADDR
address_b[0] => ram_block1a31.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[1] => ram_block1a23.PORTBADDR1
address_b[1] => ram_block1a24.PORTBADDR1
address_b[1] => ram_block1a25.PORTBADDR1
address_b[1] => ram_block1a26.PORTBADDR1
address_b[1] => ram_block1a27.PORTBADDR1
address_b[1] => ram_block1a28.PORTBADDR1
address_b[1] => ram_block1a29.PORTBADDR1
address_b[1] => ram_block1a30.PORTBADDR1
address_b[1] => ram_block1a31.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[2] => ram_block1a23.PORTBADDR2
address_b[2] => ram_block1a24.PORTBADDR2
address_b[2] => ram_block1a25.PORTBADDR2
address_b[2] => ram_block1a26.PORTBADDR2
address_b[2] => ram_block1a27.PORTBADDR2
address_b[2] => ram_block1a28.PORTBADDR2
address_b[2] => ram_block1a29.PORTBADDR2
address_b[2] => ram_block1a30.PORTBADDR2
address_b[2] => ram_block1a31.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[3] => ram_block1a23.PORTBADDR3
address_b[3] => ram_block1a24.PORTBADDR3
address_b[3] => ram_block1a25.PORTBADDR3
address_b[3] => ram_block1a26.PORTBADDR3
address_b[3] => ram_block1a27.PORTBADDR3
address_b[3] => ram_block1a28.PORTBADDR3
address_b[3] => ram_block1a29.PORTBADDR3
address_b[3] => ram_block1a30.PORTBADDR3
address_b[3] => ram_block1a31.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[4] => ram_block1a24.PORTBADDR4
address_b[4] => ram_block1a25.PORTBADDR4
address_b[4] => ram_block1a26.PORTBADDR4
address_b[4] => ram_block1a27.PORTBADDR4
address_b[4] => ram_block1a28.PORTBADDR4
address_b[4] => ram_block1a29.PORTBADDR4
address_b[4] => ram_block1a30.PORTBADDR4
address_b[4] => ram_block1a31.PORTBADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
data_a[24] => ram_block1a24.PORTADATAIN
data_a[25] => ram_block1a25.PORTADATAIN
data_a[26] => ram_block1a26.PORTADATAIN
data_a[27] => ram_block1a27.PORTADATAIN
data_a[28] => ram_block1a28.PORTADATAIN
data_a[29] => ram_block1a29.PORTADATAIN
data_a[30] => ram_block1a30.PORTADATAIN
data_a[31] => ram_block1a31.PORTADATAIN
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a23.PORTAWE
wren_a => ram_block1a24.PORTAWE
wren_a => ram_block1a25.PORTAWE
wren_a => ram_block1a26.PORTAWE
wren_a => ram_block1a27.PORTAWE
wren_a => ram_block1a28.PORTAWE
wren_a => ram_block1a29.PORTAWE
wren_a => ram_block1a30.PORTAWE
wren_a => ram_block1a31.PORTAWE


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
data[8] => data[8].IN1
data[9] => data[9].IN1
data[10] => data[10].IN1
data[11] => data[11].IN1
data[12] => data[12].IN1
data[13] => data[13].IN1
data[14] => data[14].IN1
data[15] => data[15].IN1
data[16] => data[16].IN1
data[17] => data[17].IN1
data[18] => data[18].IN1
data[19] => data[19].IN1
data[20] => data[20].IN1
data[21] => data[21].IN1
data[22] => data[22].IN1
data[23] => data[23].IN1
data[24] => data[24].IN1
data[25] => data[25].IN1
data[26] => data[26].IN1
data[27] => data[27].IN1
data[28] => data[28].IN1
data[29] => data[29].IN1
data[30] => data[30].IN1
data[31] => data[31].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wren => wren.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram
wren_a => altsyncram_c7f1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_c7f1:auto_generated.data_a[0]
data_a[1] => altsyncram_c7f1:auto_generated.data_a[1]
data_a[2] => altsyncram_c7f1:auto_generated.data_a[2]
data_a[3] => altsyncram_c7f1:auto_generated.data_a[3]
data_a[4] => altsyncram_c7f1:auto_generated.data_a[4]
data_a[5] => altsyncram_c7f1:auto_generated.data_a[5]
data_a[6] => altsyncram_c7f1:auto_generated.data_a[6]
data_a[7] => altsyncram_c7f1:auto_generated.data_a[7]
data_a[8] => altsyncram_c7f1:auto_generated.data_a[8]
data_a[9] => altsyncram_c7f1:auto_generated.data_a[9]
data_a[10] => altsyncram_c7f1:auto_generated.data_a[10]
data_a[11] => altsyncram_c7f1:auto_generated.data_a[11]
data_a[12] => altsyncram_c7f1:auto_generated.data_a[12]
data_a[13] => altsyncram_c7f1:auto_generated.data_a[13]
data_a[14] => altsyncram_c7f1:auto_generated.data_a[14]
data_a[15] => altsyncram_c7f1:auto_generated.data_a[15]
data_a[16] => altsyncram_c7f1:auto_generated.data_a[16]
data_a[17] => altsyncram_c7f1:auto_generated.data_a[17]
data_a[18] => altsyncram_c7f1:auto_generated.data_a[18]
data_a[19] => altsyncram_c7f1:auto_generated.data_a[19]
data_a[20] => altsyncram_c7f1:auto_generated.data_a[20]
data_a[21] => altsyncram_c7f1:auto_generated.data_a[21]
data_a[22] => altsyncram_c7f1:auto_generated.data_a[22]
data_a[23] => altsyncram_c7f1:auto_generated.data_a[23]
data_a[24] => altsyncram_c7f1:auto_generated.data_a[24]
data_a[25] => altsyncram_c7f1:auto_generated.data_a[25]
data_a[26] => altsyncram_c7f1:auto_generated.data_a[26]
data_a[27] => altsyncram_c7f1:auto_generated.data_a[27]
data_a[28] => altsyncram_c7f1:auto_generated.data_a[28]
data_a[29] => altsyncram_c7f1:auto_generated.data_a[29]
data_a[30] => altsyncram_c7f1:auto_generated.data_a[30]
data_a[31] => altsyncram_c7f1:auto_generated.data_a[31]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
data_b[16] => ~NO_FANOUT~
data_b[17] => ~NO_FANOUT~
data_b[18] => ~NO_FANOUT~
data_b[19] => ~NO_FANOUT~
data_b[20] => ~NO_FANOUT~
data_b[21] => ~NO_FANOUT~
data_b[22] => ~NO_FANOUT~
data_b[23] => ~NO_FANOUT~
data_b[24] => ~NO_FANOUT~
data_b[25] => ~NO_FANOUT~
data_b[26] => ~NO_FANOUT~
data_b[27] => ~NO_FANOUT~
data_b[28] => ~NO_FANOUT~
data_b[29] => ~NO_FANOUT~
data_b[30] => ~NO_FANOUT~
data_b[31] => ~NO_FANOUT~
address_a[0] => altsyncram_c7f1:auto_generated.address_a[0]
address_a[1] => altsyncram_c7f1:auto_generated.address_a[1]
address_a[2] => altsyncram_c7f1:auto_generated.address_a[2]
address_a[3] => altsyncram_c7f1:auto_generated.address_a[3]
address_a[4] => altsyncram_c7f1:auto_generated.address_a[4]
address_b[0] => altsyncram_c7f1:auto_generated.address_b[0]
address_b[1] => altsyncram_c7f1:auto_generated.address_b[1]
address_b[2] => altsyncram_c7f1:auto_generated.address_b[2]
address_b[3] => altsyncram_c7f1:auto_generated.address_b[3]
address_b[4] => altsyncram_c7f1:auto_generated.address_b[4]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_c7f1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c7f1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[0] => ram_block1a23.PORTBADDR
address_b[0] => ram_block1a24.PORTBADDR
address_b[0] => ram_block1a25.PORTBADDR
address_b[0] => ram_block1a26.PORTBADDR
address_b[0] => ram_block1a27.PORTBADDR
address_b[0] => ram_block1a28.PORTBADDR
address_b[0] => ram_block1a29.PORTBADDR
address_b[0] => ram_block1a30.PORTBADDR
address_b[0] => ram_block1a31.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[1] => ram_block1a23.PORTBADDR1
address_b[1] => ram_block1a24.PORTBADDR1
address_b[1] => ram_block1a25.PORTBADDR1
address_b[1] => ram_block1a26.PORTBADDR1
address_b[1] => ram_block1a27.PORTBADDR1
address_b[1] => ram_block1a28.PORTBADDR1
address_b[1] => ram_block1a29.PORTBADDR1
address_b[1] => ram_block1a30.PORTBADDR1
address_b[1] => ram_block1a31.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[2] => ram_block1a23.PORTBADDR2
address_b[2] => ram_block1a24.PORTBADDR2
address_b[2] => ram_block1a25.PORTBADDR2
address_b[2] => ram_block1a26.PORTBADDR2
address_b[2] => ram_block1a27.PORTBADDR2
address_b[2] => ram_block1a28.PORTBADDR2
address_b[2] => ram_block1a29.PORTBADDR2
address_b[2] => ram_block1a30.PORTBADDR2
address_b[2] => ram_block1a31.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[3] => ram_block1a23.PORTBADDR3
address_b[3] => ram_block1a24.PORTBADDR3
address_b[3] => ram_block1a25.PORTBADDR3
address_b[3] => ram_block1a26.PORTBADDR3
address_b[3] => ram_block1a27.PORTBADDR3
address_b[3] => ram_block1a28.PORTBADDR3
address_b[3] => ram_block1a29.PORTBADDR3
address_b[3] => ram_block1a30.PORTBADDR3
address_b[3] => ram_block1a31.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[4] => ram_block1a24.PORTBADDR4
address_b[4] => ram_block1a25.PORTBADDR4
address_b[4] => ram_block1a26.PORTBADDR4
address_b[4] => ram_block1a27.PORTBADDR4
address_b[4] => ram_block1a28.PORTBADDR4
address_b[4] => ram_block1a29.PORTBADDR4
address_b[4] => ram_block1a30.PORTBADDR4
address_b[4] => ram_block1a31.PORTBADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
data_a[24] => ram_block1a24.PORTADATAIN
data_a[25] => ram_block1a25.PORTADATAIN
data_a[26] => ram_block1a26.PORTADATAIN
data_a[27] => ram_block1a27.PORTADATAIN
data_a[28] => ram_block1a28.PORTADATAIN
data_a[29] => ram_block1a29.PORTADATAIN
data_a[30] => ram_block1a30.PORTADATAIN
data_a[31] => ram_block1a31.PORTADATAIN
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a23.PORTAWE
wren_a => ram_block1a24.PORTAWE
wren_a => ram_block1a25.PORTAWE
wren_a => ram_block1a26.PORTAWE
wren_a => ram_block1a27.PORTAWE
wren_a => ram_block1a28.PORTAWE
wren_a => ram_block1a29.PORTAWE
wren_a => ram_block1a30.PORTAWE
wren_a => ram_block1a31.PORTAWE


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell
A_mul_src1[0] => A_mul_src1[0].IN1
A_mul_src1[1] => A_mul_src1[1].IN1
A_mul_src1[2] => A_mul_src1[2].IN1
A_mul_src1[3] => A_mul_src1[3].IN1
A_mul_src1[4] => A_mul_src1[4].IN1
A_mul_src1[5] => A_mul_src1[5].IN1
A_mul_src1[6] => A_mul_src1[6].IN1
A_mul_src1[7] => A_mul_src1[7].IN1
A_mul_src1[8] => A_mul_src1[8].IN1
A_mul_src1[9] => A_mul_src1[9].IN1
A_mul_src1[10] => A_mul_src1[10].IN1
A_mul_src1[11] => A_mul_src1[11].IN1
A_mul_src1[12] => A_mul_src1[12].IN1
A_mul_src1[13] => A_mul_src1[13].IN1
A_mul_src1[14] => A_mul_src1[14].IN1
A_mul_src1[15] => A_mul_src1[15].IN1
A_mul_src1[16] => A_mul_src1[16].IN1
A_mul_src1[17] => A_mul_src1[17].IN1
A_mul_src1[18] => A_mul_src1[18].IN1
A_mul_src1[19] => A_mul_src1[19].IN1
A_mul_src1[20] => A_mul_src1[20].IN1
A_mul_src1[21] => A_mul_src1[21].IN1
A_mul_src1[22] => A_mul_src1[22].IN1
A_mul_src1[23] => A_mul_src1[23].IN1
A_mul_src1[24] => A_mul_src1[24].IN1
A_mul_src1[25] => A_mul_src1[25].IN1
A_mul_src1[26] => A_mul_src1[26].IN1
A_mul_src1[27] => A_mul_src1[27].IN1
A_mul_src1[28] => A_mul_src1[28].IN1
A_mul_src1[29] => A_mul_src1[29].IN1
A_mul_src1[30] => A_mul_src1[30].IN1
A_mul_src1[31] => A_mul_src1[31].IN1
A_mul_src2[0] => A_mul_src2[0].IN2
A_mul_src2[1] => A_mul_src2[1].IN2
A_mul_src2[2] => A_mul_src2[2].IN2
A_mul_src2[3] => A_mul_src2[3].IN2
A_mul_src2[4] => A_mul_src2[4].IN2
A_mul_src2[5] => A_mul_src2[5].IN2
A_mul_src2[6] => A_mul_src2[6].IN2
A_mul_src2[7] => A_mul_src2[7].IN2
A_mul_src2[8] => A_mul_src2[8].IN2
A_mul_src2[9] => A_mul_src2[9].IN2
A_mul_src2[10] => A_mul_src2[10].IN2
A_mul_src2[11] => A_mul_src2[11].IN2
A_mul_src2[12] => A_mul_src2[12].IN2
A_mul_src2[13] => A_mul_src2[13].IN2
A_mul_src2[14] => A_mul_src2[14].IN2
A_mul_src2[15] => A_mul_src2[15].IN2
A_mul_src2[16] => ~NO_FANOUT~
A_mul_src2[17] => ~NO_FANOUT~
A_mul_src2[18] => ~NO_FANOUT~
A_mul_src2[19] => ~NO_FANOUT~
A_mul_src2[20] => ~NO_FANOUT~
A_mul_src2[21] => ~NO_FANOUT~
A_mul_src2[22] => ~NO_FANOUT~
A_mul_src2[23] => ~NO_FANOUT~
A_mul_src2[24] => ~NO_FANOUT~
A_mul_src2[25] => ~NO_FANOUT~
A_mul_src2[26] => ~NO_FANOUT~
A_mul_src2[27] => ~NO_FANOUT~
A_mul_src2[28] => ~NO_FANOUT~
A_mul_src2[29] => ~NO_FANOUT~
A_mul_src2[30] => ~NO_FANOUT~
A_mul_src2[31] => ~NO_FANOUT~
clk => clk.IN2
reset_n => mul_clr.IN2


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1
accum_sload => ~NO_FANOUT~
aclr0 => mult_add_mgr2:auto_generated.aclr0
aclr1 => ~NO_FANOUT~
aclr2 => ~NO_FANOUT~
aclr3 => ~NO_FANOUT~
addnsub1 => ~NO_FANOUT~
addnsub1_round => ~NO_FANOUT~
addnsub3 => ~NO_FANOUT~
addnsub3_round => ~NO_FANOUT~
chainin[0] => ~NO_FANOUT~
chainout_round => ~NO_FANOUT~
chainout_saturate => ~NO_FANOUT~
clock0 => mult_add_mgr2:auto_generated.clock0
clock1 => ~NO_FANOUT~
clock2 => ~NO_FANOUT~
clock3 => ~NO_FANOUT~
dataa[0] => mult_add_mgr2:auto_generated.dataa[0]
dataa[1] => mult_add_mgr2:auto_generated.dataa[1]
dataa[2] => mult_add_mgr2:auto_generated.dataa[2]
dataa[3] => mult_add_mgr2:auto_generated.dataa[3]
dataa[4] => mult_add_mgr2:auto_generated.dataa[4]
dataa[5] => mult_add_mgr2:auto_generated.dataa[5]
dataa[6] => mult_add_mgr2:auto_generated.dataa[6]
dataa[7] => mult_add_mgr2:auto_generated.dataa[7]
dataa[8] => mult_add_mgr2:auto_generated.dataa[8]
dataa[9] => mult_add_mgr2:auto_generated.dataa[9]
dataa[10] => mult_add_mgr2:auto_generated.dataa[10]
dataa[11] => mult_add_mgr2:auto_generated.dataa[11]
dataa[12] => mult_add_mgr2:auto_generated.dataa[12]
dataa[13] => mult_add_mgr2:auto_generated.dataa[13]
dataa[14] => mult_add_mgr2:auto_generated.dataa[14]
dataa[15] => mult_add_mgr2:auto_generated.dataa[15]
datab[0] => mult_add_mgr2:auto_generated.datab[0]
datab[1] => mult_add_mgr2:auto_generated.datab[1]
datab[2] => mult_add_mgr2:auto_generated.datab[2]
datab[3] => mult_add_mgr2:auto_generated.datab[3]
datab[4] => mult_add_mgr2:auto_generated.datab[4]
datab[5] => mult_add_mgr2:auto_generated.datab[5]
datab[6] => mult_add_mgr2:auto_generated.datab[6]
datab[7] => mult_add_mgr2:auto_generated.datab[7]
datab[8] => mult_add_mgr2:auto_generated.datab[8]
datab[9] => mult_add_mgr2:auto_generated.datab[9]
datab[10] => mult_add_mgr2:auto_generated.datab[10]
datab[11] => mult_add_mgr2:auto_generated.datab[11]
datab[12] => mult_add_mgr2:auto_generated.datab[12]
datab[13] => mult_add_mgr2:auto_generated.datab[13]
datab[14] => mult_add_mgr2:auto_generated.datab[14]
datab[15] => mult_add_mgr2:auto_generated.datab[15]
ena0 => ~NO_FANOUT~
ena1 => ~NO_FANOUT~
ena2 => ~NO_FANOUT~
ena3 => ~NO_FANOUT~
mult01_round => ~NO_FANOUT~
mult01_saturation => ~NO_FANOUT~
mult23_round => ~NO_FANOUT~
mult23_saturation => ~NO_FANOUT~
output_round => ~NO_FANOUT~
output_saturate => ~NO_FANOUT~
rotate => ~NO_FANOUT~
scanina[0] => ~NO_FANOUT~
scanina[1] => ~NO_FANOUT~
scanina[2] => ~NO_FANOUT~
scanina[3] => ~NO_FANOUT~
scanina[4] => ~NO_FANOUT~
scanina[5] => ~NO_FANOUT~
scanina[6] => ~NO_FANOUT~
scanina[7] => ~NO_FANOUT~
scanina[8] => ~NO_FANOUT~
scanina[9] => ~NO_FANOUT~
scanina[10] => ~NO_FANOUT~
scanina[11] => ~NO_FANOUT~
scanina[12] => ~NO_FANOUT~
scanina[13] => ~NO_FANOUT~
scanina[14] => ~NO_FANOUT~
scanina[15] => ~NO_FANOUT~
scaninb[0] => ~NO_FANOUT~
scaninb[1] => ~NO_FANOUT~
scaninb[2] => ~NO_FANOUT~
scaninb[3] => ~NO_FANOUT~
scaninb[4] => ~NO_FANOUT~
scaninb[5] => ~NO_FANOUT~
scaninb[6] => ~NO_FANOUT~
scaninb[7] => ~NO_FANOUT~
scaninb[8] => ~NO_FANOUT~
scaninb[9] => ~NO_FANOUT~
scaninb[10] => ~NO_FANOUT~
scaninb[11] => ~NO_FANOUT~
scaninb[12] => ~NO_FANOUT~
scaninb[13] => ~NO_FANOUT~
scaninb[14] => ~NO_FANOUT~
scaninb[15] => ~NO_FANOUT~
shift_right => ~NO_FANOUT~
signa => ~NO_FANOUT~
signb => ~NO_FANOUT~
sourcea[0] => ~NO_FANOUT~
sourceb[0] => ~NO_FANOUT~
zero_chainout => ~NO_FANOUT~
zero_loopback => ~NO_FANOUT~
coefsel0[0] => ~NO_FANOUT~
coefsel0[1] => ~NO_FANOUT~
coefsel0[2] => ~NO_FANOUT~
coefsel1[0] => ~NO_FANOUT~
coefsel1[1] => ~NO_FANOUT~
coefsel1[2] => ~NO_FANOUT~
coefsel2[0] => ~NO_FANOUT~
coefsel2[1] => ~NO_FANOUT~
coefsel2[2] => ~NO_FANOUT~
coefsel3[0] => ~NO_FANOUT~
coefsel3[1] => ~NO_FANOUT~
coefsel3[2] => ~NO_FANOUT~
datac[0] => ~NO_FANOUT~
datac[1] => ~NO_FANOUT~
datac[2] => ~NO_FANOUT~
datac[3] => ~NO_FANOUT~
datac[4] => ~NO_FANOUT~
datac[5] => ~NO_FANOUT~
datac[6] => ~NO_FANOUT~
datac[7] => ~NO_FANOUT~
datac[8] => ~NO_FANOUT~
datac[9] => ~NO_FANOUT~
datac[10] => ~NO_FANOUT~
datac[11] => ~NO_FANOUT~
datac[12] => ~NO_FANOUT~
datac[13] => ~NO_FANOUT~
datac[14] => ~NO_FANOUT~
datac[15] => ~NO_FANOUT~
datac[16] => ~NO_FANOUT~
datac[17] => ~NO_FANOUT~
datac[18] => ~NO_FANOUT~
datac[19] => ~NO_FANOUT~
datac[20] => ~NO_FANOUT~
datac[21] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated
aclr0 => ded_mult_ks81:ded_mult1.aclr[0]
clock0 => ded_mult_ks81:ded_mult1.clock[0]
dataa[0] => ded_mult_ks81:ded_mult1.dataa[0]
dataa[1] => ded_mult_ks81:ded_mult1.dataa[1]
dataa[2] => ded_mult_ks81:ded_mult1.dataa[2]
dataa[3] => ded_mult_ks81:ded_mult1.dataa[3]
dataa[4] => ded_mult_ks81:ded_mult1.dataa[4]
dataa[5] => ded_mult_ks81:ded_mult1.dataa[5]
dataa[6] => ded_mult_ks81:ded_mult1.dataa[6]
dataa[7] => ded_mult_ks81:ded_mult1.dataa[7]
dataa[8] => ded_mult_ks81:ded_mult1.dataa[8]
dataa[9] => ded_mult_ks81:ded_mult1.dataa[9]
dataa[10] => ded_mult_ks81:ded_mult1.dataa[10]
dataa[11] => ded_mult_ks81:ded_mult1.dataa[11]
dataa[12] => ded_mult_ks81:ded_mult1.dataa[12]
dataa[13] => ded_mult_ks81:ded_mult1.dataa[13]
dataa[14] => ded_mult_ks81:ded_mult1.dataa[14]
dataa[15] => ded_mult_ks81:ded_mult1.dataa[15]
datab[0] => ded_mult_ks81:ded_mult1.datab[0]
datab[1] => ded_mult_ks81:ded_mult1.datab[1]
datab[2] => ded_mult_ks81:ded_mult1.datab[2]
datab[3] => ded_mult_ks81:ded_mult1.datab[3]
datab[4] => ded_mult_ks81:ded_mult1.datab[4]
datab[5] => ded_mult_ks81:ded_mult1.datab[5]
datab[6] => ded_mult_ks81:ded_mult1.datab[6]
datab[7] => ded_mult_ks81:ded_mult1.datab[7]
datab[8] => ded_mult_ks81:ded_mult1.datab[8]
datab[9] => ded_mult_ks81:ded_mult1.datab[9]
datab[10] => ded_mult_ks81:ded_mult1.datab[10]
datab[11] => ded_mult_ks81:ded_mult1.datab[11]
datab[12] => ded_mult_ks81:ded_mult1.datab[12]
datab[13] => ded_mult_ks81:ded_mult1.datab[13]
datab[14] => ded_mult_ks81:ded_mult1.datab[14]
datab[15] => ded_mult_ks81:ded_mult1.datab[15]


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1
aclr[0] => mac_mult2.ACLR
aclr[0] => mac_out3.ACLR
aclr[1] => ~NO_FANOUT~
aclr[2] => ~NO_FANOUT~
aclr[3] => ~NO_FANOUT~
clock[0] => mac_mult2.CLK
clock[0] => mac_out3.CLK
clock[1] => ~NO_FANOUT~
clock[2] => ~NO_FANOUT~
clock[3] => ~NO_FANOUT~
dataa[0] => mac_mult2.DATAA
dataa[1] => mac_mult2.DATAA1
dataa[2] => mac_mult2.DATAA2
dataa[3] => mac_mult2.DATAA3
dataa[4] => mac_mult2.DATAA4
dataa[5] => mac_mult2.DATAA5
dataa[6] => mac_mult2.DATAA6
dataa[7] => mac_mult2.DATAA7
dataa[8] => mac_mult2.DATAA8
dataa[9] => mac_mult2.DATAA9
dataa[10] => mac_mult2.DATAA10
dataa[11] => mac_mult2.DATAA11
dataa[12] => mac_mult2.DATAA12
dataa[13] => mac_mult2.DATAA13
dataa[14] => mac_mult2.DATAA14
dataa[15] => mac_mult2.DATAA15
datab[0] => mac_mult2.DATAB
datab[1] => mac_mult2.DATAB1
datab[2] => mac_mult2.DATAB2
datab[3] => mac_mult2.DATAB3
datab[4] => mac_mult2.DATAB4
datab[5] => mac_mult2.DATAB5
datab[6] => mac_mult2.DATAB6
datab[7] => mac_mult2.DATAB7
datab[8] => mac_mult2.DATAB8
datab[9] => mac_mult2.DATAB9
datab[10] => mac_mult2.DATAB10
datab[11] => mac_mult2.DATAB11
datab[12] => mac_mult2.DATAB12
datab[13] => mac_mult2.DATAB13
datab[14] => mac_mult2.DATAB14
datab[15] => mac_mult2.DATAB15
ena[0] => mac_mult2.ENA
ena[0] => mac_out3.ENA
ena[1] => ~NO_FANOUT~
ena[2] => ~NO_FANOUT~
ena[3] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
d[7] => q[7].DATAIN
d[8] => q[8].DATAIN
d[9] => q[9].DATAIN
d[10] => q[10].DATAIN
d[11] => q[11].DATAIN
d[12] => q[12].DATAIN
d[13] => q[13].DATAIN
d[14] => q[14].DATAIN
d[15] => q[15].DATAIN
d[16] => q[16].DATAIN
d[17] => q[17].DATAIN
d[18] => q[18].DATAIN
d[19] => q[19].DATAIN
d[20] => q[20].DATAIN
d[21] => q[21].DATAIN
d[22] => q[22].DATAIN
d[23] => q[23].DATAIN
d[24] => q[24].DATAIN
d[25] => q[25].DATAIN
d[26] => q[26].DATAIN
d[27] => q[27].DATAIN
d[28] => q[28].DATAIN
d[29] => q[29].DATAIN
d[30] => q[30].DATAIN
d[31] => q[31].DATAIN


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2
accum_sload => ~NO_FANOUT~
aclr0 => mult_add_ogr2:auto_generated.aclr0
aclr1 => ~NO_FANOUT~
aclr2 => ~NO_FANOUT~
aclr3 => ~NO_FANOUT~
addnsub1 => ~NO_FANOUT~
addnsub1_round => ~NO_FANOUT~
addnsub3 => ~NO_FANOUT~
addnsub3_round => ~NO_FANOUT~
chainin[0] => ~NO_FANOUT~
chainout_round => ~NO_FANOUT~
chainout_saturate => ~NO_FANOUT~
clock0 => mult_add_ogr2:auto_generated.clock0
clock1 => ~NO_FANOUT~
clock2 => ~NO_FANOUT~
clock3 => ~NO_FANOUT~
dataa[0] => mult_add_ogr2:auto_generated.dataa[0]
dataa[1] => mult_add_ogr2:auto_generated.dataa[1]
dataa[2] => mult_add_ogr2:auto_generated.dataa[2]
dataa[3] => mult_add_ogr2:auto_generated.dataa[3]
dataa[4] => mult_add_ogr2:auto_generated.dataa[4]
dataa[5] => mult_add_ogr2:auto_generated.dataa[5]
dataa[6] => mult_add_ogr2:auto_generated.dataa[6]
dataa[7] => mult_add_ogr2:auto_generated.dataa[7]
dataa[8] => mult_add_ogr2:auto_generated.dataa[8]
dataa[9] => mult_add_ogr2:auto_generated.dataa[9]
dataa[10] => mult_add_ogr2:auto_generated.dataa[10]
dataa[11] => mult_add_ogr2:auto_generated.dataa[11]
dataa[12] => mult_add_ogr2:auto_generated.dataa[12]
dataa[13] => mult_add_ogr2:auto_generated.dataa[13]
dataa[14] => mult_add_ogr2:auto_generated.dataa[14]
dataa[15] => mult_add_ogr2:auto_generated.dataa[15]
datab[0] => mult_add_ogr2:auto_generated.datab[0]
datab[1] => mult_add_ogr2:auto_generated.datab[1]
datab[2] => mult_add_ogr2:auto_generated.datab[2]
datab[3] => mult_add_ogr2:auto_generated.datab[3]
datab[4] => mult_add_ogr2:auto_generated.datab[4]
datab[5] => mult_add_ogr2:auto_generated.datab[5]
datab[6] => mult_add_ogr2:auto_generated.datab[6]
datab[7] => mult_add_ogr2:auto_generated.datab[7]
datab[8] => mult_add_ogr2:auto_generated.datab[8]
datab[9] => mult_add_ogr2:auto_generated.datab[9]
datab[10] => mult_add_ogr2:auto_generated.datab[10]
datab[11] => mult_add_ogr2:auto_generated.datab[11]
datab[12] => mult_add_ogr2:auto_generated.datab[12]
datab[13] => mult_add_ogr2:auto_generated.datab[13]
datab[14] => mult_add_ogr2:auto_generated.datab[14]
datab[15] => mult_add_ogr2:auto_generated.datab[15]
ena0 => ~NO_FANOUT~
ena1 => ~NO_FANOUT~
ena2 => ~NO_FANOUT~
ena3 => ~NO_FANOUT~
mult01_round => ~NO_FANOUT~
mult01_saturation => ~NO_FANOUT~
mult23_round => ~NO_FANOUT~
mult23_saturation => ~NO_FANOUT~
output_round => ~NO_FANOUT~
output_saturate => ~NO_FANOUT~
rotate => ~NO_FANOUT~
scanina[0] => ~NO_FANOUT~
scanina[1] => ~NO_FANOUT~
scanina[2] => ~NO_FANOUT~
scanina[3] => ~NO_FANOUT~
scanina[4] => ~NO_FANOUT~
scanina[5] => ~NO_FANOUT~
scanina[6] => ~NO_FANOUT~
scanina[7] => ~NO_FANOUT~
scanina[8] => ~NO_FANOUT~
scanina[9] => ~NO_FANOUT~
scanina[10] => ~NO_FANOUT~
scanina[11] => ~NO_FANOUT~
scanina[12] => ~NO_FANOUT~
scanina[13] => ~NO_FANOUT~
scanina[14] => ~NO_FANOUT~
scanina[15] => ~NO_FANOUT~
scaninb[0] => ~NO_FANOUT~
scaninb[1] => ~NO_FANOUT~
scaninb[2] => ~NO_FANOUT~
scaninb[3] => ~NO_FANOUT~
scaninb[4] => ~NO_FANOUT~
scaninb[5] => ~NO_FANOUT~
scaninb[6] => ~NO_FANOUT~
scaninb[7] => ~NO_FANOUT~
scaninb[8] => ~NO_FANOUT~
scaninb[9] => ~NO_FANOUT~
scaninb[10] => ~NO_FANOUT~
scaninb[11] => ~NO_FANOUT~
scaninb[12] => ~NO_FANOUT~
scaninb[13] => ~NO_FANOUT~
scaninb[14] => ~NO_FANOUT~
scaninb[15] => ~NO_FANOUT~
shift_right => ~NO_FANOUT~
signa => ~NO_FANOUT~
signb => ~NO_FANOUT~
sourcea[0] => ~NO_FANOUT~
sourceb[0] => ~NO_FANOUT~
zero_chainout => ~NO_FANOUT~
zero_loopback => ~NO_FANOUT~
coefsel0[0] => ~NO_FANOUT~
coefsel0[1] => ~NO_FANOUT~
coefsel0[2] => ~NO_FANOUT~
coefsel1[0] => ~NO_FANOUT~
coefsel1[1] => ~NO_FANOUT~
coefsel1[2] => ~NO_FANOUT~
coefsel2[0] => ~NO_FANOUT~
coefsel2[1] => ~NO_FANOUT~
coefsel2[2] => ~NO_FANOUT~
coefsel3[0] => ~NO_FANOUT~
coefsel3[1] => ~NO_FANOUT~
coefsel3[2] => ~NO_FANOUT~
datac[0] => ~NO_FANOUT~
datac[1] => ~NO_FANOUT~
datac[2] => ~NO_FANOUT~
datac[3] => ~NO_FANOUT~
datac[4] => ~NO_FANOUT~
datac[5] => ~NO_FANOUT~
datac[6] => ~NO_FANOUT~
datac[7] => ~NO_FANOUT~
datac[8] => ~NO_FANOUT~
datac[9] => ~NO_FANOUT~
datac[10] => ~NO_FANOUT~
datac[11] => ~NO_FANOUT~
datac[12] => ~NO_FANOUT~
datac[13] => ~NO_FANOUT~
datac[14] => ~NO_FANOUT~
datac[15] => ~NO_FANOUT~
datac[16] => ~NO_FANOUT~
datac[17] => ~NO_FANOUT~
datac[18] => ~NO_FANOUT~
datac[19] => ~NO_FANOUT~
datac[20] => ~NO_FANOUT~
datac[21] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated
aclr0 => ded_mult_ks81:ded_mult1.aclr[0]
clock0 => ded_mult_ks81:ded_mult1.clock[0]
dataa[0] => ded_mult_ks81:ded_mult1.dataa[0]
dataa[1] => ded_mult_ks81:ded_mult1.dataa[1]
dataa[2] => ded_mult_ks81:ded_mult1.dataa[2]
dataa[3] => ded_mult_ks81:ded_mult1.dataa[3]
dataa[4] => ded_mult_ks81:ded_mult1.dataa[4]
dataa[5] => ded_mult_ks81:ded_mult1.dataa[5]
dataa[6] => ded_mult_ks81:ded_mult1.dataa[6]
dataa[7] => ded_mult_ks81:ded_mult1.dataa[7]
dataa[8] => ded_mult_ks81:ded_mult1.dataa[8]
dataa[9] => ded_mult_ks81:ded_mult1.dataa[9]
dataa[10] => ded_mult_ks81:ded_mult1.dataa[10]
dataa[11] => ded_mult_ks81:ded_mult1.dataa[11]
dataa[12] => ded_mult_ks81:ded_mult1.dataa[12]
dataa[13] => ded_mult_ks81:ded_mult1.dataa[13]
dataa[14] => ded_mult_ks81:ded_mult1.dataa[14]
dataa[15] => ded_mult_ks81:ded_mult1.dataa[15]
datab[0] => ded_mult_ks81:ded_mult1.datab[0]
datab[1] => ded_mult_ks81:ded_mult1.datab[1]
datab[2] => ded_mult_ks81:ded_mult1.datab[2]
datab[3] => ded_mult_ks81:ded_mult1.datab[3]
datab[4] => ded_mult_ks81:ded_mult1.datab[4]
datab[5] => ded_mult_ks81:ded_mult1.datab[5]
datab[6] => ded_mult_ks81:ded_mult1.datab[6]
datab[7] => ded_mult_ks81:ded_mult1.datab[7]
datab[8] => ded_mult_ks81:ded_mult1.datab[8]
datab[9] => ded_mult_ks81:ded_mult1.datab[9]
datab[10] => ded_mult_ks81:ded_mult1.datab[10]
datab[11] => ded_mult_ks81:ded_mult1.datab[11]
datab[12] => ded_mult_ks81:ded_mult1.datab[12]
datab[13] => ded_mult_ks81:ded_mult1.datab[13]
datab[14] => ded_mult_ks81:ded_mult1.datab[14]
datab[15] => ded_mult_ks81:ded_mult1.datab[15]


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated|ded_mult_ks81:ded_mult1
aclr[0] => mac_mult2.ACLR
aclr[0] => mac_out3.ACLR
aclr[1] => ~NO_FANOUT~
aclr[2] => ~NO_FANOUT~
aclr[3] => ~NO_FANOUT~
clock[0] => mac_mult2.CLK
clock[0] => mac_out3.CLK
clock[1] => ~NO_FANOUT~
clock[2] => ~NO_FANOUT~
clock[3] => ~NO_FANOUT~
dataa[0] => mac_mult2.DATAA
dataa[1] => mac_mult2.DATAA1
dataa[2] => mac_mult2.DATAA2
dataa[3] => mac_mult2.DATAA3
dataa[4] => mac_mult2.DATAA4
dataa[5] => mac_mult2.DATAA5
dataa[6] => mac_mult2.DATAA6
dataa[7] => mac_mult2.DATAA7
dataa[8] => mac_mult2.DATAA8
dataa[9] => mac_mult2.DATAA9
dataa[10] => mac_mult2.DATAA10
dataa[11] => mac_mult2.DATAA11
dataa[12] => mac_mult2.DATAA12
dataa[13] => mac_mult2.DATAA13
dataa[14] => mac_mult2.DATAA14
dataa[15] => mac_mult2.DATAA15
datab[0] => mac_mult2.DATAB
datab[1] => mac_mult2.DATAB1
datab[2] => mac_mult2.DATAB2
datab[3] => mac_mult2.DATAB3
datab[4] => mac_mult2.DATAB4
datab[5] => mac_mult2.DATAB5
datab[6] => mac_mult2.DATAB6
datab[7] => mac_mult2.DATAB7
datab[8] => mac_mult2.DATAB8
datab[9] => mac_mult2.DATAB9
datab[10] => mac_mult2.DATAB10
datab[11] => mac_mult2.DATAB11
datab[12] => mac_mult2.DATAB12
datab[13] => mac_mult2.DATAB13
datab[14] => mac_mult2.DATAB14
datab[15] => mac_mult2.DATAB15
ena[0] => mac_mult2.ENA
ena[0] => mac_out3.ENA
ena[1] => ~NO_FANOUT~
ena[2] => ~NO_FANOUT~
ena[3] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
d[7] => q[7].DATAIN
d[8] => q[8].DATAIN
d[9] => q[9].DATAIN
d[10] => q[10].DATAIN
d[11] => q[11].DATAIN
d[12] => q[12].DATAIN
d[13] => q[13].DATAIN
d[14] => q[14].DATAIN
d[15] => q[15].DATAIN
d[16] => q[16].DATAIN
d[17] => q[17].DATAIN
d[18] => q[18].DATAIN
d[19] => q[19].DATAIN
d[20] => q[20].DATAIN
d[21] => q[21].DATAIN
d[22] => q[22].DATAIN
d[23] => q[23].DATAIN
d[24] => q[24].DATAIN
d[25] => q[25].DATAIN
d[26] => q[26].DATAIN
d[27] => q[27].DATAIN
d[28] => q[28].DATAIN
d[29] => q[29].DATAIN
d[30] => q[30].DATAIN
d[31] => q[31].DATAIN


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci
A_cmp_result => A_cmp_result.IN1
A_ctrl_exception => A_ctrl_exception.IN1
A_ctrl_ld => A_ctrl_ld.IN1
A_ctrl_st => A_ctrl_st.IN1
A_en => A_en.IN2
A_mem_baddr[0] => A_mem_baddr[0].IN1
A_mem_baddr[1] => A_mem_baddr[1].IN1
A_mem_baddr[2] => A_mem_baddr[2].IN1
A_mem_baddr[3] => A_mem_baddr[3].IN1
A_mem_baddr[4] => A_mem_baddr[4].IN1
A_mem_baddr[5] => A_mem_baddr[5].IN1
A_mem_baddr[6] => A_mem_baddr[6].IN1
A_mem_baddr[7] => A_mem_baddr[7].IN1
A_mem_baddr[8] => A_mem_baddr[8].IN1
A_mem_baddr[9] => A_mem_baddr[9].IN1
A_mem_baddr[10] => A_mem_baddr[10].IN1
A_mem_baddr[11] => A_mem_baddr[11].IN1
A_mem_baddr[12] => A_mem_baddr[12].IN1
A_mem_baddr[13] => A_mem_baddr[13].IN1
A_mem_baddr[14] => A_mem_baddr[14].IN1
A_mem_baddr[15] => A_mem_baddr[15].IN1
A_mem_baddr[16] => A_mem_baddr[16].IN1
A_mem_baddr[17] => A_mem_baddr[17].IN1
A_mem_baddr[18] => A_mem_baddr[18].IN1
A_mem_baddr[19] => A_mem_baddr[19].IN1
A_mem_baddr[20] => A_mem_baddr[20].IN1
A_mem_baddr[21] => A_mem_baddr[21].IN1
A_mem_baddr[22] => A_mem_baddr[22].IN1
A_mem_baddr[23] => A_mem_baddr[23].IN1
A_mem_baddr[24] => A_mem_baddr[24].IN1
A_mem_baddr[25] => A_mem_baddr[25].IN1
A_mem_baddr[26] => A_mem_baddr[26].IN1
A_op_beq => A_op_beq.IN1
A_op_bge => A_op_bge.IN1
A_op_bgeu => A_op_bgeu.IN1
A_op_blt => A_op_blt.IN1
A_op_bltu => A_op_bltu.IN1
A_op_bne => A_op_bne.IN1
A_op_br => A_op_br.IN1
A_op_bret => A_op_bret.IN1
A_op_call => A_op_call.IN1
A_op_callr => A_op_callr.IN1
A_op_eret => A_op_eret.IN1
A_op_jmp => A_op_jmp.IN1
A_op_jmpi => A_op_jmpi.IN1
A_op_ret => A_op_ret.IN1
A_pcb[0] => A_pcb[0].IN1
A_pcb[1] => A_pcb[1].IN1
A_pcb[2] => A_pcb[2].IN1
A_pcb[3] => A_pcb[3].IN1
A_pcb[4] => A_pcb[4].IN1
A_pcb[5] => A_pcb[5].IN1
A_pcb[6] => A_pcb[6].IN1
A_pcb[7] => A_pcb[7].IN1
A_pcb[8] => A_pcb[8].IN1
A_pcb[9] => A_pcb[9].IN1
A_pcb[10] => A_pcb[10].IN1
A_pcb[11] => A_pcb[11].IN1
A_pcb[12] => A_pcb[12].IN1
A_pcb[13] => A_pcb[13].IN1
A_pcb[14] => A_pcb[14].IN1
A_pcb[15] => A_pcb[15].IN1
A_pcb[16] => A_pcb[16].IN1
A_pcb[17] => A_pcb[17].IN1
A_pcb[18] => A_pcb[18].IN1
A_pcb[19] => A_pcb[19].IN1
A_pcb[20] => A_pcb[20].IN1
A_pcb[21] => A_pcb[21].IN1
A_pcb[22] => A_pcb[22].IN1
A_pcb[23] => A_pcb[23].IN1
A_pcb[24] => A_pcb[24].IN1
A_pcb[25] => A_pcb[25].IN1
A_pcb[26] => A_pcb[26].IN1
A_st_data[0] => A_st_data[0].IN1
A_st_data[1] => A_st_data[1].IN1
A_st_data[2] => A_st_data[2].IN1
A_st_data[3] => A_st_data[3].IN1
A_st_data[4] => A_st_data[4].IN1
A_st_data[5] => A_st_data[5].IN1
A_st_data[6] => A_st_data[6].IN1
A_st_data[7] => A_st_data[7].IN1
A_st_data[8] => A_st_data[8].IN1
A_st_data[9] => A_st_data[9].IN1
A_st_data[10] => A_st_data[10].IN1
A_st_data[11] => A_st_data[11].IN1
A_st_data[12] => A_st_data[12].IN1
A_st_data[13] => A_st_data[13].IN1
A_st_data[14] => A_st_data[14].IN1
A_st_data[15] => A_st_data[15].IN1
A_st_data[16] => A_st_data[16].IN1
A_st_data[17] => A_st_data[17].IN1
A_st_data[18] => A_st_data[18].IN1
A_st_data[19] => A_st_data[19].IN1
A_st_data[20] => A_st_data[20].IN1
A_st_data[21] => A_st_data[21].IN1
A_st_data[22] => A_st_data[22].IN1
A_st_data[23] => A_st_data[23].IN1
A_st_data[24] => A_st_data[24].IN1
A_st_data[25] => A_st_data[25].IN1
A_st_data[26] => A_st_data[26].IN1
A_st_data[27] => A_st_data[27].IN1
A_st_data[28] => A_st_data[28].IN1
A_st_data[29] => A_st_data[29].IN1
A_st_data[30] => A_st_data[30].IN1
A_st_data[31] => A_st_data[31].IN1
A_valid => A_valid.IN2
A_wr_data_filtered[0] => A_wr_data_filtered[0].IN2
A_wr_data_filtered[1] => A_wr_data_filtered[1].IN2
A_wr_data_filtered[2] => A_wr_data_filtered[2].IN2
A_wr_data_filtered[3] => A_wr_data_filtered[3].IN2
A_wr_data_filtered[4] => A_wr_data_filtered[4].IN2
A_wr_data_filtered[5] => A_wr_data_filtered[5].IN2
A_wr_data_filtered[6] => A_wr_data_filtered[6].IN2
A_wr_data_filtered[7] => A_wr_data_filtered[7].IN2
A_wr_data_filtered[8] => A_wr_data_filtered[8].IN2
A_wr_data_filtered[9] => A_wr_data_filtered[9].IN2
A_wr_data_filtered[10] => A_wr_data_filtered[10].IN2
A_wr_data_filtered[11] => A_wr_data_filtered[11].IN2
A_wr_data_filtered[12] => A_wr_data_filtered[12].IN2
A_wr_data_filtered[13] => A_wr_data_filtered[13].IN2
A_wr_data_filtered[14] => A_wr_data_filtered[14].IN2
A_wr_data_filtered[15] => A_wr_data_filtered[15].IN2
A_wr_data_filtered[16] => A_wr_data_filtered[16].IN2
A_wr_data_filtered[17] => A_wr_data_filtered[17].IN2
A_wr_data_filtered[18] => A_wr_data_filtered[18].IN2
A_wr_data_filtered[19] => A_wr_data_filtered[19].IN2
A_wr_data_filtered[20] => A_wr_data_filtered[20].IN2
A_wr_data_filtered[21] => A_wr_data_filtered[21].IN2
A_wr_data_filtered[22] => A_wr_data_filtered[22].IN2
A_wr_data_filtered[23] => A_wr_data_filtered[23].IN2
A_wr_data_filtered[24] => A_wr_data_filtered[24].IN2
A_wr_data_filtered[25] => A_wr_data_filtered[25].IN2
A_wr_data_filtered[26] => A_wr_data_filtered[26].IN2
A_wr_data_filtered[27] => A_wr_data_filtered[27].IN2
A_wr_data_filtered[28] => A_wr_data_filtered[28].IN2
A_wr_data_filtered[29] => A_wr_data_filtered[29].IN2
A_wr_data_filtered[30] => A_wr_data_filtered[30].IN2
A_wr_data_filtered[31] => A_wr_data_filtered[31].IN2
D_en => D_en.IN1
E_en => E_en.IN1
E_valid => E_valid.IN1
F_pc[0] => F_pc[0].IN1
F_pc[1] => F_pc[1].IN1
F_pc[2] => F_pc[2].IN1
F_pc[3] => F_pc[3].IN1
F_pc[4] => F_pc[4].IN1
F_pc[5] => F_pc[5].IN1
F_pc[6] => F_pc[6].IN1
F_pc[7] => F_pc[7].IN1
F_pc[8] => F_pc[8].IN1
F_pc[9] => F_pc[9].IN1
F_pc[10] => F_pc[10].IN1
F_pc[11] => F_pc[11].IN1
F_pc[12] => F_pc[12].IN1
F_pc[13] => F_pc[13].IN1
F_pc[14] => F_pc[14].IN1
F_pc[15] => F_pc[15].IN1
F_pc[16] => F_pc[16].IN1
F_pc[17] => F_pc[17].IN1
F_pc[18] => F_pc[18].IN1
F_pc[19] => F_pc[19].IN1
F_pc[20] => F_pc[20].IN1
F_pc[21] => F_pc[21].IN1
F_pc[22] => F_pc[22].IN1
F_pc[23] => F_pc[23].IN1
F_pc[24] => F_pc[24].IN1
M_en => M_en.IN1
address[0] => address[0].IN2
address[1] => address[1].IN2
address[2] => address[2].IN2
address[3] => address[3].IN2
address[4] => address[4].IN2
address[5] => address[5].IN2
address[6] => address[6].IN2
address[7] => address[7].IN2
address[8] => address[8].IN2
begintransfer => begintransfer.IN1
byteenable[0] => byteenable[0].IN1
byteenable[1] => byteenable[1].IN1
byteenable[2] => byteenable[2].IN1
byteenable[3] => byteenable[3].IN1
chipselect => chipselect.IN2
clk => clk.IN12
debugaccess => debugaccess.IN2
hbreak_enabled => hbreak_enabled.IN1
reset => reset.IN1
reset_n => reset_n.IN8
test_ending => test_ending.IN1
test_has_ended => test_has_ended.IN1
write => write.IN2
writedata[0] => writedata[0].IN2
writedata[1] => writedata[1].IN2
writedata[2] => writedata[2].IN2
writedata[3] => writedata[3].IN2
writedata[4] => writedata[4].IN2
writedata[5] => writedata[5].IN2
writedata[6] => writedata[6].IN2
writedata[7] => writedata[7].IN2
writedata[8] => writedata[8].IN2
writedata[9] => writedata[9].IN2
writedata[10] => writedata[10].IN2
writedata[11] => writedata[11].IN2
writedata[12] => writedata[12].IN2
writedata[13] => writedata[13].IN2
writedata[14] => writedata[14].IN2
writedata[15] => writedata[15].IN2
writedata[16] => writedata[16].IN2
writedata[17] => writedata[17].IN2
writedata[18] => writedata[18].IN2
writedata[19] => writedata[19].IN2
writedata[20] => writedata[20].IN2
writedata[21] => writedata[21].IN2
writedata[22] => writedata[22].IN2
writedata[23] => writedata[23].IN2
writedata[24] => writedata[24].IN2
writedata[25] => writedata[25].IN2
writedata[26] => writedata[26].IN2
writedata[27] => writedata[27].IN2
writedata[28] => writedata[28].IN2
writedata[29] => writedata[29].IN2
writedata[30] => writedata[30].IN2
writedata[31] => writedata[31].IN2


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug
clk => monitor_go~reg0.CLK
clk => monitor_error~reg0.CLK
clk => monitor_ready~reg0.CLK
clk => resetlatch~reg0.CLK
clk => jtag_break.CLK
clk => resetrequest~reg0.CLK
clk => probepresent.CLK
dbrk_break => oci_hbreak_req.IN1
debugreq => always0.IN0
debugreq => oci_hbreak_req.IN1
hbreak_enabled => always0.IN1
hbreak_enabled => debugack.DATAIN
jdo[0] => ~NO_FANOUT~
jdo[1] => ~NO_FANOUT~
jdo[2] => ~NO_FANOUT~
jdo[3] => ~NO_FANOUT~
jdo[4] => ~NO_FANOUT~
jdo[5] => ~NO_FANOUT~
jdo[6] => ~NO_FANOUT~
jdo[7] => ~NO_FANOUT~
jdo[8] => ~NO_FANOUT~
jdo[9] => ~NO_FANOUT~
jdo[10] => ~NO_FANOUT~
jdo[11] => ~NO_FANOUT~
jdo[12] => ~NO_FANOUT~
jdo[13] => ~NO_FANOUT~
jdo[14] => ~NO_FANOUT~
jdo[15] => ~NO_FANOUT~
jdo[16] => ~NO_FANOUT~
jdo[17] => ~NO_FANOUT~
jdo[18] => probepresent.OUTPUTSELECT
jdo[19] => probepresent.OUTPUTSELECT
jdo[20] => jtag_break.OUTPUTSELECT
jdo[21] => jtag_break.OUTPUTSELECT
jdo[22] => resetrequest~reg0.DATAIN
jdo[23] => always1.IN0
jdo[24] => resetlatch.OUTPUTSELECT
jdo[25] => always1.IN0
jdo[26] => ~NO_FANOUT~
jdo[27] => ~NO_FANOUT~
jdo[28] => ~NO_FANOUT~
jdo[29] => ~NO_FANOUT~
jdo[30] => ~NO_FANOUT~
jdo[31] => ~NO_FANOUT~
jdo[32] => ~NO_FANOUT~
jdo[33] => ~NO_FANOUT~
jdo[34] => ~NO_FANOUT~
jdo[35] => ~NO_FANOUT~
jdo[36] => ~NO_FANOUT~
jdo[37] => ~NO_FANOUT~
jrst_n => monitor_go~reg0.ACLR
jrst_n => monitor_error~reg0.ACLR
jrst_n => monitor_ready~reg0.ACLR
jrst_n => jtag_break.ACLR
jrst_n => resetrequest~reg0.ACLR
jrst_n => probepresent.ACLR
jrst_n => resetlatch~reg0.ENA
ocireg_ers => always1.IN0
ocireg_mrs => always1.IN0
reset => jtag_break.OUTPUTSELECT
reset => resetlatch.OUTPUTSELECT
st_ready_test_idle => monitor_go.OUTPUTSELECT
take_action_ocimem_a => jtag_break.OUTPUTSELECT
take_action_ocimem_a => resetlatch.OUTPUTSELECT
take_action_ocimem_a => always1.IN1
take_action_ocimem_a => always1.IN1
take_action_ocimem_a => probepresent.ENA
take_action_ocimem_a => resetrequest~reg0.ENA
take_action_ocireg => always1.IN1
take_action_ocireg => always1.IN1
xbrk_break => oci_hbreak_req.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
address[8] => comb.IN1
begintransfer => avalon.IN0
byteenable[0] => byteenable[0].IN1
byteenable[1] => byteenable[1].IN1
byteenable[2] => byteenable[2].IN1
byteenable[3] => byteenable[3].IN1
chipselect => comb.IN0
clk => clk.IN2
debugaccess => comb.IN1
jdo[0] => ~NO_FANOUT~
jdo[1] => ~NO_FANOUT~
jdo[2] => ~NO_FANOUT~
jdo[3] => MonDReg.DATAB
jdo[4] => MonDReg.DATAB
jdo[5] => MonDReg.DATAB
jdo[6] => MonDReg.DATAB
jdo[7] => MonDReg.DATAB
jdo[8] => MonDReg.DATAB
jdo[9] => MonDReg.DATAB
jdo[10] => MonDReg.DATAB
jdo[11] => MonDReg.DATAB
jdo[12] => MonDReg.DATAB
jdo[13] => MonDReg.DATAB
jdo[14] => MonDReg.DATAB
jdo[15] => MonDReg.DATAB
jdo[16] => MonDReg.DATAB
jdo[17] => MonDReg.DATAB
jdo[17] => MonAReg.DATAB
jdo[18] => MonDReg.DATAB
jdo[19] => MonDReg.DATAB
jdo[20] => MonDReg.DATAB
jdo[21] => MonDReg.DATAB
jdo[22] => MonDReg.DATAB
jdo[23] => MonDReg.DATAB
jdo[24] => MonDReg.DATAB
jdo[25] => MonDReg.DATAB
jdo[26] => MonDReg.DATAB
jdo[26] => MonAReg.DATAB
jdo[27] => MonDReg.DATAB
jdo[27] => MonAReg.DATAB
jdo[28] => MonDReg.DATAB
jdo[28] => MonAReg.DATAB
jdo[29] => MonDReg.DATAB
jdo[29] => MonAReg.DATAB
jdo[30] => MonDReg.DATAB
jdo[30] => MonAReg.DATAB
jdo[31] => MonDReg.DATAB
jdo[31] => MonAReg.DATAB
jdo[32] => MonDReg.DATAB
jdo[32] => MonAReg.DATAB
jdo[33] => MonDReg.DATAB
jdo[33] => MonAReg.DATAB
jdo[34] => MonDReg.DATAB
jdo[35] => ~NO_FANOUT~
jdo[36] => ~NO_FANOUT~
jdo[37] => ~NO_FANOUT~
jrst_n => MonDReg[0]~reg0.ACLR
jrst_n => MonDReg[1]~reg0.ACLR
jrst_n => MonDReg[2]~reg0.ACLR
jrst_n => MonDReg[3]~reg0.ACLR
jrst_n => MonDReg[4]~reg0.ACLR
jrst_n => MonDReg[5]~reg0.ACLR
jrst_n => MonDReg[6]~reg0.ACLR
jrst_n => MonDReg[7]~reg0.ACLR
jrst_n => MonDReg[8]~reg0.ACLR
jrst_n => MonDReg[9]~reg0.ACLR
jrst_n => MonDReg[10]~reg0.ACLR
jrst_n => MonDReg[11]~reg0.ACLR
jrst_n => MonDReg[12]~reg0.ACLR
jrst_n => MonDReg[13]~reg0.ACLR
jrst_n => MonDReg[14]~reg0.ACLR
jrst_n => MonDReg[15]~reg0.ACLR
jrst_n => MonDReg[16]~reg0.ACLR
jrst_n => MonDReg[17]~reg0.ACLR
jrst_n => MonDReg[18]~reg0.ACLR
jrst_n => MonDReg[19]~reg0.ACLR
jrst_n => MonDReg[20]~reg0.ACLR
jrst_n => MonDReg[21]~reg0.ACLR
jrst_n => MonDReg[22]~reg0.ACLR
jrst_n => MonDReg[23]~reg0.ACLR
jrst_n => MonDReg[24]~reg0.ACLR
jrst_n => MonDReg[25]~reg0.ACLR
jrst_n => MonDReg[26]~reg0.ACLR
jrst_n => MonDReg[27]~reg0.ACLR
jrst_n => MonDReg[28]~reg0.ACLR
jrst_n => MonDReg[29]~reg0.ACLR
jrst_n => MonDReg[30]~reg0.ACLR
jrst_n => MonDReg[31]~reg0.ACLR
jrst_n => MonAReg[2].ACLR
jrst_n => MonAReg[3].ACLR
jrst_n => MonAReg[4].ACLR
jrst_n => MonAReg[5].ACLR
jrst_n => MonAReg[6].ACLR
jrst_n => MonAReg[7].ACLR
jrst_n => MonAReg[8].ACLR
jrst_n => MonAReg[9].ACLR
jrst_n => MonAReg[10].ACLR
jrst_n => MonRd1.ACLR
jrst_n => MonRd.ACLR
jrst_n => MonWr.ACLR
resetrequest => avalon.IN1
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonAReg.OUTPUTSELECT
take_action_ocimem_a => MonRd.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonDReg.OUTPUTSELECT
take_action_ocimem_a => MonWr.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonAReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonDReg.OUTPUTSELECT
take_action_ocimem_b => MonWr.OUTPUTSELECT
take_action_ocimem_b => MonRd.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonAReg.OUTPUTSELECT
take_no_action_ocimem_a => MonRd.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonDReg.OUTPUTSELECT
take_no_action_ocimem_a => MonWr.OUTPUTSELECT
write => comb.IN1
writedata[0] => writedata[0].IN1
writedata[1] => writedata[1].IN1
writedata[2] => writedata[2].IN1
writedata[3] => writedata[3].IN1
writedata[4] => writedata[4].IN1
writedata[5] => writedata[5].IN1
writedata[6] => writedata[6].IN1
writedata[7] => writedata[7].IN1
writedata[8] => writedata[8].IN1
writedata[9] => writedata[9].IN1
writedata[10] => writedata[10].IN1
writedata[11] => writedata[11].IN1
writedata[12] => writedata[12].IN1
writedata[13] => writedata[13].IN1
writedata[14] => writedata[14].IN1
writedata[15] => writedata[15].IN1
writedata[16] => writedata[16].IN1
writedata[17] => writedata[17].IN1
writedata[18] => writedata[18].IN1
writedata[19] => writedata[19].IN1
writedata[20] => writedata[20].IN1
writedata[21] => writedata[21].IN1
writedata[22] => writedata[22].IN1
writedata[23] => writedata[23].IN1
writedata[24] => writedata[24].IN1
writedata[25] => writedata[25].IN1
writedata[26] => writedata[26].IN1
writedata[27] => writedata[27].IN1
writedata[28] => writedata[28].IN1
writedata[29] => writedata[29].IN1
writedata[30] => writedata[30].IN1
writedata[31] => writedata[31].IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
address_a[0] => address_a[0].IN1
address_a[1] => address_a[1].IN1
address_a[2] => address_a[2].IN1
address_a[3] => address_a[3].IN1
address_a[4] => address_a[4].IN1
address_a[5] => address_a[5].IN1
address_a[6] => address_a[6].IN1
address_a[7] => address_a[7].IN1
address_b[0] => address_b[0].IN1
address_b[1] => address_b[1].IN1
address_b[2] => address_b[2].IN1
address_b[3] => address_b[3].IN1
address_b[4] => address_b[4].IN1
address_b[5] => address_b[5].IN1
address_b[6] => address_b[6].IN1
address_b[7] => address_b[7].IN1
byteena_a[0] => byteena_a[0].IN1
byteena_a[1] => byteena_a[1].IN1
byteena_a[2] => byteena_a[2].IN1
byteena_a[3] => byteena_a[3].IN1
clock0 => clock0.IN1
clock1 => clock1.IN1
clocken0 => clocken0.IN1
clocken1 => clocken1.IN1
data_a[0] => data_a[0].IN1
data_a[1] => data_a[1].IN1
data_a[2] => data_a[2].IN1
data_a[3] => data_a[3].IN1
data_a[4] => data_a[4].IN1
data_a[5] => data_a[5].IN1
data_a[6] => data_a[6].IN1
data_a[7] => data_a[7].IN1
data_a[8] => data_a[8].IN1
data_a[9] => data_a[9].IN1
data_a[10] => data_a[10].IN1
data_a[11] => data_a[11].IN1
data_a[12] => data_a[12].IN1
data_a[13] => data_a[13].IN1
data_a[14] => data_a[14].IN1
data_a[15] => data_a[15].IN1
data_a[16] => data_a[16].IN1
data_a[17] => data_a[17].IN1
data_a[18] => data_a[18].IN1
data_a[19] => data_a[19].IN1
data_a[20] => data_a[20].IN1
data_a[21] => data_a[21].IN1
data_a[22] => data_a[22].IN1
data_a[23] => data_a[23].IN1
data_a[24] => data_a[24].IN1
data_a[25] => data_a[25].IN1
data_a[26] => data_a[26].IN1
data_a[27] => data_a[27].IN1
data_a[28] => data_a[28].IN1
data_a[29] => data_a[29].IN1
data_a[30] => data_a[30].IN1
data_a[31] => data_a[31].IN1
data_b[0] => data_b[0].IN1
data_b[1] => data_b[1].IN1
data_b[2] => data_b[2].IN1
data_b[3] => data_b[3].IN1
data_b[4] => data_b[4].IN1
data_b[5] => data_b[5].IN1
data_b[6] => data_b[6].IN1
data_b[7] => data_b[7].IN1
data_b[8] => data_b[8].IN1
data_b[9] => data_b[9].IN1
data_b[10] => data_b[10].IN1
data_b[11] => data_b[11].IN1
data_b[12] => data_b[12].IN1
data_b[13] => data_b[13].IN1
data_b[14] => data_b[14].IN1
data_b[15] => data_b[15].IN1
data_b[16] => data_b[16].IN1
data_b[17] => data_b[17].IN1
data_b[18] => data_b[18].IN1
data_b[19] => data_b[19].IN1
data_b[20] => data_b[20].IN1
data_b[21] => data_b[21].IN1
data_b[22] => data_b[22].IN1
data_b[23] => data_b[23].IN1
data_b[24] => data_b[24].IN1
data_b[25] => data_b[25].IN1
data_b[26] => data_b[26].IN1
data_b[27] => data_b[27].IN1
data_b[28] => data_b[28].IN1
data_b[29] => data_b[29].IN1
data_b[30] => data_b[30].IN1
data_b[31] => data_b[31].IN1
wren_a => wren_a.IN1
wren_b => wren_b.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
wren_a => altsyncram_f572:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => altsyncram_f572:auto_generated.wren_b
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_f572:auto_generated.data_a[0]
data_a[1] => altsyncram_f572:auto_generated.data_a[1]
data_a[2] => altsyncram_f572:auto_generated.data_a[2]
data_a[3] => altsyncram_f572:auto_generated.data_a[3]
data_a[4] => altsyncram_f572:auto_generated.data_a[4]
data_a[5] => altsyncram_f572:auto_generated.data_a[5]
data_a[6] => altsyncram_f572:auto_generated.data_a[6]
data_a[7] => altsyncram_f572:auto_generated.data_a[7]
data_a[8] => altsyncram_f572:auto_generated.data_a[8]
data_a[9] => altsyncram_f572:auto_generated.data_a[9]
data_a[10] => altsyncram_f572:auto_generated.data_a[10]
data_a[11] => altsyncram_f572:auto_generated.data_a[11]
data_a[12] => altsyncram_f572:auto_generated.data_a[12]
data_a[13] => altsyncram_f572:auto_generated.data_a[13]
data_a[14] => altsyncram_f572:auto_generated.data_a[14]
data_a[15] => altsyncram_f572:auto_generated.data_a[15]
data_a[16] => altsyncram_f572:auto_generated.data_a[16]
data_a[17] => altsyncram_f572:auto_generated.data_a[17]
data_a[18] => altsyncram_f572:auto_generated.data_a[18]
data_a[19] => altsyncram_f572:auto_generated.data_a[19]
data_a[20] => altsyncram_f572:auto_generated.data_a[20]
data_a[21] => altsyncram_f572:auto_generated.data_a[21]
data_a[22] => altsyncram_f572:auto_generated.data_a[22]
data_a[23] => altsyncram_f572:auto_generated.data_a[23]
data_a[24] => altsyncram_f572:auto_generated.data_a[24]
data_a[25] => altsyncram_f572:auto_generated.data_a[25]
data_a[26] => altsyncram_f572:auto_generated.data_a[26]
data_a[27] => altsyncram_f572:auto_generated.data_a[27]
data_a[28] => altsyncram_f572:auto_generated.data_a[28]
data_a[29] => altsyncram_f572:auto_generated.data_a[29]
data_a[30] => altsyncram_f572:auto_generated.data_a[30]
data_a[31] => altsyncram_f572:auto_generated.data_a[31]
data_b[0] => altsyncram_f572:auto_generated.data_b[0]
data_b[1] => altsyncram_f572:auto_generated.data_b[1]
data_b[2] => altsyncram_f572:auto_generated.data_b[2]
data_b[3] => altsyncram_f572:auto_generated.data_b[3]
data_b[4] => altsyncram_f572:auto_generated.data_b[4]
data_b[5] => altsyncram_f572:auto_generated.data_b[5]
data_b[6] => altsyncram_f572:auto_generated.data_b[6]
data_b[7] => altsyncram_f572:auto_generated.data_b[7]
data_b[8] => altsyncram_f572:auto_generated.data_b[8]
data_b[9] => altsyncram_f572:auto_generated.data_b[9]
data_b[10] => altsyncram_f572:auto_generated.data_b[10]
data_b[11] => altsyncram_f572:auto_generated.data_b[11]
data_b[12] => altsyncram_f572:auto_generated.data_b[12]
data_b[13] => altsyncram_f572:auto_generated.data_b[13]
data_b[14] => altsyncram_f572:auto_generated.data_b[14]
data_b[15] => altsyncram_f572:auto_generated.data_b[15]
data_b[16] => altsyncram_f572:auto_generated.data_b[16]
data_b[17] => altsyncram_f572:auto_generated.data_b[17]
data_b[18] => altsyncram_f572:auto_generated.data_b[18]
data_b[19] => altsyncram_f572:auto_generated.data_b[19]
data_b[20] => altsyncram_f572:auto_generated.data_b[20]
data_b[21] => altsyncram_f572:auto_generated.data_b[21]
data_b[22] => altsyncram_f572:auto_generated.data_b[22]
data_b[23] => altsyncram_f572:auto_generated.data_b[23]
data_b[24] => altsyncram_f572:auto_generated.data_b[24]
data_b[25] => altsyncram_f572:auto_generated.data_b[25]
data_b[26] => altsyncram_f572:auto_generated.data_b[26]
data_b[27] => altsyncram_f572:auto_generated.data_b[27]
data_b[28] => altsyncram_f572:auto_generated.data_b[28]
data_b[29] => altsyncram_f572:auto_generated.data_b[29]
data_b[30] => altsyncram_f572:auto_generated.data_b[30]
data_b[31] => altsyncram_f572:auto_generated.data_b[31]
address_a[0] => altsyncram_f572:auto_generated.address_a[0]
address_a[1] => altsyncram_f572:auto_generated.address_a[1]
address_a[2] => altsyncram_f572:auto_generated.address_a[2]
address_a[3] => altsyncram_f572:auto_generated.address_a[3]
address_a[4] => altsyncram_f572:auto_generated.address_a[4]
address_a[5] => altsyncram_f572:auto_generated.address_a[5]
address_a[6] => altsyncram_f572:auto_generated.address_a[6]
address_a[7] => altsyncram_f572:auto_generated.address_a[7]
address_b[0] => altsyncram_f572:auto_generated.address_b[0]
address_b[1] => altsyncram_f572:auto_generated.address_b[1]
address_b[2] => altsyncram_f572:auto_generated.address_b[2]
address_b[3] => altsyncram_f572:auto_generated.address_b[3]
address_b[4] => altsyncram_f572:auto_generated.address_b[4]
address_b[5] => altsyncram_f572:auto_generated.address_b[5]
address_b[6] => altsyncram_f572:auto_generated.address_b[6]
address_b[7] => altsyncram_f572:auto_generated.address_b[7]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_f572:auto_generated.clock0
clock1 => altsyncram_f572:auto_generated.clock1
clocken0 => altsyncram_f572:auto_generated.clocken0
clocken1 => altsyncram_f572:auto_generated.clocken1
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => altsyncram_f572:auto_generated.byteena_a[0]
byteena_a[1] => altsyncram_f572:auto_generated.byteena_a[1]
byteena_a[2] => altsyncram_f572:auto_generated.byteena_a[2]
byteena_a[3] => altsyncram_f572:auto_generated.byteena_a[3]
byteena_b[0] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_f572:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[0] => ram_block1a23.PORTBADDR
address_b[0] => ram_block1a24.PORTBADDR
address_b[0] => ram_block1a25.PORTBADDR
address_b[0] => ram_block1a26.PORTBADDR
address_b[0] => ram_block1a27.PORTBADDR
address_b[0] => ram_block1a28.PORTBADDR
address_b[0] => ram_block1a29.PORTBADDR
address_b[0] => ram_block1a30.PORTBADDR
address_b[0] => ram_block1a31.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[1] => ram_block1a23.PORTBADDR1
address_b[1] => ram_block1a24.PORTBADDR1
address_b[1] => ram_block1a25.PORTBADDR1
address_b[1] => ram_block1a26.PORTBADDR1
address_b[1] => ram_block1a27.PORTBADDR1
address_b[1] => ram_block1a28.PORTBADDR1
address_b[1] => ram_block1a29.PORTBADDR1
address_b[1] => ram_block1a30.PORTBADDR1
address_b[1] => ram_block1a31.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[2] => ram_block1a23.PORTBADDR2
address_b[2] => ram_block1a24.PORTBADDR2
address_b[2] => ram_block1a25.PORTBADDR2
address_b[2] => ram_block1a26.PORTBADDR2
address_b[2] => ram_block1a27.PORTBADDR2
address_b[2] => ram_block1a28.PORTBADDR2
address_b[2] => ram_block1a29.PORTBADDR2
address_b[2] => ram_block1a30.PORTBADDR2
address_b[2] => ram_block1a31.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[3] => ram_block1a23.PORTBADDR3
address_b[3] => ram_block1a24.PORTBADDR3
address_b[3] => ram_block1a25.PORTBADDR3
address_b[3] => ram_block1a26.PORTBADDR3
address_b[3] => ram_block1a27.PORTBADDR3
address_b[3] => ram_block1a28.PORTBADDR3
address_b[3] => ram_block1a29.PORTBADDR3
address_b[3] => ram_block1a30.PORTBADDR3
address_b[3] => ram_block1a31.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[4] => ram_block1a24.PORTBADDR4
address_b[4] => ram_block1a25.PORTBADDR4
address_b[4] => ram_block1a26.PORTBADDR4
address_b[4] => ram_block1a27.PORTBADDR4
address_b[4] => ram_block1a28.PORTBADDR4
address_b[4] => ram_block1a29.PORTBADDR4
address_b[4] => ram_block1a30.PORTBADDR4
address_b[4] => ram_block1a31.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[5] => ram_block1a16.PORTBADDR5
address_b[5] => ram_block1a17.PORTBADDR5
address_b[5] => ram_block1a18.PORTBADDR5
address_b[5] => ram_block1a19.PORTBADDR5
address_b[5] => ram_block1a20.PORTBADDR5
address_b[5] => ram_block1a21.PORTBADDR5
address_b[5] => ram_block1a22.PORTBADDR5
address_b[5] => ram_block1a23.PORTBADDR5
address_b[5] => ram_block1a24.PORTBADDR5
address_b[5] => ram_block1a25.PORTBADDR5
address_b[5] => ram_block1a26.PORTBADDR5
address_b[5] => ram_block1a27.PORTBADDR5
address_b[5] => ram_block1a28.PORTBADDR5
address_b[5] => ram_block1a29.PORTBADDR5
address_b[5] => ram_block1a30.PORTBADDR5
address_b[5] => ram_block1a31.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[6] => ram_block1a16.PORTBADDR6
address_b[6] => ram_block1a17.PORTBADDR6
address_b[6] => ram_block1a18.PORTBADDR6
address_b[6] => ram_block1a19.PORTBADDR6
address_b[6] => ram_block1a20.PORTBADDR6
address_b[6] => ram_block1a21.PORTBADDR6
address_b[6] => ram_block1a22.PORTBADDR6
address_b[6] => ram_block1a23.PORTBADDR6
address_b[6] => ram_block1a24.PORTBADDR6
address_b[6] => ram_block1a25.PORTBADDR6
address_b[6] => ram_block1a26.PORTBADDR6
address_b[6] => ram_block1a27.PORTBADDR6
address_b[6] => ram_block1a28.PORTBADDR6
address_b[6] => ram_block1a29.PORTBADDR6
address_b[6] => ram_block1a30.PORTBADDR6
address_b[6] => ram_block1a31.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[7] => ram_block1a16.PORTBADDR7
address_b[7] => ram_block1a17.PORTBADDR7
address_b[7] => ram_block1a18.PORTBADDR7
address_b[7] => ram_block1a19.PORTBADDR7
address_b[7] => ram_block1a20.PORTBADDR7
address_b[7] => ram_block1a21.PORTBADDR7
address_b[7] => ram_block1a22.PORTBADDR7
address_b[7] => ram_block1a23.PORTBADDR7
address_b[7] => ram_block1a24.PORTBADDR7
address_b[7] => ram_block1a25.PORTBADDR7
address_b[7] => ram_block1a26.PORTBADDR7
address_b[7] => ram_block1a27.PORTBADDR7
address_b[7] => ram_block1a28.PORTBADDR7
address_b[7] => ram_block1a29.PORTBADDR7
address_b[7] => ram_block1a30.PORTBADDR7
address_b[7] => ram_block1a31.PORTBADDR7
byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS
byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS
byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS
byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS
byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS
byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS
byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS
byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS
byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS
byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS
byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS
byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS
byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS
byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS
byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS
byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS
byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS
byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS
byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS
byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS
byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS
byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS
byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS
byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS
byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS
byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS
byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS
byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS
byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS
byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS
byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS
byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
clock1 => ram_block1a16.CLK1
clock1 => ram_block1a17.CLK1
clock1 => ram_block1a18.CLK1
clock1 => ram_block1a19.CLK1
clock1 => ram_block1a20.CLK1
clock1 => ram_block1a21.CLK1
clock1 => ram_block1a22.CLK1
clock1 => ram_block1a23.CLK1
clock1 => ram_block1a24.CLK1
clock1 => ram_block1a25.CLK1
clock1 => ram_block1a26.CLK1
clock1 => ram_block1a27.CLK1
clock1 => ram_block1a28.CLK1
clock1 => ram_block1a29.CLK1
clock1 => ram_block1a30.CLK1
clock1 => ram_block1a31.CLK1
clocken0 => ram_block1a0.ENA0
clocken0 => ram_block1a1.ENA0
clocken0 => ram_block1a2.ENA0
clocken0 => ram_block1a3.ENA0
clocken0 => ram_block1a4.ENA0
clocken0 => ram_block1a5.ENA0
clocken0 => ram_block1a6.ENA0
clocken0 => ram_block1a7.ENA0
clocken0 => ram_block1a8.ENA0
clocken0 => ram_block1a9.ENA0
clocken0 => ram_block1a10.ENA0
clocken0 => ram_block1a11.ENA0
clocken0 => ram_block1a12.ENA0
clocken0 => ram_block1a13.ENA0
clocken0 => ram_block1a14.ENA0
clocken0 => ram_block1a15.ENA0
clocken0 => ram_block1a16.ENA0
clocken0 => ram_block1a17.ENA0
clocken0 => ram_block1a18.ENA0
clocken0 => ram_block1a19.ENA0
clocken0 => ram_block1a20.ENA0
clocken0 => ram_block1a21.ENA0
clocken0 => ram_block1a22.ENA0
clocken0 => ram_block1a23.ENA0
clocken0 => ram_block1a24.ENA0
clocken0 => ram_block1a25.ENA0
clocken0 => ram_block1a26.ENA0
clocken0 => ram_block1a27.ENA0
clocken0 => ram_block1a28.ENA0
clocken0 => ram_block1a29.ENA0
clocken0 => ram_block1a30.ENA0
clocken0 => ram_block1a31.ENA0
clocken1 => ram_block1a0.ENA1
clocken1 => ram_block1a1.ENA1
clocken1 => ram_block1a2.ENA1
clocken1 => ram_block1a3.ENA1
clocken1 => ram_block1a4.ENA1
clocken1 => ram_block1a5.ENA1
clocken1 => ram_block1a6.ENA1
clocken1 => ram_block1a7.ENA1
clocken1 => ram_block1a8.ENA1
clocken1 => ram_block1a9.ENA1
clocken1 => ram_block1a10.ENA1
clocken1 => ram_block1a11.ENA1
clocken1 => ram_block1a12.ENA1
clocken1 => ram_block1a13.ENA1
clocken1 => ram_block1a14.ENA1
clocken1 => ram_block1a15.ENA1
clocken1 => ram_block1a16.ENA1
clocken1 => ram_block1a17.ENA1
clocken1 => ram_block1a18.ENA1
clocken1 => ram_block1a19.ENA1
clocken1 => ram_block1a20.ENA1
clocken1 => ram_block1a21.ENA1
clocken1 => ram_block1a22.ENA1
clocken1 => ram_block1a23.ENA1
clocken1 => ram_block1a24.ENA1
clocken1 => ram_block1a25.ENA1
clocken1 => ram_block1a26.ENA1
clocken1 => ram_block1a27.ENA1
clocken1 => ram_block1a28.ENA1
clocken1 => ram_block1a29.ENA1
clocken1 => ram_block1a30.ENA1
clocken1 => ram_block1a31.ENA1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
data_a[24] => ram_block1a24.PORTADATAIN
data_a[25] => ram_block1a25.PORTADATAIN
data_a[26] => ram_block1a26.PORTADATAIN
data_a[27] => ram_block1a27.PORTADATAIN
data_a[28] => ram_block1a28.PORTADATAIN
data_a[29] => ram_block1a29.PORTADATAIN
data_a[30] => ram_block1a30.PORTADATAIN
data_a[31] => ram_block1a31.PORTADATAIN
data_b[0] => ram_block1a0.PORTBDATAIN
data_b[1] => ram_block1a1.PORTBDATAIN
data_b[2] => ram_block1a2.PORTBDATAIN
data_b[3] => ram_block1a3.PORTBDATAIN
data_b[4] => ram_block1a4.PORTBDATAIN
data_b[5] => ram_block1a5.PORTBDATAIN
data_b[6] => ram_block1a6.PORTBDATAIN
data_b[7] => ram_block1a7.PORTBDATAIN
data_b[8] => ram_block1a8.PORTBDATAIN
data_b[9] => ram_block1a9.PORTBDATAIN
data_b[10] => ram_block1a10.PORTBDATAIN
data_b[11] => ram_block1a11.PORTBDATAIN
data_b[12] => ram_block1a12.PORTBDATAIN
data_b[13] => ram_block1a13.PORTBDATAIN
data_b[14] => ram_block1a14.PORTBDATAIN
data_b[15] => ram_block1a15.PORTBDATAIN
data_b[16] => ram_block1a16.PORTBDATAIN
data_b[17] => ram_block1a17.PORTBDATAIN
data_b[18] => ram_block1a18.PORTBDATAIN
data_b[19] => ram_block1a19.PORTBDATAIN
data_b[20] => ram_block1a20.PORTBDATAIN
data_b[21] => ram_block1a21.PORTBDATAIN
data_b[22] => ram_block1a22.PORTBDATAIN
data_b[23] => ram_block1a23.PORTBDATAIN
data_b[24] => ram_block1a24.PORTBDATAIN
data_b[25] => ram_block1a25.PORTBDATAIN
data_b[26] => ram_block1a26.PORTBDATAIN
data_b[27] => ram_block1a27.PORTBDATAIN
data_b[28] => ram_block1a28.PORTBDATAIN
data_b[29] => ram_block1a29.PORTBDATAIN
data_b[30] => ram_block1a30.PORTBDATAIN
data_b[31] => ram_block1a31.PORTBDATAIN
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a23.PORTAWE
wren_a => ram_block1a24.PORTAWE
wren_a => ram_block1a25.PORTAWE
wren_a => ram_block1a26.PORTAWE
wren_a => ram_block1a27.PORTAWE
wren_a => ram_block1a28.PORTAWE
wren_a => ram_block1a29.PORTAWE
wren_a => ram_block1a30.PORTAWE
wren_a => ram_block1a31.PORTAWE
wren_b => ram_block1a0.PORTBWE
wren_b => ram_block1a1.PORTBWE
wren_b => ram_block1a2.PORTBWE
wren_b => ram_block1a3.PORTBWE
wren_b => ram_block1a4.PORTBWE
wren_b => ram_block1a5.PORTBWE
wren_b => ram_block1a6.PORTBWE
wren_b => ram_block1a7.PORTBWE
wren_b => ram_block1a8.PORTBWE
wren_b => ram_block1a9.PORTBWE
wren_b => ram_block1a10.PORTBWE
wren_b => ram_block1a11.PORTBWE
wren_b => ram_block1a12.PORTBWE
wren_b => ram_block1a13.PORTBWE
wren_b => ram_block1a14.PORTBWE
wren_b => ram_block1a15.PORTBWE
wren_b => ram_block1a16.PORTBWE
wren_b => ram_block1a17.PORTBWE
wren_b => ram_block1a18.PORTBWE
wren_b => ram_block1a19.PORTBWE
wren_b => ram_block1a20.PORTBWE
wren_b => ram_block1a21.PORTBWE
wren_b => ram_block1a22.PORTBWE
wren_b => ram_block1a23.PORTBWE
wren_b => ram_block1a24.PORTBWE
wren_b => ram_block1a25.PORTBWE
wren_b => ram_block1a26.PORTBWE
wren_b => ram_block1a27.PORTBWE
wren_b => ram_block1a28.PORTBWE
wren_b => ram_block1a29.PORTBWE
wren_b => ram_block1a30.PORTBWE
wren_b => ram_block1a31.PORTBWE


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg
address[0] => Equal0.IN8
address[0] => Equal1.IN1
address[1] => Equal0.IN7
address[1] => Equal1.IN8
address[2] => Equal0.IN6
address[2] => Equal1.IN7
address[3] => Equal0.IN5
address[3] => Equal1.IN6
address[4] => Equal0.IN4
address[4] => Equal1.IN5
address[5] => Equal0.IN3
address[5] => Equal1.IN4
address[6] => Equal0.IN2
address[6] => Equal1.IN3
address[7] => Equal0.IN1
address[7] => Equal1.IN2
address[8] => Equal0.IN0
address[8] => Equal1.IN0
chipselect => write_strobe.IN0
clk => oci_ienable[0]~reg0.CLK
clk => oci_ienable[1]~reg0.CLK
clk => oci_ienable[2]~reg0.CLK
clk => oci_ienable[3]~reg0.CLK
clk => oci_ienable[4]~reg0.CLK
clk => oci_ienable[5]~reg0.CLK
clk => oci_ienable[6]~reg0.CLK
clk => oci_ienable[7]~reg0.CLK
clk => oci_ienable[8]~reg0.CLK
clk => oci_ienable[9]~reg0.CLK
clk => oci_ienable[10]~reg0.CLK
clk => oci_ienable[11]~reg0.CLK
clk => oci_ienable[12]~reg0.CLK
clk => oci_ienable[13]~reg0.CLK
clk => oci_ienable[14]~reg0.CLK
clk => oci_ienable[15]~reg0.CLK
clk => oci_ienable[16]~reg0.CLK
clk => oci_ienable[17]~reg0.CLK
clk => oci_ienable[18]~reg0.CLK
clk => oci_ienable[19]~reg0.CLK
clk => oci_ienable[20]~reg0.CLK
clk => oci_ienable[21]~reg0.CLK
clk => oci_ienable[22]~reg0.CLK
clk => oci_ienable[23]~reg0.CLK
clk => oci_ienable[24]~reg0.CLK
clk => oci_ienable[25]~reg0.CLK
clk => oci_ienable[26]~reg0.CLK
clk => oci_ienable[27]~reg0.CLK
clk => oci_ienable[28]~reg0.CLK
clk => oci_ienable[29]~reg0.CLK
clk => oci_ienable[30]~reg0.CLK
clk => oci_ienable[31]~reg0.CLK
clk => oci_single_step_mode~reg0.CLK
debugaccess => write_strobe.IN1
monitor_error => oci_reg_readdata.DATAB
monitor_go => oci_reg_readdata.DATAB
monitor_ready => oci_reg_readdata.DATAB
reset_n => oci_ienable[0]~reg0.PRESET
reset_n => oci_ienable[1]~reg0.PRESET
reset_n => oci_ienable[2]~reg0.PRESET
reset_n => oci_ienable[3]~reg0.ACLR
reset_n => oci_ienable[4]~reg0.ACLR
reset_n => oci_ienable[5]~reg0.ACLR
reset_n => oci_ienable[6]~reg0.ACLR
reset_n => oci_ienable[7]~reg0.ACLR
reset_n => oci_ienable[8]~reg0.ACLR
reset_n => oci_ienable[9]~reg0.ACLR
reset_n => oci_ienable[10]~reg0.ACLR
reset_n => oci_ienable[11]~reg0.ACLR
reset_n => oci_ienable[12]~reg0.ACLR
reset_n => oci_ienable[13]~reg0.ACLR
reset_n => oci_ienable[14]~reg0.ACLR
reset_n => oci_ienable[15]~reg0.ACLR
reset_n => oci_ienable[16]~reg0.ACLR
reset_n => oci_ienable[17]~reg0.ACLR
reset_n => oci_ienable[18]~reg0.ACLR
reset_n => oci_ienable[19]~reg0.ACLR
reset_n => oci_ienable[20]~reg0.ACLR
reset_n => oci_ienable[21]~reg0.ACLR
reset_n => oci_ienable[22]~reg0.ACLR
reset_n => oci_ienable[23]~reg0.ACLR
reset_n => oci_ienable[24]~reg0.ACLR
reset_n => oci_ienable[25]~reg0.ACLR
reset_n => oci_ienable[26]~reg0.ACLR
reset_n => oci_ienable[27]~reg0.ACLR
reset_n => oci_ienable[28]~reg0.ACLR
reset_n => oci_ienable[29]~reg0.ACLR
reset_n => oci_ienable[30]~reg0.ACLR
reset_n => oci_ienable[31]~reg0.ACLR
reset_n => oci_single_step_mode~reg0.ACLR
write => write_strobe.IN1
writedata[0] => ocireg_mrs.DATAIN
writedata[0] => oci_ienable[0]~reg0.DATAIN
writedata[1] => ocireg_ers.DATAIN
writedata[1] => oci_ienable[1]~reg0.DATAIN
writedata[2] => oci_ienable[2]~reg0.DATAIN
writedata[3] => oci_single_step_mode~reg0.DATAIN
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break
clk => trigger_state.CLK
clk => break_readreg[0]~reg0.CLK
clk => break_readreg[1]~reg0.CLK
clk => break_readreg[2]~reg0.CLK
clk => break_readreg[3]~reg0.CLK
clk => break_readreg[4]~reg0.CLK
clk => break_readreg[5]~reg0.CLK
clk => break_readreg[6]~reg0.CLK
clk => break_readreg[7]~reg0.CLK
clk => break_readreg[8]~reg0.CLK
clk => break_readreg[9]~reg0.CLK
clk => break_readreg[10]~reg0.CLK
clk => break_readreg[11]~reg0.CLK
clk => break_readreg[12]~reg0.CLK
clk => break_readreg[13]~reg0.CLK
clk => break_readreg[14]~reg0.CLK
clk => break_readreg[15]~reg0.CLK
clk => break_readreg[16]~reg0.CLK
clk => break_readreg[17]~reg0.CLK
clk => break_readreg[18]~reg0.CLK
clk => break_readreg[19]~reg0.CLK
clk => break_readreg[20]~reg0.CLK
clk => break_readreg[21]~reg0.CLK
clk => break_readreg[22]~reg0.CLK
clk => break_readreg[23]~reg0.CLK
clk => break_readreg[24]~reg0.CLK
clk => break_readreg[25]~reg0.CLK
clk => break_readreg[26]~reg0.CLK
clk => break_readreg[27]~reg0.CLK
clk => break_readreg[28]~reg0.CLK
clk => break_readreg[29]~reg0.CLK
clk => break_readreg[30]~reg0.CLK
clk => break_readreg[31]~reg0.CLK
clk => trigbrktype~reg0.CLK
dbrk_break => trigbrktype.OUTPUTSELECT
dbrk_goto0 => always2.IN0
dbrk_goto1 => always2.IN0
jdo[0] => break_readreg.DATAB
jdo[0] => break_readreg.DATAB
jdo[0] => break_readreg.DATAB
jdo[1] => break_readreg.DATAB
jdo[1] => break_readreg.DATAB
jdo[1] => break_readreg.DATAB
jdo[2] => break_readreg.DATAB
jdo[2] => break_readreg.DATAB
jdo[2] => break_readreg.DATAB
jdo[3] => break_readreg.DATAB
jdo[3] => break_readreg.DATAB
jdo[3] => break_readreg.DATAB
jdo[4] => break_readreg.DATAB
jdo[4] => break_readreg.DATAB
jdo[4] => break_readreg.DATAB
jdo[5] => break_readreg.DATAB
jdo[5] => break_readreg.DATAB
jdo[5] => break_readreg.DATAB
jdo[6] => break_readreg.DATAB
jdo[6] => break_readreg.DATAB
jdo[6] => break_readreg.DATAB
jdo[7] => break_readreg.DATAB
jdo[7] => break_readreg.DATAB
jdo[7] => break_readreg.DATAB
jdo[8] => break_readreg.DATAB
jdo[8] => break_readreg.DATAB
jdo[8] => break_readreg.DATAB
jdo[9] => break_readreg.DATAB
jdo[9] => break_readreg.DATAB
jdo[9] => break_readreg.DATAB
jdo[10] => break_readreg.DATAB
jdo[10] => break_readreg.DATAB
jdo[10] => break_readreg.DATAB
jdo[11] => break_readreg.DATAB
jdo[11] => break_readreg.DATAB
jdo[11] => break_readreg.DATAB
jdo[12] => break_readreg.DATAB
jdo[12] => break_readreg.DATAB
jdo[12] => break_readreg.DATAB
jdo[13] => break_readreg.DATAB
jdo[13] => break_readreg.DATAB
jdo[13] => break_readreg.DATAB
jdo[14] => break_readreg.DATAB
jdo[14] => break_readreg.DATAB
jdo[14] => break_readreg.DATAB
jdo[15] => break_readreg.DATAB
jdo[15] => break_readreg.DATAB
jdo[15] => break_readreg.DATAB
jdo[16] => break_readreg.DATAB
jdo[16] => break_readreg.DATAB
jdo[16] => break_readreg.DATAB
jdo[17] => break_readreg.DATAB
jdo[17] => break_readreg.DATAB
jdo[17] => break_readreg.DATAB
jdo[18] => break_readreg.DATAB
jdo[18] => break_readreg.DATAB
jdo[18] => break_readreg.DATAB
jdo[19] => break_readreg.DATAB
jdo[19] => break_readreg.DATAB
jdo[19] => break_readreg.DATAB
jdo[20] => break_readreg.DATAB
jdo[20] => break_readreg.DATAB
jdo[20] => break_readreg.DATAB
jdo[21] => break_readreg.DATAB
jdo[21] => break_readreg.DATAB
jdo[21] => break_readreg.DATAB
jdo[22] => break_readreg.DATAB
jdo[22] => break_readreg.DATAB
jdo[22] => break_readreg.DATAB
jdo[23] => break_readreg.DATAB
jdo[23] => break_readreg.DATAB
jdo[23] => break_readreg.DATAB
jdo[24] => break_readreg.DATAB
jdo[24] => break_readreg.DATAB
jdo[24] => break_readreg.DATAB
jdo[25] => break_readreg.DATAB
jdo[25] => break_readreg.DATAB
jdo[25] => break_readreg.DATAB
jdo[26] => break_readreg.DATAB
jdo[26] => break_readreg.DATAB
jdo[26] => break_readreg.DATAB
jdo[27] => break_readreg.DATAB
jdo[27] => break_readreg.DATAB
jdo[27] => break_readreg.DATAB
jdo[28] => break_readreg.DATAB
jdo[28] => break_readreg.DATAB
jdo[28] => break_readreg.DATAB
jdo[29] => break_readreg.DATAB
jdo[29] => break_readreg.DATAB
jdo[29] => break_readreg.DATAB
jdo[30] => break_readreg.DATAB
jdo[30] => break_readreg.DATAB
jdo[30] => break_readreg.DATAB
jdo[31] => break_readreg.DATAB
jdo[31] => break_readreg.DATAB
jdo[31] => break_readreg.DATAB
jdo[32] => ~NO_FANOUT~
jdo[33] => ~NO_FANOUT~
jdo[34] => ~NO_FANOUT~
jdo[35] => ~NO_FANOUT~
jdo[36] => ~NO_FANOUT~
jdo[37] => ~NO_FANOUT~
jrst_n => break_readreg[0]~reg0.ACLR
jrst_n => break_readreg[1]~reg0.ACLR
jrst_n => break_readreg[2]~reg0.ACLR
jrst_n => break_readreg[3]~reg0.ACLR
jrst_n => break_readreg[4]~reg0.ACLR
jrst_n => break_readreg[5]~reg0.ACLR
jrst_n => break_readreg[6]~reg0.ACLR
jrst_n => break_readreg[7]~reg0.ACLR
jrst_n => break_readreg[8]~reg0.ACLR
jrst_n => break_readreg[9]~reg0.ACLR
jrst_n => break_readreg[10]~reg0.ACLR
jrst_n => break_readreg[11]~reg0.ACLR
jrst_n => break_readreg[12]~reg0.ACLR
jrst_n => break_readreg[13]~reg0.ACLR
jrst_n => break_readreg[14]~reg0.ACLR
jrst_n => break_readreg[15]~reg0.ACLR
jrst_n => break_readreg[16]~reg0.ACLR
jrst_n => break_readreg[17]~reg0.ACLR
jrst_n => break_readreg[18]~reg0.ACLR
jrst_n => break_readreg[19]~reg0.ACLR
jrst_n => break_readreg[20]~reg0.ACLR
jrst_n => break_readreg[21]~reg0.ACLR
jrst_n => break_readreg[22]~reg0.ACLR
jrst_n => break_readreg[23]~reg0.ACLR
jrst_n => break_readreg[24]~reg0.ACLR
jrst_n => break_readreg[25]~reg0.ACLR
jrst_n => break_readreg[26]~reg0.ACLR
jrst_n => break_readreg[27]~reg0.ACLR
jrst_n => break_readreg[28]~reg0.ACLR
jrst_n => break_readreg[29]~reg0.ACLR
jrst_n => break_readreg[30]~reg0.ACLR
jrst_n => break_readreg[31]~reg0.ACLR
jrst_n => trigbrktype~reg0.ACLR
reset_n => trigger_state.ACLR
take_action_break_a => take_action_any_break.IN0
take_action_break_b => take_action_any_break.IN1
take_action_break_c => take_action_any_break.IN1
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_a => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_b => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
take_no_action_break_c => break_readreg.OUTPUTSELECT
xbrk_goto0 => always2.IN1
xbrk_goto1 => always2.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk
D_en => ~NO_FANOUT~
E_en => xbrk_break~reg0.ENA
E_en => E_xbrk_traceon.ENA
E_en => E_xbrk_traceoff.ENA
E_en => E_xbrk_trigout.ENA
E_en => E_xbrk_goto0.ENA
E_en => E_xbrk_goto1.ENA
E_valid => M_xbrk_traceon.IN1
E_valid => M_xbrk_traceoff.IN1
E_valid => M_xbrk_trigout.IN1
E_valid => M_xbrk_goto0.IN1
E_valid => M_xbrk_goto1.IN1
F_pc[0] => ~NO_FANOUT~
F_pc[1] => ~NO_FANOUT~
F_pc[2] => ~NO_FANOUT~
F_pc[3] => ~NO_FANOUT~
F_pc[4] => ~NO_FANOUT~
F_pc[5] => ~NO_FANOUT~
F_pc[6] => ~NO_FANOUT~
F_pc[7] => ~NO_FANOUT~
F_pc[8] => ~NO_FANOUT~
F_pc[9] => ~NO_FANOUT~
F_pc[10] => ~NO_FANOUT~
F_pc[11] => ~NO_FANOUT~
F_pc[12] => ~NO_FANOUT~
F_pc[13] => ~NO_FANOUT~
F_pc[14] => ~NO_FANOUT~
F_pc[15] => ~NO_FANOUT~
F_pc[16] => ~NO_FANOUT~
F_pc[17] => ~NO_FANOUT~
F_pc[18] => ~NO_FANOUT~
F_pc[19] => ~NO_FANOUT~
F_pc[20] => ~NO_FANOUT~
F_pc[21] => ~NO_FANOUT~
F_pc[22] => ~NO_FANOUT~
F_pc[23] => ~NO_FANOUT~
F_pc[24] => ~NO_FANOUT~
M_en => M_xbrk_traceon.ENA
M_en => M_xbrk_traceoff.ENA
M_en => M_xbrk_trigout.ENA
M_en => M_xbrk_goto0.ENA
M_en => M_xbrk_goto1.ENA
clk => M_xbrk_goto1.CLK
clk => M_xbrk_goto0.CLK
clk => M_xbrk_trigout.CLK
clk => M_xbrk_traceoff.CLK
clk => M_xbrk_traceon.CLK
clk => E_xbrk_goto1.CLK
clk => E_xbrk_goto0.CLK
clk => E_xbrk_trigout.CLK
clk => E_xbrk_traceoff.CLK
clk => E_xbrk_traceon.CLK
clk => xbrk_break~reg0.CLK
reset_n => xbrk_break~reg0.ACLR
reset_n => M_xbrk_goto0.ACLR
reset_n => M_xbrk_goto1.ACLR
reset_n => M_xbrk_traceoff.ACLR
reset_n => M_xbrk_traceon.ACLR
reset_n => M_xbrk_trigout.ACLR
reset_n => E_xbrk_traceon.ACLR
reset_n => E_xbrk_traceoff.ACLR
reset_n => E_xbrk_trigout.ACLR
reset_n => E_xbrk_goto0.ACLR
reset_n => E_xbrk_goto1.ACLR
trigger_state_0 => ~NO_FANOUT~
trigger_state_1 => ~NO_FANOUT~
xbrk_ctrl0[0] => ~NO_FANOUT~
xbrk_ctrl0[1] => ~NO_FANOUT~
xbrk_ctrl0[2] => ~NO_FANOUT~
xbrk_ctrl0[3] => ~NO_FANOUT~
xbrk_ctrl0[4] => ~NO_FANOUT~
xbrk_ctrl0[5] => ~NO_FANOUT~
xbrk_ctrl0[6] => ~NO_FANOUT~
xbrk_ctrl0[7] => ~NO_FANOUT~
xbrk_ctrl1[0] => ~NO_FANOUT~
xbrk_ctrl1[1] => ~NO_FANOUT~
xbrk_ctrl1[2] => ~NO_FANOUT~
xbrk_ctrl1[3] => ~NO_FANOUT~
xbrk_ctrl1[4] => ~NO_FANOUT~
xbrk_ctrl1[5] => ~NO_FANOUT~
xbrk_ctrl1[6] => ~NO_FANOUT~
xbrk_ctrl1[7] => ~NO_FANOUT~
xbrk_ctrl2[0] => ~NO_FANOUT~
xbrk_ctrl2[1] => ~NO_FANOUT~
xbrk_ctrl2[2] => ~NO_FANOUT~
xbrk_ctrl2[3] => ~NO_FANOUT~
xbrk_ctrl2[4] => ~NO_FANOUT~
xbrk_ctrl2[5] => ~NO_FANOUT~
xbrk_ctrl2[6] => ~NO_FANOUT~
xbrk_ctrl2[7] => ~NO_FANOUT~
xbrk_ctrl3[0] => ~NO_FANOUT~
xbrk_ctrl3[1] => ~NO_FANOUT~
xbrk_ctrl3[2] => ~NO_FANOUT~
xbrk_ctrl3[3] => ~NO_FANOUT~
xbrk_ctrl3[4] => ~NO_FANOUT~
xbrk_ctrl3[5] => ~NO_FANOUT~
xbrk_ctrl3[6] => ~NO_FANOUT~
xbrk_ctrl3[7] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk
A_ctrl_ld => cpu_d_read.IN0
A_ctrl_st => cpu_d_write.IN0
A_en => cpu_d_wait.DATAIN
A_mem_baddr[0] => cpu_d_address[0].DATAIN
A_mem_baddr[1] => cpu_d_address[1].DATAIN
A_mem_baddr[2] => cpu_d_address[2].DATAIN
A_mem_baddr[3] => cpu_d_address[3].DATAIN
A_mem_baddr[4] => cpu_d_address[4].DATAIN
A_mem_baddr[5] => cpu_d_address[5].DATAIN
A_mem_baddr[6] => cpu_d_address[6].DATAIN
A_mem_baddr[7] => cpu_d_address[7].DATAIN
A_mem_baddr[8] => cpu_d_address[8].DATAIN
A_mem_baddr[9] => cpu_d_address[9].DATAIN
A_mem_baddr[10] => cpu_d_address[10].DATAIN
A_mem_baddr[11] => cpu_d_address[11].DATAIN
A_mem_baddr[12] => cpu_d_address[12].DATAIN
A_mem_baddr[13] => cpu_d_address[13].DATAIN
A_mem_baddr[14] => cpu_d_address[14].DATAIN
A_mem_baddr[15] => cpu_d_address[15].DATAIN
A_mem_baddr[16] => cpu_d_address[16].DATAIN
A_mem_baddr[17] => cpu_d_address[17].DATAIN
A_mem_baddr[18] => cpu_d_address[18].DATAIN
A_mem_baddr[19] => cpu_d_address[19].DATAIN
A_mem_baddr[20] => cpu_d_address[20].DATAIN
A_mem_baddr[21] => cpu_d_address[21].DATAIN
A_mem_baddr[22] => cpu_d_address[22].DATAIN
A_mem_baddr[23] => cpu_d_address[23].DATAIN
A_mem_baddr[24] => cpu_d_address[24].DATAIN
A_mem_baddr[25] => cpu_d_address[25].DATAIN
A_mem_baddr[26] => cpu_d_address[26].DATAIN
A_st_data[0] => cpu_d_writedata[0].DATAIN
A_st_data[1] => cpu_d_writedata[1].DATAIN
A_st_data[2] => cpu_d_writedata[2].DATAIN
A_st_data[3] => cpu_d_writedata[3].DATAIN
A_st_data[4] => cpu_d_writedata[4].DATAIN
A_st_data[5] => cpu_d_writedata[5].DATAIN
A_st_data[6] => cpu_d_writedata[6].DATAIN
A_st_data[7] => cpu_d_writedata[7].DATAIN
A_st_data[8] => cpu_d_writedata[8].DATAIN
A_st_data[9] => cpu_d_writedata[9].DATAIN
A_st_data[10] => cpu_d_writedata[10].DATAIN
A_st_data[11] => cpu_d_writedata[11].DATAIN
A_st_data[12] => cpu_d_writedata[12].DATAIN
A_st_data[13] => cpu_d_writedata[13].DATAIN
A_st_data[14] => cpu_d_writedata[14].DATAIN
A_st_data[15] => cpu_d_writedata[15].DATAIN
A_st_data[16] => cpu_d_writedata[16].DATAIN
A_st_data[17] => cpu_d_writedata[17].DATAIN
A_st_data[18] => cpu_d_writedata[18].DATAIN
A_st_data[19] => cpu_d_writedata[19].DATAIN
A_st_data[20] => cpu_d_writedata[20].DATAIN
A_st_data[21] => cpu_d_writedata[21].DATAIN
A_st_data[22] => cpu_d_writedata[22].DATAIN
A_st_data[23] => cpu_d_writedata[23].DATAIN
A_st_data[24] => cpu_d_writedata[24].DATAIN
A_st_data[25] => cpu_d_writedata[25].DATAIN
A_st_data[26] => cpu_d_writedata[26].DATAIN
A_st_data[27] => cpu_d_writedata[27].DATAIN
A_st_data[28] => cpu_d_writedata[28].DATAIN
A_st_data[29] => cpu_d_writedata[29].DATAIN
A_st_data[30] => cpu_d_writedata[30].DATAIN
A_st_data[31] => cpu_d_writedata[31].DATAIN
A_valid => cpu_d_read.IN1
A_valid => cpu_d_write.IN1
A_wr_data_filtered[0] => cpu_d_readdata[0].DATAIN
A_wr_data_filtered[1] => cpu_d_readdata[1].DATAIN
A_wr_data_filtered[2] => cpu_d_readdata[2].DATAIN
A_wr_data_filtered[3] => cpu_d_readdata[3].DATAIN
A_wr_data_filtered[4] => cpu_d_readdata[4].DATAIN
A_wr_data_filtered[5] => cpu_d_readdata[5].DATAIN
A_wr_data_filtered[6] => cpu_d_readdata[6].DATAIN
A_wr_data_filtered[7] => cpu_d_readdata[7].DATAIN
A_wr_data_filtered[8] => cpu_d_readdata[8].DATAIN
A_wr_data_filtered[9] => cpu_d_readdata[9].DATAIN
A_wr_data_filtered[10] => cpu_d_readdata[10].DATAIN
A_wr_data_filtered[11] => cpu_d_readdata[11].DATAIN
A_wr_data_filtered[12] => cpu_d_readdata[12].DATAIN
A_wr_data_filtered[13] => cpu_d_readdata[13].DATAIN
A_wr_data_filtered[14] => cpu_d_readdata[14].DATAIN
A_wr_data_filtered[15] => cpu_d_readdata[15].DATAIN
A_wr_data_filtered[16] => cpu_d_readdata[16].DATAIN
A_wr_data_filtered[17] => cpu_d_readdata[17].DATAIN
A_wr_data_filtered[18] => cpu_d_readdata[18].DATAIN
A_wr_data_filtered[19] => cpu_d_readdata[19].DATAIN
A_wr_data_filtered[20] => cpu_d_readdata[20].DATAIN
A_wr_data_filtered[21] => cpu_d_readdata[21].DATAIN
A_wr_data_filtered[22] => cpu_d_readdata[22].DATAIN
A_wr_data_filtered[23] => cpu_d_readdata[23].DATAIN
A_wr_data_filtered[24] => cpu_d_readdata[24].DATAIN
A_wr_data_filtered[25] => cpu_d_readdata[25].DATAIN
A_wr_data_filtered[26] => cpu_d_readdata[26].DATAIN
A_wr_data_filtered[27] => cpu_d_readdata[27].DATAIN
A_wr_data_filtered[28] => cpu_d_readdata[28].DATAIN
A_wr_data_filtered[29] => cpu_d_readdata[29].DATAIN
A_wr_data_filtered[30] => cpu_d_readdata[30].DATAIN
A_wr_data_filtered[31] => cpu_d_readdata[31].DATAIN
clk => dbrk_goto1~reg0.CLK
clk => dbrk_goto0~reg0.CLK
clk => dbrk_traceme~reg0.CLK
clk => dbrk_traceon~reg0.CLK
clk => dbrk_traceoff~reg0.CLK
clk => dbrk_break_pulse.CLK
clk => dbrk_trigout~reg0.CLK
clk => dbrk_break~reg0.CLK
debugack => dbrk_break.DATAB
reset_n => dbrk_goto1~reg0.ACLR
reset_n => dbrk_goto0~reg0.ACLR
reset_n => dbrk_traceme~reg0.ACLR
reset_n => dbrk_traceon~reg0.ACLR
reset_n => dbrk_traceoff~reg0.ACLR
reset_n => dbrk_break_pulse.ACLR
reset_n => dbrk_trigout~reg0.ACLR
reset_n => dbrk_break~reg0.ACLR


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace
A_cmp_result => ~NO_FANOUT~
A_ctrl_exception => ~NO_FANOUT~
A_en => instr_retired.IN0
A_op_beq => ~NO_FANOUT~
A_op_bge => ~NO_FANOUT~
A_op_bgeu => ~NO_FANOUT~
A_op_blt => ~NO_FANOUT~
A_op_bltu => ~NO_FANOUT~
A_op_bne => ~NO_FANOUT~
A_op_br => ~NO_FANOUT~
A_op_bret => ~NO_FANOUT~
A_op_call => ~NO_FANOUT~
A_op_callr => ~NO_FANOUT~
A_op_eret => ~NO_FANOUT~
A_op_jmp => ~NO_FANOUT~
A_op_jmpi => ~NO_FANOUT~
A_op_ret => ~NO_FANOUT~
A_pcb[0] => ~NO_FANOUT~
A_pcb[1] => ~NO_FANOUT~
A_pcb[2] => ~NO_FANOUT~
A_pcb[3] => ~NO_FANOUT~
A_pcb[4] => ~NO_FANOUT~
A_pcb[5] => ~NO_FANOUT~
A_pcb[6] => ~NO_FANOUT~
A_pcb[7] => ~NO_FANOUT~
A_pcb[8] => ~NO_FANOUT~
A_pcb[9] => ~NO_FANOUT~
A_pcb[10] => ~NO_FANOUT~
A_pcb[11] => ~NO_FANOUT~
A_pcb[12] => ~NO_FANOUT~
A_pcb[13] => ~NO_FANOUT~
A_pcb[14] => ~NO_FANOUT~
A_pcb[15] => ~NO_FANOUT~
A_pcb[16] => ~NO_FANOUT~
A_pcb[17] => ~NO_FANOUT~
A_pcb[18] => ~NO_FANOUT~
A_pcb[19] => ~NO_FANOUT~
A_pcb[20] => ~NO_FANOUT~
A_pcb[21] => ~NO_FANOUT~
A_pcb[22] => ~NO_FANOUT~
A_pcb[23] => ~NO_FANOUT~
A_pcb[24] => ~NO_FANOUT~
A_pcb[25] => ~NO_FANOUT~
A_pcb[26] => ~NO_FANOUT~
A_valid => instr_retired.IN1
A_wr_data_filtered[0] => ~NO_FANOUT~
A_wr_data_filtered[1] => ~NO_FANOUT~
A_wr_data_filtered[2] => ~NO_FANOUT~
A_wr_data_filtered[3] => ~NO_FANOUT~
A_wr_data_filtered[4] => ~NO_FANOUT~
A_wr_data_filtered[5] => ~NO_FANOUT~
A_wr_data_filtered[6] => ~NO_FANOUT~
A_wr_data_filtered[7] => ~NO_FANOUT~
A_wr_data_filtered[8] => ~NO_FANOUT~
A_wr_data_filtered[9] => ~NO_FANOUT~
A_wr_data_filtered[10] => ~NO_FANOUT~
A_wr_data_filtered[11] => ~NO_FANOUT~
A_wr_data_filtered[12] => ~NO_FANOUT~
A_wr_data_filtered[13] => ~NO_FANOUT~
A_wr_data_filtered[14] => ~NO_FANOUT~
A_wr_data_filtered[15] => ~NO_FANOUT~
A_wr_data_filtered[16] => ~NO_FANOUT~
A_wr_data_filtered[17] => ~NO_FANOUT~
A_wr_data_filtered[18] => ~NO_FANOUT~
A_wr_data_filtered[19] => ~NO_FANOUT~
A_wr_data_filtered[20] => ~NO_FANOUT~
A_wr_data_filtered[21] => ~NO_FANOUT~
A_wr_data_filtered[22] => ~NO_FANOUT~
A_wr_data_filtered[23] => ~NO_FANOUT~
A_wr_data_filtered[24] => ~NO_FANOUT~
A_wr_data_filtered[25] => ~NO_FANOUT~
A_wr_data_filtered[26] => ~NO_FANOUT~
A_wr_data_filtered[27] => ~NO_FANOUT~
A_wr_data_filtered[28] => ~NO_FANOUT~
A_wr_data_filtered[29] => ~NO_FANOUT~
A_wr_data_filtered[30] => ~NO_FANOUT~
A_wr_data_filtered[31] => ~NO_FANOUT~
clk => dct_count[0]~reg0.CLK
clk => dct_count[1]~reg0.CLK
clk => dct_count[2]~reg0.CLK
clk => dct_count[3]~reg0.CLK
clk => dct_buffer[0]~reg0.CLK
clk => dct_buffer[1]~reg0.CLK
clk => dct_buffer[2]~reg0.CLK
clk => dct_buffer[3]~reg0.CLK
clk => dct_buffer[4]~reg0.CLK
clk => dct_buffer[5]~reg0.CLK
clk => dct_buffer[6]~reg0.CLK
clk => dct_buffer[7]~reg0.CLK
clk => dct_buffer[8]~reg0.CLK
clk => dct_buffer[9]~reg0.CLK
clk => dct_buffer[10]~reg0.CLK
clk => dct_buffer[11]~reg0.CLK
clk => dct_buffer[12]~reg0.CLK
clk => dct_buffer[13]~reg0.CLK
clk => dct_buffer[14]~reg0.CLK
clk => dct_buffer[15]~reg0.CLK
clk => dct_buffer[16]~reg0.CLK
clk => dct_buffer[17]~reg0.CLK
clk => dct_buffer[18]~reg0.CLK
clk => dct_buffer[19]~reg0.CLK
clk => dct_buffer[20]~reg0.CLK
clk => dct_buffer[21]~reg0.CLK
clk => dct_buffer[22]~reg0.CLK
clk => dct_buffer[23]~reg0.CLK
clk => dct_buffer[24]~reg0.CLK
clk => dct_buffer[25]~reg0.CLK
clk => dct_buffer[26]~reg0.CLK
clk => dct_buffer[27]~reg0.CLK
clk => dct_buffer[28]~reg0.CLK
clk => dct_buffer[29]~reg0.CLK
clk => itm[0]~reg0.CLK
clk => itm[1]~reg0.CLK
clk => itm[2]~reg0.CLK
clk => itm[3]~reg0.CLK
clk => itm[4]~reg0.CLK
clk => itm[5]~reg0.CLK
clk => itm[6]~reg0.CLK
clk => itm[7]~reg0.CLK
clk => itm[8]~reg0.CLK
clk => itm[9]~reg0.CLK
clk => itm[10]~reg0.CLK
clk => itm[11]~reg0.CLK
clk => itm[12]~reg0.CLK
clk => itm[13]~reg0.CLK
clk => itm[14]~reg0.CLK
clk => itm[15]~reg0.CLK
clk => itm[16]~reg0.CLK
clk => itm[17]~reg0.CLK
clk => itm[18]~reg0.CLK
clk => itm[19]~reg0.CLK
clk => itm[20]~reg0.CLK
clk => itm[21]~reg0.CLK
clk => itm[22]~reg0.CLK
clk => itm[23]~reg0.CLK
clk => itm[24]~reg0.CLK
clk => itm[25]~reg0.CLK
clk => itm[26]~reg0.CLK
clk => itm[27]~reg0.CLK
clk => itm[28]~reg0.CLK
clk => itm[29]~reg0.CLK
clk => itm[30]~reg0.CLK
clk => itm[31]~reg0.CLK
clk => itm[32]~reg0.CLK
clk => itm[33]~reg0.CLK
clk => itm[34]~reg0.CLK
clk => itm[35]~reg0.CLK
clk => d1_debugack.CLK
dbrk_traceoff => ~NO_FANOUT~
dbrk_traceon => ~NO_FANOUT~
debugack => d1_debugack.DATAIN
jdo[0] => ~NO_FANOUT~
jdo[1] => ~NO_FANOUT~
jdo[2] => ~NO_FANOUT~
jdo[3] => ~NO_FANOUT~
jdo[4] => ~NO_FANOUT~
jdo[5] => ~NO_FANOUT~
jdo[6] => ~NO_FANOUT~
jdo[7] => ~NO_FANOUT~
jdo[8] => ~NO_FANOUT~
jdo[9] => ~NO_FANOUT~
jdo[10] => ~NO_FANOUT~
jdo[11] => ~NO_FANOUT~
jdo[12] => ~NO_FANOUT~
jdo[13] => ~NO_FANOUT~
jdo[14] => ~NO_FANOUT~
jdo[15] => ~NO_FANOUT~
jrst_n => dct_count[0]~reg0.ACLR
jrst_n => dct_count[1]~reg0.ACLR
jrst_n => dct_count[2]~reg0.ACLR
jrst_n => dct_count[3]~reg0.ACLR
jrst_n => dct_buffer[0]~reg0.ACLR
jrst_n => dct_buffer[1]~reg0.ACLR
jrst_n => dct_buffer[2]~reg0.ACLR
jrst_n => dct_buffer[3]~reg0.ACLR
jrst_n => dct_buffer[4]~reg0.ACLR
jrst_n => dct_buffer[5]~reg0.ACLR
jrst_n => dct_buffer[6]~reg0.ACLR
jrst_n => dct_buffer[7]~reg0.ACLR
jrst_n => dct_buffer[8]~reg0.ACLR
jrst_n => dct_buffer[9]~reg0.ACLR
jrst_n => dct_buffer[10]~reg0.ACLR
jrst_n => dct_buffer[11]~reg0.ACLR
jrst_n => dct_buffer[12]~reg0.ACLR
jrst_n => dct_buffer[13]~reg0.ACLR
jrst_n => dct_buffer[14]~reg0.ACLR
jrst_n => dct_buffer[15]~reg0.ACLR
jrst_n => dct_buffer[16]~reg0.ACLR
jrst_n => dct_buffer[17]~reg0.ACLR
jrst_n => dct_buffer[18]~reg0.ACLR
jrst_n => dct_buffer[19]~reg0.ACLR
jrst_n => dct_buffer[20]~reg0.ACLR
jrst_n => dct_buffer[21]~reg0.ACLR
jrst_n => dct_buffer[22]~reg0.ACLR
jrst_n => dct_buffer[23]~reg0.ACLR
jrst_n => dct_buffer[24]~reg0.ACLR
jrst_n => dct_buffer[25]~reg0.ACLR
jrst_n => dct_buffer[26]~reg0.ACLR
jrst_n => dct_buffer[27]~reg0.ACLR
jrst_n => dct_buffer[28]~reg0.ACLR
jrst_n => dct_buffer[29]~reg0.ACLR
jrst_n => itm[0]~reg0.ACLR
jrst_n => itm[1]~reg0.ACLR
jrst_n => itm[2]~reg0.ACLR
jrst_n => itm[3]~reg0.ACLR
jrst_n => itm[4]~reg0.ACLR
jrst_n => itm[5]~reg0.ACLR
jrst_n => itm[6]~reg0.ACLR
jrst_n => itm[7]~reg0.ACLR
jrst_n => itm[8]~reg0.ACLR
jrst_n => itm[9]~reg0.ACLR
jrst_n => itm[10]~reg0.ACLR
jrst_n => itm[11]~reg0.ACLR
jrst_n => itm[12]~reg0.ACLR
jrst_n => itm[13]~reg0.ACLR
jrst_n => itm[14]~reg0.ACLR
jrst_n => itm[15]~reg0.ACLR
jrst_n => itm[16]~reg0.ACLR
jrst_n => itm[17]~reg0.ACLR
jrst_n => itm[18]~reg0.ACLR
jrst_n => itm[19]~reg0.ACLR
jrst_n => itm[20]~reg0.ACLR
jrst_n => itm[21]~reg0.ACLR
jrst_n => itm[22]~reg0.ACLR
jrst_n => itm[23]~reg0.ACLR
jrst_n => itm[24]~reg0.ACLR
jrst_n => itm[25]~reg0.ACLR
jrst_n => itm[26]~reg0.ACLR
jrst_n => itm[27]~reg0.ACLR
jrst_n => itm[28]~reg0.ACLR
jrst_n => itm[29]~reg0.ACLR
jrst_n => itm[30]~reg0.ACLR
jrst_n => itm[31]~reg0.ACLR
jrst_n => itm[32]~reg0.ACLR
jrst_n => itm[33]~reg0.ACLR
jrst_n => itm[34]~reg0.ACLR
jrst_n => itm[35]~reg0.ACLR
reset_n => d1_debugack.ACLR
take_action_tracectrl => ~NO_FANOUT~
trc_enb => ~NO_FANOUT~
xbrk_traceoff => ~NO_FANOUT~
xbrk_traceon => ~NO_FANOUT~
xbrk_wrap_traceoff => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace
clk => dtm[0]~reg0.CLK
clk => dtm[1]~reg0.CLK
clk => dtm[2]~reg0.CLK
clk => dtm[3]~reg0.CLK
clk => dtm[4]~reg0.CLK
clk => dtm[5]~reg0.CLK
clk => dtm[6]~reg0.CLK
clk => dtm[7]~reg0.CLK
clk => dtm[8]~reg0.CLK
clk => dtm[9]~reg0.CLK
clk => dtm[10]~reg0.CLK
clk => dtm[11]~reg0.CLK
clk => dtm[12]~reg0.CLK
clk => dtm[13]~reg0.CLK
clk => dtm[14]~reg0.CLK
clk => dtm[15]~reg0.CLK
clk => dtm[16]~reg0.CLK
clk => dtm[17]~reg0.CLK
clk => dtm[18]~reg0.CLK
clk => dtm[19]~reg0.CLK
clk => dtm[20]~reg0.CLK
clk => dtm[21]~reg0.CLK
clk => dtm[22]~reg0.CLK
clk => dtm[23]~reg0.CLK
clk => dtm[24]~reg0.CLK
clk => dtm[25]~reg0.CLK
clk => dtm[26]~reg0.CLK
clk => dtm[27]~reg0.CLK
clk => dtm[28]~reg0.CLK
clk => dtm[29]~reg0.CLK
clk => dtm[30]~reg0.CLK
clk => dtm[31]~reg0.CLK
clk => dtm[32]~reg0.CLK
clk => dtm[33]~reg0.CLK
clk => dtm[34]~reg0.CLK
clk => dtm[35]~reg0.CLK
clk => atm[0]~reg0.CLK
clk => atm[1]~reg0.CLK
clk => atm[2]~reg0.CLK
clk => atm[3]~reg0.CLK
clk => atm[4]~reg0.CLK
clk => atm[5]~reg0.CLK
clk => atm[6]~reg0.CLK
clk => atm[7]~reg0.CLK
clk => atm[8]~reg0.CLK
clk => atm[9]~reg0.CLK
clk => atm[10]~reg0.CLK
clk => atm[11]~reg0.CLK
clk => atm[12]~reg0.CLK
clk => atm[13]~reg0.CLK
clk => atm[14]~reg0.CLK
clk => atm[15]~reg0.CLK
clk => atm[16]~reg0.CLK
clk => atm[17]~reg0.CLK
clk => atm[18]~reg0.CLK
clk => atm[19]~reg0.CLK
clk => atm[20]~reg0.CLK
clk => atm[21]~reg0.CLK
clk => atm[22]~reg0.CLK
clk => atm[23]~reg0.CLK
clk => atm[24]~reg0.CLK
clk => atm[25]~reg0.CLK
clk => atm[26]~reg0.CLK
clk => atm[27]~reg0.CLK
clk => atm[28]~reg0.CLK
clk => atm[29]~reg0.CLK
clk => atm[30]~reg0.CLK
clk => atm[31]~reg0.CLK
clk => atm[32]~reg0.CLK
clk => atm[33]~reg0.CLK
clk => atm[34]~reg0.CLK
clk => atm[35]~reg0.CLK
cpu_d_address[0] => ~NO_FANOUT~
cpu_d_address[1] => ~NO_FANOUT~
cpu_d_address[2] => ~NO_FANOUT~
cpu_d_address[3] => ~NO_FANOUT~
cpu_d_address[4] => ~NO_FANOUT~
cpu_d_address[5] => ~NO_FANOUT~
cpu_d_address[6] => ~NO_FANOUT~
cpu_d_address[7] => ~NO_FANOUT~
cpu_d_address[8] => ~NO_FANOUT~
cpu_d_address[9] => ~NO_FANOUT~
cpu_d_address[10] => ~NO_FANOUT~
cpu_d_address[11] => ~NO_FANOUT~
cpu_d_address[12] => ~NO_FANOUT~
cpu_d_address[13] => ~NO_FANOUT~
cpu_d_address[14] => ~NO_FANOUT~
cpu_d_address[15] => ~NO_FANOUT~
cpu_d_address[16] => ~NO_FANOUT~
cpu_d_address[17] => ~NO_FANOUT~
cpu_d_address[18] => ~NO_FANOUT~
cpu_d_address[19] => ~NO_FANOUT~
cpu_d_address[20] => ~NO_FANOUT~
cpu_d_address[21] => ~NO_FANOUT~
cpu_d_address[22] => ~NO_FANOUT~
cpu_d_address[23] => ~NO_FANOUT~
cpu_d_address[24] => ~NO_FANOUT~
cpu_d_address[25] => ~NO_FANOUT~
cpu_d_address[26] => ~NO_FANOUT~
cpu_d_read => ~NO_FANOUT~
cpu_d_readdata[0] => ~NO_FANOUT~
cpu_d_readdata[1] => ~NO_FANOUT~
cpu_d_readdata[2] => ~NO_FANOUT~
cpu_d_readdata[3] => ~NO_FANOUT~
cpu_d_readdata[4] => ~NO_FANOUT~
cpu_d_readdata[5] => ~NO_FANOUT~
cpu_d_readdata[6] => ~NO_FANOUT~
cpu_d_readdata[7] => ~NO_FANOUT~
cpu_d_readdata[8] => ~NO_FANOUT~
cpu_d_readdata[9] => ~NO_FANOUT~
cpu_d_readdata[10] => ~NO_FANOUT~
cpu_d_readdata[11] => ~NO_FANOUT~
cpu_d_readdata[12] => ~NO_FANOUT~
cpu_d_readdata[13] => ~NO_FANOUT~
cpu_d_readdata[14] => ~NO_FANOUT~
cpu_d_readdata[15] => ~NO_FANOUT~
cpu_d_readdata[16] => ~NO_FANOUT~
cpu_d_readdata[17] => ~NO_FANOUT~
cpu_d_readdata[18] => ~NO_FANOUT~
cpu_d_readdata[19] => ~NO_FANOUT~
cpu_d_readdata[20] => ~NO_FANOUT~
cpu_d_readdata[21] => ~NO_FANOUT~
cpu_d_readdata[22] => ~NO_FANOUT~
cpu_d_readdata[23] => ~NO_FANOUT~
cpu_d_readdata[24] => ~NO_FANOUT~
cpu_d_readdata[25] => ~NO_FANOUT~
cpu_d_readdata[26] => ~NO_FANOUT~
cpu_d_readdata[27] => ~NO_FANOUT~
cpu_d_readdata[28] => ~NO_FANOUT~
cpu_d_readdata[29] => ~NO_FANOUT~
cpu_d_readdata[30] => ~NO_FANOUT~
cpu_d_readdata[31] => ~NO_FANOUT~
cpu_d_wait => ~NO_FANOUT~
cpu_d_write => ~NO_FANOUT~
cpu_d_writedata[0] => ~NO_FANOUT~
cpu_d_writedata[1] => ~NO_FANOUT~
cpu_d_writedata[2] => ~NO_FANOUT~
cpu_d_writedata[3] => ~NO_FANOUT~
cpu_d_writedata[4] => ~NO_FANOUT~
cpu_d_writedata[5] => ~NO_FANOUT~
cpu_d_writedata[6] => ~NO_FANOUT~
cpu_d_writedata[7] => ~NO_FANOUT~
cpu_d_writedata[8] => ~NO_FANOUT~
cpu_d_writedata[9] => ~NO_FANOUT~
cpu_d_writedata[10] => ~NO_FANOUT~
cpu_d_writedata[11] => ~NO_FANOUT~
cpu_d_writedata[12] => ~NO_FANOUT~
cpu_d_writedata[13] => ~NO_FANOUT~
cpu_d_writedata[14] => ~NO_FANOUT~
cpu_d_writedata[15] => ~NO_FANOUT~
cpu_d_writedata[16] => ~NO_FANOUT~
cpu_d_writedata[17] => ~NO_FANOUT~
cpu_d_writedata[18] => ~NO_FANOUT~
cpu_d_writedata[19] => ~NO_FANOUT~
cpu_d_writedata[20] => ~NO_FANOUT~
cpu_d_writedata[21] => ~NO_FANOUT~
cpu_d_writedata[22] => ~NO_FANOUT~
cpu_d_writedata[23] => ~NO_FANOUT~
cpu_d_writedata[24] => ~NO_FANOUT~
cpu_d_writedata[25] => ~NO_FANOUT~
cpu_d_writedata[26] => ~NO_FANOUT~
cpu_d_writedata[27] => ~NO_FANOUT~
cpu_d_writedata[28] => ~NO_FANOUT~
cpu_d_writedata[29] => ~NO_FANOUT~
cpu_d_writedata[30] => ~NO_FANOUT~
cpu_d_writedata[31] => ~NO_FANOUT~
jrst_n => dtm[0]~reg0.ACLR
jrst_n => dtm[1]~reg0.ACLR
jrst_n => dtm[2]~reg0.ACLR
jrst_n => dtm[3]~reg0.ACLR
jrst_n => dtm[4]~reg0.ACLR
jrst_n => dtm[5]~reg0.ACLR
jrst_n => dtm[6]~reg0.ACLR
jrst_n => dtm[7]~reg0.ACLR
jrst_n => dtm[8]~reg0.ACLR
jrst_n => dtm[9]~reg0.ACLR
jrst_n => dtm[10]~reg0.ACLR
jrst_n => dtm[11]~reg0.ACLR
jrst_n => dtm[12]~reg0.ACLR
jrst_n => dtm[13]~reg0.ACLR
jrst_n => dtm[14]~reg0.ACLR
jrst_n => dtm[15]~reg0.ACLR
jrst_n => dtm[16]~reg0.ACLR
jrst_n => dtm[17]~reg0.ACLR
jrst_n => dtm[18]~reg0.ACLR
jrst_n => dtm[19]~reg0.ACLR
jrst_n => dtm[20]~reg0.ACLR
jrst_n => dtm[21]~reg0.ACLR
jrst_n => dtm[22]~reg0.ACLR
jrst_n => dtm[23]~reg0.ACLR
jrst_n => dtm[24]~reg0.ACLR
jrst_n => dtm[25]~reg0.ACLR
jrst_n => dtm[26]~reg0.ACLR
jrst_n => dtm[27]~reg0.ACLR
jrst_n => dtm[28]~reg0.ACLR
jrst_n => dtm[29]~reg0.ACLR
jrst_n => dtm[30]~reg0.ACLR
jrst_n => dtm[31]~reg0.ACLR
jrst_n => dtm[32]~reg0.ACLR
jrst_n => dtm[33]~reg0.ACLR
jrst_n => dtm[34]~reg0.ACLR
jrst_n => dtm[35]~reg0.ACLR
jrst_n => atm[0]~reg0.ACLR
jrst_n => atm[1]~reg0.ACLR
jrst_n => atm[2]~reg0.ACLR
jrst_n => atm[3]~reg0.ACLR
jrst_n => atm[4]~reg0.ACLR
jrst_n => atm[5]~reg0.ACLR
jrst_n => atm[6]~reg0.ACLR
jrst_n => atm[7]~reg0.ACLR
jrst_n => atm[8]~reg0.ACLR
jrst_n => atm[9]~reg0.ACLR
jrst_n => atm[10]~reg0.ACLR
jrst_n => atm[11]~reg0.ACLR
jrst_n => atm[12]~reg0.ACLR
jrst_n => atm[13]~reg0.ACLR
jrst_n => atm[14]~reg0.ACLR
jrst_n => atm[15]~reg0.ACLR
jrst_n => atm[16]~reg0.ACLR
jrst_n => atm[17]~reg0.ACLR
jrst_n => atm[18]~reg0.ACLR
jrst_n => atm[19]~reg0.ACLR
jrst_n => atm[20]~reg0.ACLR
jrst_n => atm[21]~reg0.ACLR
jrst_n => atm[22]~reg0.ACLR
jrst_n => atm[23]~reg0.ACLR
jrst_n => atm[24]~reg0.ACLR
jrst_n => atm[25]~reg0.ACLR
jrst_n => atm[26]~reg0.ACLR
jrst_n => atm[27]~reg0.ACLR
jrst_n => atm[28]~reg0.ACLR
jrst_n => atm[29]~reg0.ACLR
jrst_n => atm[30]~reg0.ACLR
jrst_n => atm[31]~reg0.ACLR
jrst_n => atm[32]~reg0.ACLR
jrst_n => atm[33]~reg0.ACLR
jrst_n => atm[34]~reg0.ACLR
jrst_n => atm[35]~reg0.ACLR
trc_ctrl[0] => trc_ctrl[0].IN1
trc_ctrl[1] => trc_ctrl[1].IN1
trc_ctrl[2] => trc_ctrl[2].IN1
trc_ctrl[3] => trc_ctrl[3].IN1
trc_ctrl[4] => trc_ctrl[4].IN1
trc_ctrl[5] => trc_ctrl[5].IN1
trc_ctrl[6] => trc_ctrl[6].IN1
trc_ctrl[7] => trc_ctrl[7].IN1
trc_ctrl[8] => trc_ctrl[8].IN1
trc_ctrl[9] => ~NO_FANOUT~
trc_ctrl[10] => ~NO_FANOUT~
trc_ctrl[11] => ~NO_FANOUT~
trc_ctrl[12] => ~NO_FANOUT~
trc_ctrl[13] => ~NO_FANOUT~
trc_ctrl[14] => ~NO_FANOUT~
trc_ctrl[15] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode
ctrl[0] => ~NO_FANOUT~
ctrl[1] => ~NO_FANOUT~
ctrl[2] => ~NO_FANOUT~
ctrl[3] => ~NO_FANOUT~
ctrl[4] => ~NO_FANOUT~
ctrl[5] => Decoder0.IN2
ctrl[5] => td_mode[3].DATAIN
ctrl[6] => Decoder0.IN1
ctrl[6] => Decoder1.IN1
ctrl[6] => td_mode[2].DATAIN
ctrl[7] => Decoder0.IN0
ctrl[7] => Decoder1.IN0
ctrl[8] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo
atm[0] => ~NO_FANOUT~
atm[1] => ~NO_FANOUT~
atm[2] => ~NO_FANOUT~
atm[3] => ~NO_FANOUT~
atm[4] => ~NO_FANOUT~
atm[5] => ~NO_FANOUT~
atm[6] => ~NO_FANOUT~
atm[7] => ~NO_FANOUT~
atm[8] => ~NO_FANOUT~
atm[9] => ~NO_FANOUT~
atm[10] => ~NO_FANOUT~
atm[11] => ~NO_FANOUT~
atm[12] => ~NO_FANOUT~
atm[13] => ~NO_FANOUT~
atm[14] => ~NO_FANOUT~
atm[15] => ~NO_FANOUT~
atm[16] => ~NO_FANOUT~
atm[17] => ~NO_FANOUT~
atm[18] => ~NO_FANOUT~
atm[19] => ~NO_FANOUT~
atm[20] => ~NO_FANOUT~
atm[21] => ~NO_FANOUT~
atm[22] => ~NO_FANOUT~
atm[23] => ~NO_FANOUT~
atm[24] => ~NO_FANOUT~
atm[25] => ~NO_FANOUT~
atm[26] => ~NO_FANOUT~
atm[27] => ~NO_FANOUT~
atm[28] => ~NO_FANOUT~
atm[29] => ~NO_FANOUT~
atm[30] => ~NO_FANOUT~
atm[31] => ~NO_FANOUT~
atm[32] => WideOr1.IN0
atm[33] => WideOr1.IN1
atm[34] => WideOr1.IN2
atm[35] => WideOr1.IN3
clk => fifocount[0].CLK
clk => fifocount[1].CLK
clk => fifocount[2].CLK
clk => fifocount[3].CLK
clk => fifocount[4].CLK
dbrk_traceme => trc_this.IN1
dbrk_traceoff => trc_this.IN0
dbrk_traceon => trc_this.IN1
dct_buffer[0] => dct_buffer[0].IN1
dct_buffer[1] => dct_buffer[1].IN1
dct_buffer[2] => dct_buffer[2].IN1
dct_buffer[3] => dct_buffer[3].IN1
dct_buffer[4] => dct_buffer[4].IN1
dct_buffer[5] => dct_buffer[5].IN1
dct_buffer[6] => dct_buffer[6].IN1
dct_buffer[7] => dct_buffer[7].IN1
dct_buffer[8] => dct_buffer[8].IN1
dct_buffer[9] => dct_buffer[9].IN1
dct_buffer[10] => dct_buffer[10].IN1
dct_buffer[11] => dct_buffer[11].IN1
dct_buffer[12] => dct_buffer[12].IN1
dct_buffer[13] => dct_buffer[13].IN1
dct_buffer[14] => dct_buffer[14].IN1
dct_buffer[15] => dct_buffer[15].IN1
dct_buffer[16] => dct_buffer[16].IN1
dct_buffer[17] => dct_buffer[17].IN1
dct_buffer[18] => dct_buffer[18].IN1
dct_buffer[19] => dct_buffer[19].IN1
dct_buffer[20] => dct_buffer[20].IN1
dct_buffer[21] => dct_buffer[21].IN1
dct_buffer[22] => dct_buffer[22].IN1
dct_buffer[23] => dct_buffer[23].IN1
dct_buffer[24] => dct_buffer[24].IN1
dct_buffer[25] => dct_buffer[25].IN1
dct_buffer[26] => dct_buffer[26].IN1
dct_buffer[27] => dct_buffer[27].IN1
dct_buffer[28] => dct_buffer[28].IN1
dct_buffer[29] => dct_buffer[29].IN1
dct_count[0] => dct_count[0].IN1
dct_count[1] => dct_count[1].IN1
dct_count[2] => dct_count[2].IN1
dct_count[3] => dct_count[3].IN1
dtm[0] => ~NO_FANOUT~
dtm[1] => ~NO_FANOUT~
dtm[2] => ~NO_FANOUT~
dtm[3] => ~NO_FANOUT~
dtm[4] => ~NO_FANOUT~
dtm[5] => ~NO_FANOUT~
dtm[6] => ~NO_FANOUT~
dtm[7] => ~NO_FANOUT~
dtm[8] => ~NO_FANOUT~
dtm[9] => ~NO_FANOUT~
dtm[10] => ~NO_FANOUT~
dtm[11] => ~NO_FANOUT~
dtm[12] => ~NO_FANOUT~
dtm[13] => ~NO_FANOUT~
dtm[14] => ~NO_FANOUT~
dtm[15] => ~NO_FANOUT~
dtm[16] => ~NO_FANOUT~
dtm[17] => ~NO_FANOUT~
dtm[18] => ~NO_FANOUT~
dtm[19] => ~NO_FANOUT~
dtm[20] => ~NO_FANOUT~
dtm[21] => ~NO_FANOUT~
dtm[22] => ~NO_FANOUT~
dtm[23] => ~NO_FANOUT~
dtm[24] => ~NO_FANOUT~
dtm[25] => ~NO_FANOUT~
dtm[26] => ~NO_FANOUT~
dtm[27] => ~NO_FANOUT~
dtm[28] => ~NO_FANOUT~
dtm[29] => ~NO_FANOUT~
dtm[30] => ~NO_FANOUT~
dtm[31] => ~NO_FANOUT~
dtm[32] => WideOr2.IN0
dtm[33] => WideOr2.IN1
dtm[34] => WideOr2.IN2
dtm[35] => WideOr2.IN3
itm[0] => tw[0].DATAIN
itm[1] => tw[1].DATAIN
itm[2] => tw[2].DATAIN
itm[3] => tw[3].DATAIN
itm[4] => tw[4].DATAIN
itm[5] => tw[5].DATAIN
itm[6] => tw[6].DATAIN
itm[7] => tw[7].DATAIN
itm[8] => tw[8].DATAIN
itm[9] => tw[9].DATAIN
itm[10] => tw[10].DATAIN
itm[11] => tw[11].DATAIN
itm[12] => tw[12].DATAIN
itm[13] => tw[13].DATAIN
itm[14] => tw[14].DATAIN
itm[15] => tw[15].DATAIN
itm[16] => tw[16].DATAIN
itm[17] => tw[17].DATAIN
itm[18] => tw[18].DATAIN
itm[19] => tw[19].DATAIN
itm[20] => tw[20].DATAIN
itm[21] => tw[21].DATAIN
itm[22] => tw[22].DATAIN
itm[23] => tw[23].DATAIN
itm[24] => tw[24].DATAIN
itm[25] => tw[25].DATAIN
itm[26] => tw[26].DATAIN
itm[27] => tw[27].DATAIN
itm[28] => tw[28].DATAIN
itm[29] => tw[29].DATAIN
itm[30] => tw[30].DATAIN
itm[31] => tw[31].DATAIN
itm[32] => WideOr0.IN0
itm[32] => tw[32].DATAIN
itm[33] => WideOr0.IN1
itm[33] => tw[33].DATAIN
itm[34] => WideOr0.IN2
itm[34] => tw[34].DATAIN
itm[35] => WideOr0.IN3
itm[35] => tw[35].DATAIN
jrst_n => fifocount[0].ACLR
jrst_n => fifocount[1].ACLR
jrst_n => fifocount[2].ACLR
jrst_n => fifocount[3].ACLR
jrst_n => fifocount[4].ACLR
reset_n => ~NO_FANOUT~
test_ending => test_ending.IN1
test_has_ended => test_has_ended.IN1
trc_on => trc_this.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count
atm_valid => Decoder0.IN1
dtm_valid => Decoder0.IN2
itm_valid => Decoder0.IN0


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp
free2 => always0.IN1
free3 => always0.IN1
tm_count[0] => LessThan0.IN4
tm_count[0] => LessThan1.IN4
tm_count[0] => Equal0.IN1
tm_count[1] => LessThan0.IN3
tm_count[1] => LessThan1.IN3
tm_count[1] => Equal0.IN0


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount
empty => fifocount_inc.OUTPUTSELECT
empty => fifocount_inc.OUTPUTSELECT
empty => fifocount_inc.OUTPUTSELECT
empty => fifocount_inc.OUTPUTSELECT
empty => fifocount_inc.OUTPUTSELECT
free2 => always0.IN1
free3 => always0.IN1
tm_count[0] => LessThan0.IN4
tm_count[0] => LessThan1.IN4
tm_count[0] => fifocount_inc.DATAB
tm_count[0] => Equal0.IN1
tm_count[1] => LessThan0.IN3
tm_count[1] => LessThan1.IN3
tm_count[1] => fifocount_inc.DATAB
tm_count[1] => Equal0.IN0


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_oci_test_bench:the_cpu_oci_test_bench
dct_buffer[0] => ~NO_FANOUT~
dct_buffer[1] => ~NO_FANOUT~
dct_buffer[2] => ~NO_FANOUT~
dct_buffer[3] => ~NO_FANOUT~
dct_buffer[4] => ~NO_FANOUT~
dct_buffer[5] => ~NO_FANOUT~
dct_buffer[6] => ~NO_FANOUT~
dct_buffer[7] => ~NO_FANOUT~
dct_buffer[8] => ~NO_FANOUT~
dct_buffer[9] => ~NO_FANOUT~
dct_buffer[10] => ~NO_FANOUT~
dct_buffer[11] => ~NO_FANOUT~
dct_buffer[12] => ~NO_FANOUT~
dct_buffer[13] => ~NO_FANOUT~
dct_buffer[14] => ~NO_FANOUT~
dct_buffer[15] => ~NO_FANOUT~
dct_buffer[16] => ~NO_FANOUT~
dct_buffer[17] => ~NO_FANOUT~
dct_buffer[18] => ~NO_FANOUT~
dct_buffer[19] => ~NO_FANOUT~
dct_buffer[20] => ~NO_FANOUT~
dct_buffer[21] => ~NO_FANOUT~
dct_buffer[22] => ~NO_FANOUT~
dct_buffer[23] => ~NO_FANOUT~
dct_buffer[24] => ~NO_FANOUT~
dct_buffer[25] => ~NO_FANOUT~
dct_buffer[26] => ~NO_FANOUT~
dct_buffer[27] => ~NO_FANOUT~
dct_buffer[28] => ~NO_FANOUT~
dct_buffer[29] => ~NO_FANOUT~
dct_count[0] => ~NO_FANOUT~
dct_count[1] => ~NO_FANOUT~
dct_count[2] => ~NO_FANOUT~
dct_count[3] => ~NO_FANOUT~
test_ending => ~NO_FANOUT~
test_has_ended => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib
clk => ~NO_FANOUT~
clkx2 => ~NO_FANOUT~
jrst_n => ~NO_FANOUT~
tw[0] => ~NO_FANOUT~
tw[1] => ~NO_FANOUT~
tw[2] => ~NO_FANOUT~
tw[3] => ~NO_FANOUT~
tw[4] => ~NO_FANOUT~
tw[5] => ~NO_FANOUT~
tw[6] => ~NO_FANOUT~
tw[7] => ~NO_FANOUT~
tw[8] => ~NO_FANOUT~
tw[9] => ~NO_FANOUT~
tw[10] => ~NO_FANOUT~
tw[11] => ~NO_FANOUT~
tw[12] => ~NO_FANOUT~
tw[13] => ~NO_FANOUT~
tw[14] => ~NO_FANOUT~
tw[15] => ~NO_FANOUT~
tw[16] => ~NO_FANOUT~
tw[17] => ~NO_FANOUT~
tw[18] => ~NO_FANOUT~
tw[19] => ~NO_FANOUT~
tw[20] => ~NO_FANOUT~
tw[21] => ~NO_FANOUT~
tw[22] => ~NO_FANOUT~
tw[23] => ~NO_FANOUT~
tw[24] => ~NO_FANOUT~
tw[25] => ~NO_FANOUT~
tw[26] => ~NO_FANOUT~
tw[27] => ~NO_FANOUT~
tw[28] => ~NO_FANOUT~
tw[29] => ~NO_FANOUT~
tw[30] => ~NO_FANOUT~
tw[31] => ~NO_FANOUT~
tw[32] => ~NO_FANOUT~
tw[33] => ~NO_FANOUT~
tw[34] => ~NO_FANOUT~
tw[35] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im
clk => clk.IN2
jdo[0] => ~NO_FANOUT~
jdo[1] => jdo[1].IN1
jdo[2] => jdo[2].IN1
jdo[3] => jdo[3].IN1
jdo[4] => jdo[4].IN1
jdo[5] => jdo[5].IN1
jdo[6] => jdo[6].IN1
jdo[7] => jdo[7].IN1
jdo[8] => jdo[8].IN1
jdo[9] => jdo[9].IN1
jdo[10] => jdo[10].IN1
jdo[11] => jdo[11].IN1
jdo[12] => jdo[12].IN1
jdo[13] => jdo[13].IN1
jdo[14] => jdo[14].IN1
jdo[15] => jdo[15].IN1
jdo[16] => jdo[16].IN1
jdo[17] => jdo[17].IN1
jdo[18] => jdo[18].IN1
jdo[19] => jdo[19].IN1
jdo[20] => jdo[20].IN1
jdo[21] => jdo[21].IN1
jdo[22] => jdo[22].IN1
jdo[23] => jdo[23].IN1
jdo[24] => jdo[24].IN1
jdo[25] => jdo[25].IN1
jdo[26] => jdo[26].IN1
jdo[27] => jdo[27].IN1
jdo[28] => jdo[28].IN1
jdo[29] => jdo[29].IN1
jdo[30] => jdo[30].IN1
jdo[31] => jdo[31].IN1
jdo[32] => jdo[32].IN1
jdo[33] => jdo[33].IN1
jdo[34] => jdo[34].IN1
jdo[35] => jdo[35].IN1
jdo[36] => jdo[36].IN1
jdo[37] => ~NO_FANOUT~
jrst_n => trc_wrap~reg0.ACLR
jrst_n => trc_im_addr[0]~reg0.ACLR
jrst_n => trc_im_addr[1]~reg0.ACLR
jrst_n => trc_im_addr[2]~reg0.ACLR
jrst_n => trc_im_addr[3]~reg0.ACLR
jrst_n => trc_im_addr[4]~reg0.ACLR
jrst_n => trc_im_addr[5]~reg0.ACLR
jrst_n => trc_im_addr[6]~reg0.ACLR
reset_n => trc_jtag_addr[0].ACLR
reset_n => trc_jtag_addr[1].ACLR
reset_n => trc_jtag_addr[2].ACLR
reset_n => trc_jtag_addr[3].ACLR
reset_n => trc_jtag_addr[4].ACLR
reset_n => trc_jtag_addr[5].ACLR
reset_n => trc_jtag_addr[6].ACLR
reset_n => trc_jtag_addr[7].ACLR
reset_n => trc_jtag_addr[8].ACLR
reset_n => trc_jtag_addr[9].ACLR
reset_n => trc_jtag_addr[10].ACLR
reset_n => trc_jtag_addr[11].ACLR
reset_n => trc_jtag_addr[12].ACLR
reset_n => trc_jtag_addr[13].ACLR
reset_n => trc_jtag_addr[14].ACLR
reset_n => trc_jtag_addr[15].ACLR
reset_n => trc_jtag_addr[16].ACLR
take_action_tracectrl => ~NO_FANOUT~
take_action_tracemem_a => always1.IN0
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT
take_action_tracemem_b => take_action_tracemem_b.IN1
take_no_action_tracemem_a => always1.IN1
trc_ctrl[0] => comb.IN1
trc_ctrl[0] => trc_enb.DATAIN
trc_ctrl[0] => tracemem_on.DATAIN
trc_ctrl[1] => ~NO_FANOUT~
trc_ctrl[2] => ~NO_FANOUT~
trc_ctrl[3] => ~NO_FANOUT~
trc_ctrl[4] => ~NO_FANOUT~
trc_ctrl[5] => ~NO_FANOUT~
trc_ctrl[6] => ~NO_FANOUT~
trc_ctrl[7] => ~NO_FANOUT~
trc_ctrl[8] => ~NO_FANOUT~
trc_ctrl[9] => ~NO_FANOUT~
trc_ctrl[10] => xbrk_wrap_traceoff.IN1
trc_ctrl[11] => ~NO_FANOUT~
trc_ctrl[12] => ~NO_FANOUT~
trc_ctrl[13] => ~NO_FANOUT~
trc_ctrl[14] => ~NO_FANOUT~
trc_ctrl[15] => ~NO_FANOUT~
tw[0] => trc_im_data[0].IN1
tw[1] => trc_im_data[1].IN1
tw[2] => trc_im_data[2].IN1
tw[3] => trc_im_data[3].IN1
tw[4] => trc_im_data[4].IN1
tw[5] => trc_im_data[5].IN1
tw[6] => trc_im_data[6].IN1
tw[7] => trc_im_data[7].IN1
tw[8] => trc_im_data[8].IN1
tw[9] => trc_im_data[9].IN1
tw[10] => trc_im_data[10].IN1
tw[11] => trc_im_data[11].IN1
tw[12] => trc_im_data[12].IN1
tw[13] => trc_im_data[13].IN1
tw[14] => trc_im_data[14].IN1
tw[15] => trc_im_data[15].IN1
tw[16] => trc_im_data[16].IN1
tw[17] => trc_im_data[17].IN1
tw[18] => trc_im_data[18].IN1
tw[19] => trc_im_data[19].IN1
tw[20] => trc_im_data[20].IN1
tw[21] => trc_im_data[21].IN1
tw[22] => trc_im_data[22].IN1
tw[23] => trc_im_data[23].IN1
tw[24] => trc_im_data[24].IN1
tw[25] => trc_im_data[25].IN1
tw[26] => trc_im_data[26].IN1
tw[27] => trc_im_data[27].IN1
tw[28] => trc_im_data[28].IN1
tw[29] => trc_im_data[29].IN1
tw[30] => trc_im_data[30].IN1
tw[31] => trc_im_data[31].IN1
tw[32] => trc_im_data[32].IN1
tw[33] => trc_im_data[33].IN1
tw[34] => trc_im_data[34].IN1
tw[35] => trc_im_data[35].IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component
address_a[0] => address_a[0].IN1
address_a[1] => address_a[1].IN1
address_a[2] => address_a[2].IN1
address_a[3] => address_a[3].IN1
address_a[4] => address_a[4].IN1
address_a[5] => address_a[5].IN1
address_a[6] => address_a[6].IN1
address_b[0] => address_b[0].IN1
address_b[1] => address_b[1].IN1
address_b[2] => address_b[2].IN1
address_b[3] => address_b[3].IN1
address_b[4] => address_b[4].IN1
address_b[5] => address_b[5].IN1
address_b[6] => address_b[6].IN1
clock0 => clock0.IN1
clock1 => clock1.IN1
clocken0 => clocken0.IN1
clocken1 => clocken1.IN1
data_a[0] => data_a[0].IN1
data_a[1] => data_a[1].IN1
data_a[2] => data_a[2].IN1
data_a[3] => data_a[3].IN1
data_a[4] => data_a[4].IN1
data_a[5] => data_a[5].IN1
data_a[6] => data_a[6].IN1
data_a[7] => data_a[7].IN1
data_a[8] => data_a[8].IN1
data_a[9] => data_a[9].IN1
data_a[10] => data_a[10].IN1
data_a[11] => data_a[11].IN1
data_a[12] => data_a[12].IN1
data_a[13] => data_a[13].IN1
data_a[14] => data_a[14].IN1
data_a[15] => data_a[15].IN1
data_a[16] => data_a[16].IN1
data_a[17] => data_a[17].IN1
data_a[18] => data_a[18].IN1
data_a[19] => data_a[19].IN1
data_a[20] => data_a[20].IN1
data_a[21] => data_a[21].IN1
data_a[22] => data_a[22].IN1
data_a[23] => data_a[23].IN1
data_a[24] => data_a[24].IN1
data_a[25] => data_a[25].IN1
data_a[26] => data_a[26].IN1
data_a[27] => data_a[27].IN1
data_a[28] => data_a[28].IN1
data_a[29] => data_a[29].IN1
data_a[30] => data_a[30].IN1
data_a[31] => data_a[31].IN1
data_a[32] => data_a[32].IN1
data_a[33] => data_a[33].IN1
data_a[34] => data_a[34].IN1
data_a[35] => data_a[35].IN1
data_b[0] => data_b[0].IN1
data_b[1] => data_b[1].IN1
data_b[2] => data_b[2].IN1
data_b[3] => data_b[3].IN1
data_b[4] => data_b[4].IN1
data_b[5] => data_b[5].IN1
data_b[6] => data_b[6].IN1
data_b[7] => data_b[7].IN1
data_b[8] => data_b[8].IN1
data_b[9] => data_b[9].IN1
data_b[10] => data_b[10].IN1
data_b[11] => data_b[11].IN1
data_b[12] => data_b[12].IN1
data_b[13] => data_b[13].IN1
data_b[14] => data_b[14].IN1
data_b[15] => data_b[15].IN1
data_b[16] => data_b[16].IN1
data_b[17] => data_b[17].IN1
data_b[18] => data_b[18].IN1
data_b[19] => data_b[19].IN1
data_b[20] => data_b[20].IN1
data_b[21] => data_b[21].IN1
data_b[22] => data_b[22].IN1
data_b[23] => data_b[23].IN1
data_b[24] => data_b[24].IN1
data_b[25] => data_b[25].IN1
data_b[26] => data_b[26].IN1
data_b[27] => data_b[27].IN1
data_b[28] => data_b[28].IN1
data_b[29] => data_b[29].IN1
data_b[30] => data_b[30].IN1
data_b[31] => data_b[31].IN1
data_b[32] => data_b[32].IN1
data_b[33] => data_b[33].IN1
data_b[34] => data_b[34].IN1
data_b[35] => data_b[35].IN1
wren_a => wren_a.IN1
wren_b => wren_b.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
wren_a => altsyncram_0a02:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => altsyncram_0a02:auto_generated.wren_b
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_0a02:auto_generated.data_a[0]
data_a[1] => altsyncram_0a02:auto_generated.data_a[1]
data_a[2] => altsyncram_0a02:auto_generated.data_a[2]
data_a[3] => altsyncram_0a02:auto_generated.data_a[3]
data_a[4] => altsyncram_0a02:auto_generated.data_a[4]
data_a[5] => altsyncram_0a02:auto_generated.data_a[5]
data_a[6] => altsyncram_0a02:auto_generated.data_a[6]
data_a[7] => altsyncram_0a02:auto_generated.data_a[7]
data_a[8] => altsyncram_0a02:auto_generated.data_a[8]
data_a[9] => altsyncram_0a02:auto_generated.data_a[9]
data_a[10] => altsyncram_0a02:auto_generated.data_a[10]
data_a[11] => altsyncram_0a02:auto_generated.data_a[11]
data_a[12] => altsyncram_0a02:auto_generated.data_a[12]
data_a[13] => altsyncram_0a02:auto_generated.data_a[13]
data_a[14] => altsyncram_0a02:auto_generated.data_a[14]
data_a[15] => altsyncram_0a02:auto_generated.data_a[15]
data_a[16] => altsyncram_0a02:auto_generated.data_a[16]
data_a[17] => altsyncram_0a02:auto_generated.data_a[17]
data_a[18] => altsyncram_0a02:auto_generated.data_a[18]
data_a[19] => altsyncram_0a02:auto_generated.data_a[19]
data_a[20] => altsyncram_0a02:auto_generated.data_a[20]
data_a[21] => altsyncram_0a02:auto_generated.data_a[21]
data_a[22] => altsyncram_0a02:auto_generated.data_a[22]
data_a[23] => altsyncram_0a02:auto_generated.data_a[23]
data_a[24] => altsyncram_0a02:auto_generated.data_a[24]
data_a[25] => altsyncram_0a02:auto_generated.data_a[25]
data_a[26] => altsyncram_0a02:auto_generated.data_a[26]
data_a[27] => altsyncram_0a02:auto_generated.data_a[27]
data_a[28] => altsyncram_0a02:auto_generated.data_a[28]
data_a[29] => altsyncram_0a02:auto_generated.data_a[29]
data_a[30] => altsyncram_0a02:auto_generated.data_a[30]
data_a[31] => altsyncram_0a02:auto_generated.data_a[31]
data_a[32] => altsyncram_0a02:auto_generated.data_a[32]
data_a[33] => altsyncram_0a02:auto_generated.data_a[33]
data_a[34] => altsyncram_0a02:auto_generated.data_a[34]
data_a[35] => altsyncram_0a02:auto_generated.data_a[35]
data_b[0] => altsyncram_0a02:auto_generated.data_b[0]
data_b[1] => altsyncram_0a02:auto_generated.data_b[1]
data_b[2] => altsyncram_0a02:auto_generated.data_b[2]
data_b[3] => altsyncram_0a02:auto_generated.data_b[3]
data_b[4] => altsyncram_0a02:auto_generated.data_b[4]
data_b[5] => altsyncram_0a02:auto_generated.data_b[5]
data_b[6] => altsyncram_0a02:auto_generated.data_b[6]
data_b[7] => altsyncram_0a02:auto_generated.data_b[7]
data_b[8] => altsyncram_0a02:auto_generated.data_b[8]
data_b[9] => altsyncram_0a02:auto_generated.data_b[9]
data_b[10] => altsyncram_0a02:auto_generated.data_b[10]
data_b[11] => altsyncram_0a02:auto_generated.data_b[11]
data_b[12] => altsyncram_0a02:auto_generated.data_b[12]
data_b[13] => altsyncram_0a02:auto_generated.data_b[13]
data_b[14] => altsyncram_0a02:auto_generated.data_b[14]
data_b[15] => altsyncram_0a02:auto_generated.data_b[15]
data_b[16] => altsyncram_0a02:auto_generated.data_b[16]
data_b[17] => altsyncram_0a02:auto_generated.data_b[17]
data_b[18] => altsyncram_0a02:auto_generated.data_b[18]
data_b[19] => altsyncram_0a02:auto_generated.data_b[19]
data_b[20] => altsyncram_0a02:auto_generated.data_b[20]
data_b[21] => altsyncram_0a02:auto_generated.data_b[21]
data_b[22] => altsyncram_0a02:auto_generated.data_b[22]
data_b[23] => altsyncram_0a02:auto_generated.data_b[23]
data_b[24] => altsyncram_0a02:auto_generated.data_b[24]
data_b[25] => altsyncram_0a02:auto_generated.data_b[25]
data_b[26] => altsyncram_0a02:auto_generated.data_b[26]
data_b[27] => altsyncram_0a02:auto_generated.data_b[27]
data_b[28] => altsyncram_0a02:auto_generated.data_b[28]
data_b[29] => altsyncram_0a02:auto_generated.data_b[29]
data_b[30] => altsyncram_0a02:auto_generated.data_b[30]
data_b[31] => altsyncram_0a02:auto_generated.data_b[31]
data_b[32] => altsyncram_0a02:auto_generated.data_b[32]
data_b[33] => altsyncram_0a02:auto_generated.data_b[33]
data_b[34] => altsyncram_0a02:auto_generated.data_b[34]
data_b[35] => altsyncram_0a02:auto_generated.data_b[35]
address_a[0] => altsyncram_0a02:auto_generated.address_a[0]
address_a[1] => altsyncram_0a02:auto_generated.address_a[1]
address_a[2] => altsyncram_0a02:auto_generated.address_a[2]
address_a[3] => altsyncram_0a02:auto_generated.address_a[3]
address_a[4] => altsyncram_0a02:auto_generated.address_a[4]
address_a[5] => altsyncram_0a02:auto_generated.address_a[5]
address_a[6] => altsyncram_0a02:auto_generated.address_a[6]
address_b[0] => altsyncram_0a02:auto_generated.address_b[0]
address_b[1] => altsyncram_0a02:auto_generated.address_b[1]
address_b[2] => altsyncram_0a02:auto_generated.address_b[2]
address_b[3] => altsyncram_0a02:auto_generated.address_b[3]
address_b[4] => altsyncram_0a02:auto_generated.address_b[4]
address_b[5] => altsyncram_0a02:auto_generated.address_b[5]
address_b[6] => altsyncram_0a02:auto_generated.address_b[6]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_0a02:auto_generated.clock0
clock1 => altsyncram_0a02:auto_generated.clock1
clocken0 => altsyncram_0a02:auto_generated.clocken0
clocken1 => altsyncram_0a02:auto_generated.clocken1
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[0] => ram_block1a32.PORTAADDR
address_a[0] => ram_block1a33.PORTAADDR
address_a[0] => ram_block1a34.PORTAADDR
address_a[0] => ram_block1a35.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[1] => ram_block1a32.PORTAADDR1
address_a[1] => ram_block1a33.PORTAADDR1
address_a[1] => ram_block1a34.PORTAADDR1
address_a[1] => ram_block1a35.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[2] => ram_block1a32.PORTAADDR2
address_a[2] => ram_block1a33.PORTAADDR2
address_a[2] => ram_block1a34.PORTAADDR2
address_a[2] => ram_block1a35.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[3] => ram_block1a32.PORTAADDR3
address_a[3] => ram_block1a33.PORTAADDR3
address_a[3] => ram_block1a34.PORTAADDR3
address_a[3] => ram_block1a35.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[4] => ram_block1a32.PORTAADDR4
address_a[4] => ram_block1a33.PORTAADDR4
address_a[4] => ram_block1a34.PORTAADDR4
address_a[4] => ram_block1a35.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[5] => ram_block1a32.PORTAADDR5
address_a[5] => ram_block1a33.PORTAADDR5
address_a[5] => ram_block1a34.PORTAADDR5
address_a[5] => ram_block1a35.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[6] => ram_block1a32.PORTAADDR6
address_a[6] => ram_block1a33.PORTAADDR6
address_a[6] => ram_block1a34.PORTAADDR6
address_a[6] => ram_block1a35.PORTAADDR6
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[0] => ram_block1a23.PORTBADDR
address_b[0] => ram_block1a24.PORTBADDR
address_b[0] => ram_block1a25.PORTBADDR
address_b[0] => ram_block1a26.PORTBADDR
address_b[0] => ram_block1a27.PORTBADDR
address_b[0] => ram_block1a28.PORTBADDR
address_b[0] => ram_block1a29.PORTBADDR
address_b[0] => ram_block1a30.PORTBADDR
address_b[0] => ram_block1a31.PORTBADDR
address_b[0] => ram_block1a32.PORTBADDR
address_b[0] => ram_block1a33.PORTBADDR
address_b[0] => ram_block1a34.PORTBADDR
address_b[0] => ram_block1a35.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[1] => ram_block1a23.PORTBADDR1
address_b[1] => ram_block1a24.PORTBADDR1
address_b[1] => ram_block1a25.PORTBADDR1
address_b[1] => ram_block1a26.PORTBADDR1
address_b[1] => ram_block1a27.PORTBADDR1
address_b[1] => ram_block1a28.PORTBADDR1
address_b[1] => ram_block1a29.PORTBADDR1
address_b[1] => ram_block1a30.PORTBADDR1
address_b[1] => ram_block1a31.PORTBADDR1
address_b[1] => ram_block1a32.PORTBADDR1
address_b[1] => ram_block1a33.PORTBADDR1
address_b[1] => ram_block1a34.PORTBADDR1
address_b[1] => ram_block1a35.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[2] => ram_block1a23.PORTBADDR2
address_b[2] => ram_block1a24.PORTBADDR2
address_b[2] => ram_block1a25.PORTBADDR2
address_b[2] => ram_block1a26.PORTBADDR2
address_b[2] => ram_block1a27.PORTBADDR2
address_b[2] => ram_block1a28.PORTBADDR2
address_b[2] => ram_block1a29.PORTBADDR2
address_b[2] => ram_block1a30.PORTBADDR2
address_b[2] => ram_block1a31.PORTBADDR2
address_b[2] => ram_block1a32.PORTBADDR2
address_b[2] => ram_block1a33.PORTBADDR2
address_b[2] => ram_block1a34.PORTBADDR2
address_b[2] => ram_block1a35.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[3] => ram_block1a23.PORTBADDR3
address_b[3] => ram_block1a24.PORTBADDR3
address_b[3] => ram_block1a25.PORTBADDR3
address_b[3] => ram_block1a26.PORTBADDR3
address_b[3] => ram_block1a27.PORTBADDR3
address_b[3] => ram_block1a28.PORTBADDR3
address_b[3] => ram_block1a29.PORTBADDR3
address_b[3] => ram_block1a30.PORTBADDR3
address_b[3] => ram_block1a31.PORTBADDR3
address_b[3] => ram_block1a32.PORTBADDR3
address_b[3] => ram_block1a33.PORTBADDR3
address_b[3] => ram_block1a34.PORTBADDR3
address_b[3] => ram_block1a35.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[4] => ram_block1a24.PORTBADDR4
address_b[4] => ram_block1a25.PORTBADDR4
address_b[4] => ram_block1a26.PORTBADDR4
address_b[4] => ram_block1a27.PORTBADDR4
address_b[4] => ram_block1a28.PORTBADDR4
address_b[4] => ram_block1a29.PORTBADDR4
address_b[4] => ram_block1a30.PORTBADDR4
address_b[4] => ram_block1a31.PORTBADDR4
address_b[4] => ram_block1a32.PORTBADDR4
address_b[4] => ram_block1a33.PORTBADDR4
address_b[4] => ram_block1a34.PORTBADDR4
address_b[4] => ram_block1a35.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[5] => ram_block1a16.PORTBADDR5
address_b[5] => ram_block1a17.PORTBADDR5
address_b[5] => ram_block1a18.PORTBADDR5
address_b[5] => ram_block1a19.PORTBADDR5
address_b[5] => ram_block1a20.PORTBADDR5
address_b[5] => ram_block1a21.PORTBADDR5
address_b[5] => ram_block1a22.PORTBADDR5
address_b[5] => ram_block1a23.PORTBADDR5
address_b[5] => ram_block1a24.PORTBADDR5
address_b[5] => ram_block1a25.PORTBADDR5
address_b[5] => ram_block1a26.PORTBADDR5
address_b[5] => ram_block1a27.PORTBADDR5
address_b[5] => ram_block1a28.PORTBADDR5
address_b[5] => ram_block1a29.PORTBADDR5
address_b[5] => ram_block1a30.PORTBADDR5
address_b[5] => ram_block1a31.PORTBADDR5
address_b[5] => ram_block1a32.PORTBADDR5
address_b[5] => ram_block1a33.PORTBADDR5
address_b[5] => ram_block1a34.PORTBADDR5
address_b[5] => ram_block1a35.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[6] => ram_block1a16.PORTBADDR6
address_b[6] => ram_block1a17.PORTBADDR6
address_b[6] => ram_block1a18.PORTBADDR6
address_b[6] => ram_block1a19.PORTBADDR6
address_b[6] => ram_block1a20.PORTBADDR6
address_b[6] => ram_block1a21.PORTBADDR6
address_b[6] => ram_block1a22.PORTBADDR6
address_b[6] => ram_block1a23.PORTBADDR6
address_b[6] => ram_block1a24.PORTBADDR6
address_b[6] => ram_block1a25.PORTBADDR6
address_b[6] => ram_block1a26.PORTBADDR6
address_b[6] => ram_block1a27.PORTBADDR6
address_b[6] => ram_block1a28.PORTBADDR6
address_b[6] => ram_block1a29.PORTBADDR6
address_b[6] => ram_block1a30.PORTBADDR6
address_b[6] => ram_block1a31.PORTBADDR6
address_b[6] => ram_block1a32.PORTBADDR6
address_b[6] => ram_block1a33.PORTBADDR6
address_b[6] => ram_block1a34.PORTBADDR6
address_b[6] => ram_block1a35.PORTBADDR6
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => ram_block1a32.CLK0
clock0 => ram_block1a33.CLK0
clock0 => ram_block1a34.CLK0
clock0 => ram_block1a35.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
clock1 => ram_block1a16.CLK1
clock1 => ram_block1a17.CLK1
clock1 => ram_block1a18.CLK1
clock1 => ram_block1a19.CLK1
clock1 => ram_block1a20.CLK1
clock1 => ram_block1a21.CLK1
clock1 => ram_block1a22.CLK1
clock1 => ram_block1a23.CLK1
clock1 => ram_block1a24.CLK1
clock1 => ram_block1a25.CLK1
clock1 => ram_block1a26.CLK1
clock1 => ram_block1a27.CLK1
clock1 => ram_block1a28.CLK1
clock1 => ram_block1a29.CLK1
clock1 => ram_block1a30.CLK1
clock1 => ram_block1a31.CLK1
clock1 => ram_block1a32.CLK1
clock1 => ram_block1a33.CLK1
clock1 => ram_block1a34.CLK1
clock1 => ram_block1a35.CLK1
clocken0 => ram_block1a0.ENA0
clocken0 => ram_block1a1.ENA0
clocken0 => ram_block1a2.ENA0
clocken0 => ram_block1a3.ENA0
clocken0 => ram_block1a4.ENA0
clocken0 => ram_block1a5.ENA0
clocken0 => ram_block1a6.ENA0
clocken0 => ram_block1a7.ENA0
clocken0 => ram_block1a8.ENA0
clocken0 => ram_block1a9.ENA0
clocken0 => ram_block1a10.ENA0
clocken0 => ram_block1a11.ENA0
clocken0 => ram_block1a12.ENA0
clocken0 => ram_block1a13.ENA0
clocken0 => ram_block1a14.ENA0
clocken0 => ram_block1a15.ENA0
clocken0 => ram_block1a16.ENA0
clocken0 => ram_block1a17.ENA0
clocken0 => ram_block1a18.ENA0
clocken0 => ram_block1a19.ENA0
clocken0 => ram_block1a20.ENA0
clocken0 => ram_block1a21.ENA0
clocken0 => ram_block1a22.ENA0
clocken0 => ram_block1a23.ENA0
clocken0 => ram_block1a24.ENA0
clocken0 => ram_block1a25.ENA0
clocken0 => ram_block1a26.ENA0
clocken0 => ram_block1a27.ENA0
clocken0 => ram_block1a28.ENA0
clocken0 => ram_block1a29.ENA0
clocken0 => ram_block1a30.ENA0
clocken0 => ram_block1a31.ENA0
clocken0 => ram_block1a32.ENA0
clocken0 => ram_block1a33.ENA0
clocken0 => ram_block1a34.ENA0
clocken0 => ram_block1a35.ENA0
clocken1 => ram_block1a0.ENA1
clocken1 => ram_block1a1.ENA1
clocken1 => ram_block1a2.ENA1
clocken1 => ram_block1a3.ENA1
clocken1 => ram_block1a4.ENA1
clocken1 => ram_block1a5.ENA1
clocken1 => ram_block1a6.ENA1
clocken1 => ram_block1a7.ENA1
clocken1 => ram_block1a8.ENA1
clocken1 => ram_block1a9.ENA1
clocken1 => ram_block1a10.ENA1
clocken1 => ram_block1a11.ENA1
clocken1 => ram_block1a12.ENA1
clocken1 => ram_block1a13.ENA1
clocken1 => ram_block1a14.ENA1
clocken1 => ram_block1a15.ENA1
clocken1 => ram_block1a16.ENA1
clocken1 => ram_block1a17.ENA1
clocken1 => ram_block1a18.ENA1
clocken1 => ram_block1a19.ENA1
clocken1 => ram_block1a20.ENA1
clocken1 => ram_block1a21.ENA1
clocken1 => ram_block1a22.ENA1
clocken1 => ram_block1a23.ENA1
clocken1 => ram_block1a24.ENA1
clocken1 => ram_block1a25.ENA1
clocken1 => ram_block1a26.ENA1
clocken1 => ram_block1a27.ENA1
clocken1 => ram_block1a28.ENA1
clocken1 => ram_block1a29.ENA1
clocken1 => ram_block1a30.ENA1
clocken1 => ram_block1a31.ENA1
clocken1 => ram_block1a32.ENA1
clocken1 => ram_block1a33.ENA1
clocken1 => ram_block1a34.ENA1
clocken1 => ram_block1a35.ENA1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
data_a[24] => ram_block1a24.PORTADATAIN
data_a[25] => ram_block1a25.PORTADATAIN
data_a[26] => ram_block1a26.PORTADATAIN
data_a[27] => ram_block1a27.PORTADATAIN
data_a[28] => ram_block1a28.PORTADATAIN
data_a[29] => ram_block1a29.PORTADATAIN
data_a[30] => ram_block1a30.PORTADATAIN
data_a[31] => ram_block1a31.PORTADATAIN
data_a[32] => ram_block1a32.PORTADATAIN
data_a[33] => ram_block1a33.PORTADATAIN
data_a[34] => ram_block1a34.PORTADATAIN
data_a[35] => ram_block1a35.PORTADATAIN
data_b[0] => ram_block1a0.PORTBDATAIN
data_b[1] => ram_block1a1.PORTBDATAIN
data_b[2] => ram_block1a2.PORTBDATAIN
data_b[3] => ram_block1a3.PORTBDATAIN
data_b[4] => ram_block1a4.PORTBDATAIN
data_b[5] => ram_block1a5.PORTBDATAIN
data_b[6] => ram_block1a6.PORTBDATAIN
data_b[7] => ram_block1a7.PORTBDATAIN
data_b[8] => ram_block1a8.PORTBDATAIN
data_b[9] => ram_block1a9.PORTBDATAIN
data_b[10] => ram_block1a10.PORTBDATAIN
data_b[11] => ram_block1a11.PORTBDATAIN
data_b[12] => ram_block1a12.PORTBDATAIN
data_b[13] => ram_block1a13.PORTBDATAIN
data_b[14] => ram_block1a14.PORTBDATAIN
data_b[15] => ram_block1a15.PORTBDATAIN
data_b[16] => ram_block1a16.PORTBDATAIN
data_b[17] => ram_block1a17.PORTBDATAIN
data_b[18] => ram_block1a18.PORTBDATAIN
data_b[19] => ram_block1a19.PORTBDATAIN
data_b[20] => ram_block1a20.PORTBDATAIN
data_b[21] => ram_block1a21.PORTBDATAIN
data_b[22] => ram_block1a22.PORTBDATAIN
data_b[23] => ram_block1a23.PORTBDATAIN
data_b[24] => ram_block1a24.PORTBDATAIN
data_b[25] => ram_block1a25.PORTBDATAIN
data_b[26] => ram_block1a26.PORTBDATAIN
data_b[27] => ram_block1a27.PORTBDATAIN
data_b[28] => ram_block1a28.PORTBDATAIN
data_b[29] => ram_block1a29.PORTBDATAIN
data_b[30] => ram_block1a30.PORTBDATAIN
data_b[31] => ram_block1a31.PORTBDATAIN
data_b[32] => ram_block1a32.PORTBDATAIN
data_b[33] => ram_block1a33.PORTBDATAIN
data_b[34] => ram_block1a34.PORTBDATAIN
data_b[35] => ram_block1a35.PORTBDATAIN
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a23.PORTAWE
wren_a => ram_block1a24.PORTAWE
wren_a => ram_block1a25.PORTAWE
wren_a => ram_block1a26.PORTAWE
wren_a => ram_block1a27.PORTAWE
wren_a => ram_block1a28.PORTAWE
wren_a => ram_block1a29.PORTAWE
wren_a => ram_block1a30.PORTAWE
wren_a => ram_block1a31.PORTAWE
wren_a => ram_block1a32.PORTAWE
wren_a => ram_block1a33.PORTAWE
wren_a => ram_block1a34.PORTAWE
wren_a => ram_block1a35.PORTAWE
wren_b => ram_block1a0.PORTBWE
wren_b => ram_block1a1.PORTBWE
wren_b => ram_block1a2.PORTBWE
wren_b => ram_block1a3.PORTBWE
wren_b => ram_block1a4.PORTBWE
wren_b => ram_block1a5.PORTBWE
wren_b => ram_block1a6.PORTBWE
wren_b => ram_block1a7.PORTBWE
wren_b => ram_block1a8.PORTBWE
wren_b => ram_block1a9.PORTBWE
wren_b => ram_block1a10.PORTBWE
wren_b => ram_block1a11.PORTBWE
wren_b => ram_block1a12.PORTBWE
wren_b => ram_block1a13.PORTBWE
wren_b => ram_block1a14.PORTBWE
wren_b => ram_block1a15.PORTBWE
wren_b => ram_block1a16.PORTBWE
wren_b => ram_block1a17.PORTBWE
wren_b => ram_block1a18.PORTBWE
wren_b => ram_block1a19.PORTBWE
wren_b => ram_block1a20.PORTBWE
wren_b => ram_block1a21.PORTBWE
wren_b => ram_block1a22.PORTBWE
wren_b => ram_block1a23.PORTBWE
wren_b => ram_block1a24.PORTBWE
wren_b => ram_block1a25.PORTBWE
wren_b => ram_block1a26.PORTBWE
wren_b => ram_block1a27.PORTBWE
wren_b => ram_block1a28.PORTBWE
wren_b => ram_block1a29.PORTBWE
wren_b => ram_block1a30.PORTBWE
wren_b => ram_block1a31.PORTBWE
wren_b => ram_block1a32.PORTBWE
wren_b => ram_block1a33.PORTBWE
wren_b => ram_block1a34.PORTBWE
wren_b => ram_block1a35.PORTBWE


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper
MonDReg[0] => MonDReg[0].IN1
MonDReg[1] => MonDReg[1].IN1
MonDReg[2] => MonDReg[2].IN1
MonDReg[3] => MonDReg[3].IN1
MonDReg[4] => MonDReg[4].IN1
MonDReg[5] => MonDReg[5].IN1
MonDReg[6] => MonDReg[6].IN1
MonDReg[7] => MonDReg[7].IN1
MonDReg[8] => MonDReg[8].IN1
MonDReg[9] => MonDReg[9].IN1
MonDReg[10] => MonDReg[10].IN1
MonDReg[11] => MonDReg[11].IN1
MonDReg[12] => MonDReg[12].IN1
MonDReg[13] => MonDReg[13].IN1
MonDReg[14] => MonDReg[14].IN1
MonDReg[15] => MonDReg[15].IN1
MonDReg[16] => MonDReg[16].IN1
MonDReg[17] => MonDReg[17].IN1
MonDReg[18] => MonDReg[18].IN1
MonDReg[19] => MonDReg[19].IN1
MonDReg[20] => MonDReg[20].IN1
MonDReg[21] => MonDReg[21].IN1
MonDReg[22] => MonDReg[22].IN1
MonDReg[23] => MonDReg[23].IN1
MonDReg[24] => MonDReg[24].IN1
MonDReg[25] => MonDReg[25].IN1
MonDReg[26] => MonDReg[26].IN1
MonDReg[27] => MonDReg[27].IN1
MonDReg[28] => MonDReg[28].IN1
MonDReg[29] => MonDReg[29].IN1
MonDReg[30] => MonDReg[30].IN1
MonDReg[31] => MonDReg[31].IN1
break_readreg[0] => break_readreg[0].IN1
break_readreg[1] => break_readreg[1].IN1
break_readreg[2] => break_readreg[2].IN1
break_readreg[3] => break_readreg[3].IN1
break_readreg[4] => break_readreg[4].IN1
break_readreg[5] => break_readreg[5].IN1
break_readreg[6] => break_readreg[6].IN1
break_readreg[7] => break_readreg[7].IN1
break_readreg[8] => break_readreg[8].IN1
break_readreg[9] => break_readreg[9].IN1
break_readreg[10] => break_readreg[10].IN1
break_readreg[11] => break_readreg[11].IN1
break_readreg[12] => break_readreg[12].IN1
break_readreg[13] => break_readreg[13].IN1
break_readreg[14] => break_readreg[14].IN1
break_readreg[15] => break_readreg[15].IN1
break_readreg[16] => break_readreg[16].IN1
break_readreg[17] => break_readreg[17].IN1
break_readreg[18] => break_readreg[18].IN1
break_readreg[19] => break_readreg[19].IN1
break_readreg[20] => break_readreg[20].IN1
break_readreg[21] => break_readreg[21].IN1
break_readreg[22] => break_readreg[22].IN1
break_readreg[23] => break_readreg[23].IN1
break_readreg[24] => break_readreg[24].IN1
break_readreg[25] => break_readreg[25].IN1
break_readreg[26] => break_readreg[26].IN1
break_readreg[27] => break_readreg[27].IN1
break_readreg[28] => break_readreg[28].IN1
break_readreg[29] => break_readreg[29].IN1
break_readreg[30] => break_readreg[30].IN1
break_readreg[31] => break_readreg[31].IN1
clk => clk.IN1
dbrk_hit0_latch => dbrk_hit0_latch.IN1
dbrk_hit1_latch => dbrk_hit1_latch.IN1
dbrk_hit2_latch => dbrk_hit2_latch.IN1
dbrk_hit3_latch => dbrk_hit3_latch.IN1
debugack => debugack.IN1
monitor_error => monitor_error.IN1
monitor_ready => monitor_ready.IN1
reset_n => reset_n.IN1
resetlatch => resetlatch.IN1
tracemem_on => tracemem_on.IN1
tracemem_trcdata[0] => tracemem_trcdata[0].IN1
tracemem_trcdata[1] => tracemem_trcdata[1].IN1
tracemem_trcdata[2] => tracemem_trcdata[2].IN1
tracemem_trcdata[3] => tracemem_trcdata[3].IN1
tracemem_trcdata[4] => tracemem_trcdata[4].IN1
tracemem_trcdata[5] => tracemem_trcdata[5].IN1
tracemem_trcdata[6] => tracemem_trcdata[6].IN1
tracemem_trcdata[7] => tracemem_trcdata[7].IN1
tracemem_trcdata[8] => tracemem_trcdata[8].IN1
tracemem_trcdata[9] => tracemem_trcdata[9].IN1
tracemem_trcdata[10] => tracemem_trcdata[10].IN1
tracemem_trcdata[11] => tracemem_trcdata[11].IN1
tracemem_trcdata[12] => tracemem_trcdata[12].IN1
tracemem_trcdata[13] => tracemem_trcdata[13].IN1
tracemem_trcdata[14] => tracemem_trcdata[14].IN1
tracemem_trcdata[15] => tracemem_trcdata[15].IN1
tracemem_trcdata[16] => tracemem_trcdata[16].IN1
tracemem_trcdata[17] => tracemem_trcdata[17].IN1
tracemem_trcdata[18] => tracemem_trcdata[18].IN1
tracemem_trcdata[19] => tracemem_trcdata[19].IN1
tracemem_trcdata[20] => tracemem_trcdata[20].IN1
tracemem_trcdata[21] => tracemem_trcdata[21].IN1
tracemem_trcdata[22] => tracemem_trcdata[22].IN1
tracemem_trcdata[23] => tracemem_trcdata[23].IN1
tracemem_trcdata[24] => tracemem_trcdata[24].IN1
tracemem_trcdata[25] => tracemem_trcdata[25].IN1
tracemem_trcdata[26] => tracemem_trcdata[26].IN1
tracemem_trcdata[27] => tracemem_trcdata[27].IN1
tracemem_trcdata[28] => tracemem_trcdata[28].IN1
tracemem_trcdata[29] => tracemem_trcdata[29].IN1
tracemem_trcdata[30] => tracemem_trcdata[30].IN1
tracemem_trcdata[31] => tracemem_trcdata[31].IN1
tracemem_trcdata[32] => tracemem_trcdata[32].IN1
tracemem_trcdata[33] => tracemem_trcdata[33].IN1
tracemem_trcdata[34] => tracemem_trcdata[34].IN1
tracemem_trcdata[35] => tracemem_trcdata[35].IN1
tracemem_tw => tracemem_tw.IN1
trc_im_addr[0] => trc_im_addr[0].IN1
trc_im_addr[1] => trc_im_addr[1].IN1
trc_im_addr[2] => trc_im_addr[2].IN1
trc_im_addr[3] => trc_im_addr[3].IN1
trc_im_addr[4] => trc_im_addr[4].IN1
trc_im_addr[5] => trc_im_addr[5].IN1
trc_im_addr[6] => trc_im_addr[6].IN1
trc_on => trc_on.IN1
trc_wrap => trc_wrap.IN1
trigbrktype => trigbrktype.IN1
trigger_state_1 => trigger_state_1.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck
MonDReg[0] => Mux36.IN0
MonDReg[1] => Mux35.IN0
MonDReg[2] => Mux34.IN0
MonDReg[3] => Mux33.IN0
MonDReg[4] => Mux32.IN0
MonDReg[5] => Mux31.IN0
MonDReg[6] => Mux30.IN0
MonDReg[7] => Mux29.IN0
MonDReg[8] => Mux28.IN1
MonDReg[9] => Mux27.IN1
MonDReg[10] => Mux26.IN1
MonDReg[11] => Mux25.IN1
MonDReg[12] => Mux24.IN1
MonDReg[13] => Mux23.IN1
MonDReg[14] => Mux22.IN1
MonDReg[15] => Mux21.IN1
MonDReg[16] => Mux20.IN1
MonDReg[17] => Mux19.IN1
MonDReg[18] => Mux18.IN1
MonDReg[19] => Mux17.IN1
MonDReg[20] => Mux16.IN1
MonDReg[21] => Mux15.IN1
MonDReg[22] => Mux14.IN1
MonDReg[23] => Mux13.IN1
MonDReg[24] => Mux12.IN1
MonDReg[25] => Mux11.IN1
MonDReg[26] => Mux10.IN1
MonDReg[27] => Mux9.IN1
MonDReg[28] => Mux8.IN1
MonDReg[29] => Mux7.IN1
MonDReg[30] => Mux6.IN1
MonDReg[31] => Mux5.IN1
break_readreg[0] => Mux36.IN1
break_readreg[1] => Mux35.IN1
break_readreg[2] => Mux34.IN1
break_readreg[3] => Mux33.IN1
break_readreg[4] => Mux32.IN1
break_readreg[5] => Mux31.IN1
break_readreg[6] => Mux30.IN1
break_readreg[7] => Mux29.IN1
break_readreg[8] => Mux28.IN2
break_readreg[9] => Mux27.IN2
break_readreg[10] => Mux26.IN2
break_readreg[11] => Mux25.IN2
break_readreg[12] => Mux24.IN2
break_readreg[13] => Mux23.IN2
break_readreg[14] => Mux22.IN2
break_readreg[15] => Mux21.IN2
break_readreg[16] => Mux20.IN2
break_readreg[17] => Mux19.IN2
break_readreg[18] => Mux18.IN2
break_readreg[19] => Mux17.IN2
break_readreg[20] => Mux16.IN2
break_readreg[21] => Mux15.IN2
break_readreg[22] => Mux14.IN2
break_readreg[23] => Mux13.IN2
break_readreg[24] => Mux12.IN2
break_readreg[25] => Mux11.IN2
break_readreg[26] => Mux10.IN2
break_readreg[27] => Mux9.IN2
break_readreg[28] => Mux8.IN2
break_readreg[29] => Mux7.IN2
break_readreg[30] => Mux6.IN2
break_readreg[31] => Mux5.IN2
dbrk_hit0_latch => Mux4.IN1
dbrk_hit1_latch => Mux3.IN1
dbrk_hit2_latch => Mux2.IN1
dbrk_hit3_latch => Mux1.IN2
debugack => debugack.IN1
ir_in[0] => Mux0.IN3
ir_in[0] => Mux1.IN4
ir_in[0] => Mux2.IN3
ir_in[0] => Mux3.IN3
ir_in[0] => Mux4.IN3
ir_in[0] => Mux5.IN4
ir_in[0] => Mux6.IN4
ir_in[0] => Mux7.IN4
ir_in[0] => Mux8.IN4
ir_in[0] => Mux9.IN4
ir_in[0] => Mux10.IN4
ir_in[0] => Mux11.IN4
ir_in[0] => Mux12.IN4
ir_in[0] => Mux13.IN4
ir_in[0] => Mux14.IN4
ir_in[0] => Mux15.IN4
ir_in[0] => Mux16.IN4
ir_in[0] => Mux17.IN4
ir_in[0] => Mux18.IN4
ir_in[0] => Mux19.IN4
ir_in[0] => Mux20.IN4
ir_in[0] => Mux21.IN4
ir_in[0] => Mux22.IN4
ir_in[0] => Mux23.IN4
ir_in[0] => Mux24.IN4
ir_in[0] => Mux25.IN4
ir_in[0] => Mux26.IN4
ir_in[0] => Mux27.IN4
ir_in[0] => Mux28.IN4
ir_in[0] => Mux29.IN3
ir_in[0] => Mux30.IN3
ir_in[0] => Mux31.IN3
ir_in[0] => Mux32.IN3
ir_in[0] => Mux33.IN3
ir_in[0] => Mux34.IN3
ir_in[0] => Mux35.IN3
ir_in[0] => Mux36.IN3
ir_in[0] => Mux37.IN1
ir_in[0] => Decoder0.IN1
ir_in[1] => Mux0.IN2
ir_in[1] => Mux1.IN3
ir_in[1] => Mux2.IN2
ir_in[1] => Mux3.IN2
ir_in[1] => Mux4.IN2
ir_in[1] => Mux5.IN3
ir_in[1] => Mux6.IN3
ir_in[1] => Mux7.IN3
ir_in[1] => Mux8.IN3
ir_in[1] => Mux9.IN3
ir_in[1] => Mux10.IN3
ir_in[1] => Mux11.IN3
ir_in[1] => Mux12.IN3
ir_in[1] => Mux13.IN3
ir_in[1] => Mux14.IN3
ir_in[1] => Mux15.IN3
ir_in[1] => Mux16.IN3
ir_in[1] => Mux17.IN3
ir_in[1] => Mux18.IN3
ir_in[1] => Mux19.IN3
ir_in[1] => Mux20.IN3
ir_in[1] => Mux21.IN3
ir_in[1] => Mux22.IN3
ir_in[1] => Mux23.IN3
ir_in[1] => Mux24.IN3
ir_in[1] => Mux25.IN3
ir_in[1] => Mux26.IN3
ir_in[1] => Mux27.IN3
ir_in[1] => Mux28.IN3
ir_in[1] => Mux29.IN2
ir_in[1] => Mux30.IN2
ir_in[1] => Mux31.IN2
ir_in[1] => Mux32.IN2
ir_in[1] => Mux33.IN2
ir_in[1] => Mux34.IN2
ir_in[1] => Mux35.IN2
ir_in[1] => Mux36.IN2
ir_in[1] => Mux37.IN0
ir_in[1] => Decoder0.IN0
jtag_state_rti => st_ready_test_idle.DATAIN
monitor_error => Mux3.IN4
monitor_ready => monitor_ready.IN1
reset_n => ~NO_FANOUT~
resetlatch => Mux4.IN4
tck => tck.IN2
tdi => sr.DATAB
tdi => sr.DATAB
tdi => sr.DATAB
tdi => sr.DATAB
tdi => sr.DATAB
tdi => sr.DATAB
tracemem_on => Mux1.IN5
tracemem_trcdata[0] => Mux37.IN2
tracemem_trcdata[1] => Mux36.IN4
tracemem_trcdata[2] => Mux35.IN4
tracemem_trcdata[3] => Mux34.IN4
tracemem_trcdata[4] => Mux33.IN4
tracemem_trcdata[5] => Mux32.IN4
tracemem_trcdata[6] => Mux31.IN4
tracemem_trcdata[7] => Mux30.IN4
tracemem_trcdata[8] => Mux29.IN4
tracemem_trcdata[9] => Mux28.IN5
tracemem_trcdata[10] => Mux27.IN5
tracemem_trcdata[11] => Mux26.IN5
tracemem_trcdata[12] => Mux25.IN5
tracemem_trcdata[13] => Mux24.IN5
tracemem_trcdata[14] => Mux23.IN5
tracemem_trcdata[15] => Mux22.IN5
tracemem_trcdata[16] => Mux21.IN5
tracemem_trcdata[17] => Mux20.IN5
tracemem_trcdata[18] => Mux19.IN5
tracemem_trcdata[19] => Mux18.IN5
tracemem_trcdata[20] => Mux17.IN5
tracemem_trcdata[21] => Mux16.IN5
tracemem_trcdata[22] => Mux15.IN5
tracemem_trcdata[23] => Mux14.IN5
tracemem_trcdata[24] => Mux13.IN5
tracemem_trcdata[25] => Mux12.IN5
tracemem_trcdata[26] => Mux11.IN5
tracemem_trcdata[27] => Mux10.IN5
tracemem_trcdata[28] => Mux9.IN5
tracemem_trcdata[29] => Mux8.IN5
tracemem_trcdata[30] => Mux7.IN5
tracemem_trcdata[31] => Mux6.IN5
tracemem_trcdata[32] => Mux5.IN5
tracemem_trcdata[33] => Mux4.IN5
tracemem_trcdata[34] => Mux3.IN5
tracemem_trcdata[35] => Mux2.IN4
tracemem_tw => Mux0.IN4
trc_im_addr[0] => Mux35.IN5
trc_im_addr[1] => Mux34.IN5
trc_im_addr[2] => Mux33.IN5
trc_im_addr[3] => Mux32.IN5
trc_im_addr[4] => Mux31.IN5
trc_im_addr[5] => Mux30.IN5
trc_im_addr[6] => Mux29.IN5
trc_on => Mux37.IN3
trc_wrap => Mux36.IN5
trigbrktype => Mux37.IN4
trigger_state_1 => Mux0.IN5
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_cdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_sdr => sr.OUTPUTSELECT
vs_uir => DRsize.OUTPUTSELECT
vs_uir => DRsize.OUTPUTSELECT
vs_uir => DRsize.OUTPUTSELECT
vs_uir => DRsize.OUTPUTSELECT
vs_uir => DRsize.OUTPUTSELECT
vs_uir => DRsize.OUTPUTSELECT


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
clk => dreg[0].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
clk => dreg[0].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk
clk => clk.IN2
ir_in[0] => ir[0].DATAIN
ir_in[1] => ir[1].DATAIN
sr[0] => jdo[0]~reg0.DATAIN
sr[1] => jdo[1]~reg0.DATAIN
sr[2] => jdo[2]~reg0.DATAIN
sr[3] => jdo[3]~reg0.DATAIN
sr[4] => jdo[4]~reg0.DATAIN
sr[5] => jdo[5]~reg0.DATAIN
sr[6] => jdo[6]~reg0.DATAIN
sr[7] => jdo[7]~reg0.DATAIN
sr[8] => jdo[8]~reg0.DATAIN
sr[9] => jdo[9]~reg0.DATAIN
sr[10] => jdo[10]~reg0.DATAIN
sr[11] => jdo[11]~reg0.DATAIN
sr[12] => jdo[12]~reg0.DATAIN
sr[13] => jdo[13]~reg0.DATAIN
sr[14] => jdo[14]~reg0.DATAIN
sr[15] => jdo[15]~reg0.DATAIN
sr[16] => jdo[16]~reg0.DATAIN
sr[17] => jdo[17]~reg0.DATAIN
sr[18] => jdo[18]~reg0.DATAIN
sr[19] => jdo[19]~reg0.DATAIN
sr[20] => jdo[20]~reg0.DATAIN
sr[21] => jdo[21]~reg0.DATAIN
sr[22] => jdo[22]~reg0.DATAIN
sr[23] => jdo[23]~reg0.DATAIN
sr[24] => jdo[24]~reg0.DATAIN
sr[25] => jdo[25]~reg0.DATAIN
sr[26] => jdo[26]~reg0.DATAIN
sr[27] => jdo[27]~reg0.DATAIN
sr[28] => jdo[28]~reg0.DATAIN
sr[29] => jdo[29]~reg0.DATAIN
sr[30] => jdo[30]~reg0.DATAIN
sr[31] => jdo[31]~reg0.DATAIN
sr[32] => jdo[32]~reg0.DATAIN
sr[33] => jdo[33]~reg0.DATAIN
sr[34] => jdo[34]~reg0.DATAIN
sr[35] => jdo[35]~reg0.DATAIN
sr[36] => jdo[36]~reg0.DATAIN
sr[37] => jdo[37]~reg0.DATAIN
vs_udr => vs_udr.IN1
vs_uir => vs_uir.IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
clk => dreg[0].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
clk => dreg[0].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy
tdo => tdo.IN1
ir_out[0] => ir_out[0].IN1
ir_out[1] => ir_out[1].IN1


|LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst
usr_tdo => tdo.DATAIN
usr_ir_out[0] => ir_out[0].DATAIN
usr_ir_out[1] => ir_out[1].DATAIN
raw_tck => usr_tck.DATAIN
raw_tms => usr_tms.DATAIN
tdi => usr_tdi.DATAIN
jtag_state_tlr => usr_jtag_state_tlr.DATAIN
jtag_state_rti => usr_jtag_state_rti.DATAIN
jtag_state_sdrs => usr_jtag_state_sdrs.DATAIN
jtag_state_cdr => virtual_state_cdr.IN1
jtag_state_cdr => usr_virtual_state_cir.DATAIN
jtag_state_cdr => usr_jtag_state_cdr.DATAIN
jtag_state_sdr => virtual_state_sdr.IN1
jtag_state_sdr => usr_jtag_state_sdr.DATAIN
jtag_state_e1dr => virtual_state_e1dr.IN1
jtag_state_e1dr => usr_jtag_state_e1dr.DATAIN
jtag_state_pdr => virtual_state_pdr.IN1
jtag_state_pdr => usr_jtag_state_pdr.DATAIN
jtag_state_e2dr => virtual_state_e2dr.IN1
jtag_state_e2dr => usr_jtag_state_e2dr.DATAIN
jtag_state_udr => virtual_state_udr.IN1
jtag_state_udr => virtual_state_uir.IN1
jtag_state_udr => usr_jtag_state_udr.DATAIN
jtag_state_sirs => usr_jtag_state_sirs.DATAIN
jtag_state_cir => usr_jtag_state_cir.DATAIN
jtag_state_sir => usr_jtag_state_sir.DATAIN
jtag_state_e1ir => usr_jtag_state_e1ir.DATAIN
jtag_state_pir => usr_jtag_state_pir.DATAIN
jtag_state_e2ir => usr_jtag_state_e2ir.DATAIN
jtag_state_uir => usr_jtag_state_uir.DATAIN
usr1 => virtual_ir_scan.IN0
usr1 => virtual_dr_scan.IN0
clr => ~NO_FANOUT~
ena => virtual_dr_scan.IN1
ena => virtual_ir_scan.IN1
ir_in[0] => usr_ir_in[0].DATAIN
ir_in[1] => usr_ir_in[1].DATAIN


|LED_hello_world|CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port
clk => d1_epcs_epcs_control_port_end_xfer~reg0.CLK
clk => epcs_epcs_control_port_reg_firsttransfer.CLK
clk => epcs_epcs_control_port_arb_addend[0].CLK
clk => epcs_epcs_control_port_arb_addend[1].CLK
clk => epcs_epcs_control_port_saved_chosen_master_vector[0].CLK
clk => epcs_epcs_control_port_saved_chosen_master_vector[1].CLK
clk => last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port.CLK
clk => last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port.CLK
clk => epcs_epcs_control_port_slavearbiterlockenable.CLK
clk => epcs_epcs_control_port_arb_share_counter[0].CLK
clk => epcs_epcs_control_port_arb_share_counter[1].CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[3] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[4] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[5] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[6] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[7] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[8] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[9] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[10] => epcs_epcs_control_port_address.DATAB
cpu_data_master_address_to_slave[11] => Equal0.IN15
cpu_data_master_address_to_slave[12] => Equal0.IN14
cpu_data_master_address_to_slave[13] => Equal0.IN13
cpu_data_master_address_to_slave[14] => Equal0.IN12
cpu_data_master_address_to_slave[15] => Equal0.IN11
cpu_data_master_address_to_slave[16] => Equal0.IN10
cpu_data_master_address_to_slave[17] => Equal0.IN9
cpu_data_master_address_to_slave[18] => Equal0.IN8
cpu_data_master_address_to_slave[19] => Equal0.IN7
cpu_data_master_address_to_slave[20] => Equal0.IN6
cpu_data_master_address_to_slave[21] => Equal0.IN5
cpu_data_master_address_to_slave[22] => Equal0.IN4
cpu_data_master_address_to_slave[23] => Equal0.IN3
cpu_data_master_address_to_slave[24] => Equal0.IN2
cpu_data_master_address_to_slave[25] => Equal0.IN1
cpu_data_master_address_to_slave[26] => Equal0.IN0
cpu_data_master_read => cpu_data_master_requests_epcs_epcs_control_port.IN0
cpu_data_master_read => epcs_epcs_control_port_in_a_read_cycle.IN1
cpu_data_master_write => cpu_data_master_requests_epcs_epcs_control_port.IN1
cpu_data_master_write => in_a_write_cycle.IN1
cpu_data_master_writedata[0] => epcs_epcs_control_port_writedata[0].DATAIN
cpu_data_master_writedata[1] => epcs_epcs_control_port_writedata[1].DATAIN
cpu_data_master_writedata[2] => epcs_epcs_control_port_writedata[2].DATAIN
cpu_data_master_writedata[3] => epcs_epcs_control_port_writedata[3].DATAIN
cpu_data_master_writedata[4] => epcs_epcs_control_port_writedata[4].DATAIN
cpu_data_master_writedata[5] => epcs_epcs_control_port_writedata[5].DATAIN
cpu_data_master_writedata[6] => epcs_epcs_control_port_writedata[6].DATAIN
cpu_data_master_writedata[7] => epcs_epcs_control_port_writedata[7].DATAIN
cpu_data_master_writedata[8] => epcs_epcs_control_port_writedata[8].DATAIN
cpu_data_master_writedata[9] => epcs_epcs_control_port_writedata[9].DATAIN
cpu_data_master_writedata[10] => epcs_epcs_control_port_writedata[10].DATAIN
cpu_data_master_writedata[11] => epcs_epcs_control_port_writedata[11].DATAIN
cpu_data_master_writedata[12] => epcs_epcs_control_port_writedata[12].DATAIN
cpu_data_master_writedata[13] => epcs_epcs_control_port_writedata[13].DATAIN
cpu_data_master_writedata[14] => epcs_epcs_control_port_writedata[14].DATAIN
cpu_data_master_writedata[15] => epcs_epcs_control_port_writedata[15].DATAIN
cpu_data_master_writedata[16] => epcs_epcs_control_port_writedata[16].DATAIN
cpu_data_master_writedata[17] => epcs_epcs_control_port_writedata[17].DATAIN
cpu_data_master_writedata[18] => epcs_epcs_control_port_writedata[18].DATAIN
cpu_data_master_writedata[19] => epcs_epcs_control_port_writedata[19].DATAIN
cpu_data_master_writedata[20] => epcs_epcs_control_port_writedata[20].DATAIN
cpu_data_master_writedata[21] => epcs_epcs_control_port_writedata[21].DATAIN
cpu_data_master_writedata[22] => epcs_epcs_control_port_writedata[22].DATAIN
cpu_data_master_writedata[23] => epcs_epcs_control_port_writedata[23].DATAIN
cpu_data_master_writedata[24] => epcs_epcs_control_port_writedata[24].DATAIN
cpu_data_master_writedata[25] => epcs_epcs_control_port_writedata[25].DATAIN
cpu_data_master_writedata[26] => epcs_epcs_control_port_writedata[26].DATAIN
cpu_data_master_writedata[27] => epcs_epcs_control_port_writedata[27].DATAIN
cpu_data_master_writedata[28] => epcs_epcs_control_port_writedata[28].DATAIN
cpu_data_master_writedata[29] => epcs_epcs_control_port_writedata[29].DATAIN
cpu_data_master_writedata[30] => epcs_epcs_control_port_writedata[30].DATAIN
cpu_data_master_writedata[31] => epcs_epcs_control_port_writedata[31].DATAIN
cpu_instruction_master_address_to_slave[0] => ~NO_FANOUT~
cpu_instruction_master_address_to_slave[1] => ~NO_FANOUT~
cpu_instruction_master_address_to_slave[2] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[3] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[4] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[5] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[6] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[7] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[8] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[9] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[10] => epcs_epcs_control_port_address.DATAA
cpu_instruction_master_address_to_slave[11] => Equal1.IN15
cpu_instruction_master_address_to_slave[12] => Equal1.IN14
cpu_instruction_master_address_to_slave[13] => Equal1.IN13
cpu_instruction_master_address_to_slave[14] => Equal1.IN12
cpu_instruction_master_address_to_slave[15] => Equal1.IN11
cpu_instruction_master_address_to_slave[16] => Equal1.IN10
cpu_instruction_master_address_to_slave[17] => Equal1.IN9
cpu_instruction_master_address_to_slave[18] => Equal1.IN8
cpu_instruction_master_address_to_slave[19] => Equal1.IN7
cpu_instruction_master_address_to_slave[20] => Equal1.IN6
cpu_instruction_master_address_to_slave[21] => Equal1.IN5
cpu_instruction_master_address_to_slave[22] => Equal1.IN4
cpu_instruction_master_address_to_slave[23] => Equal1.IN3
cpu_instruction_master_address_to_slave[24] => Equal1.IN2
cpu_instruction_master_address_to_slave[25] => Equal1.IN1
cpu_instruction_master_address_to_slave[26] => Equal1.IN0
cpu_instruction_master_latency_counter => cpu_instruction_master_qualified_request_epcs_epcs_control_port.IN0
cpu_instruction_master_read => cpu_instruction_master_requests_epcs_epcs_control_port.IN1
cpu_instruction_master_read => cpu_instruction_master_requests_epcs_epcs_control_port.IN1
cpu_instruction_master_read => cpu_instruction_master_qualified_request_epcs_epcs_control_port.IN1
cpu_instruction_master_read => epcs_epcs_control_port_in_a_read_cycle.IN1
cpu_instruction_master_read_data_valid_sdram_s1_shift_register => cpu_instruction_master_qualified_request_epcs_epcs_control_port.IN1
epcs_epcs_control_port_dataavailable => epcs_epcs_control_port_dataavailable_from_sa.DATAIN
epcs_epcs_control_port_endofpacket => epcs_epcs_control_port_endofpacket_from_sa.DATAIN
epcs_epcs_control_port_irq => epcs_epcs_control_port_irq_from_sa.DATAIN
epcs_epcs_control_port_readdata[0] => epcs_epcs_control_port_readdata_from_sa[0].DATAIN
epcs_epcs_control_port_readdata[1] => epcs_epcs_control_port_readdata_from_sa[1].DATAIN
epcs_epcs_control_port_readdata[2] => epcs_epcs_control_port_readdata_from_sa[2].DATAIN
epcs_epcs_control_port_readdata[3] => epcs_epcs_control_port_readdata_from_sa[3].DATAIN
epcs_epcs_control_port_readdata[4] => epcs_epcs_control_port_readdata_from_sa[4].DATAIN
epcs_epcs_control_port_readdata[5] => epcs_epcs_control_port_readdata_from_sa[5].DATAIN
epcs_epcs_control_port_readdata[6] => epcs_epcs_control_port_readdata_from_sa[6].DATAIN
epcs_epcs_control_port_readdata[7] => epcs_epcs_control_port_readdata_from_sa[7].DATAIN
epcs_epcs_control_port_readdata[8] => epcs_epcs_control_port_readdata_from_sa[8].DATAIN
epcs_epcs_control_port_readdata[9] => epcs_epcs_control_port_readdata_from_sa[9].DATAIN
epcs_epcs_control_port_readdata[10] => epcs_epcs_control_port_readdata_from_sa[10].DATAIN
epcs_epcs_control_port_readdata[11] => epcs_epcs_control_port_readdata_from_sa[11].DATAIN
epcs_epcs_control_port_readdata[12] => epcs_epcs_control_port_readdata_from_sa[12].DATAIN
epcs_epcs_control_port_readdata[13] => epcs_epcs_control_port_readdata_from_sa[13].DATAIN
epcs_epcs_control_port_readdata[14] => epcs_epcs_control_port_readdata_from_sa[14].DATAIN
epcs_epcs_control_port_readdata[15] => epcs_epcs_control_port_readdata_from_sa[15].DATAIN
epcs_epcs_control_port_readdata[16] => epcs_epcs_control_port_readdata_from_sa[16].DATAIN
epcs_epcs_control_port_readdata[17] => epcs_epcs_control_port_readdata_from_sa[17].DATAIN
epcs_epcs_control_port_readdata[18] => epcs_epcs_control_port_readdata_from_sa[18].DATAIN
epcs_epcs_control_port_readdata[19] => epcs_epcs_control_port_readdata_from_sa[19].DATAIN
epcs_epcs_control_port_readdata[20] => epcs_epcs_control_port_readdata_from_sa[20].DATAIN
epcs_epcs_control_port_readdata[21] => epcs_epcs_control_port_readdata_from_sa[21].DATAIN
epcs_epcs_control_port_readdata[22] => epcs_epcs_control_port_readdata_from_sa[22].DATAIN
epcs_epcs_control_port_readdata[23] => epcs_epcs_control_port_readdata_from_sa[23].DATAIN
epcs_epcs_control_port_readdata[24] => epcs_epcs_control_port_readdata_from_sa[24].DATAIN
epcs_epcs_control_port_readdata[25] => epcs_epcs_control_port_readdata_from_sa[25].DATAIN
epcs_epcs_control_port_readdata[26] => epcs_epcs_control_port_readdata_from_sa[26].DATAIN
epcs_epcs_control_port_readdata[27] => epcs_epcs_control_port_readdata_from_sa[27].DATAIN
epcs_epcs_control_port_readdata[28] => epcs_epcs_control_port_readdata_from_sa[28].DATAIN
epcs_epcs_control_port_readdata[29] => epcs_epcs_control_port_readdata_from_sa[29].DATAIN
epcs_epcs_control_port_readdata[30] => epcs_epcs_control_port_readdata_from_sa[30].DATAIN
epcs_epcs_control_port_readdata[31] => epcs_epcs_control_port_readdata_from_sa[31].DATAIN
epcs_epcs_control_port_readyfordata => epcs_epcs_control_port_readyfordata_from_sa.DATAIN
reset_n => epcs_epcs_control_port_reset_n.DATAIN
reset_n => d1_epcs_epcs_control_port_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR
reset_n => epcs_epcs_control_port_arb_share_counter[0].ACLR
reset_n => epcs_epcs_control_port_arb_share_counter[1].ACLR
reset_n => epcs_epcs_control_port_slavearbiterlockenable.ACLR
reset_n => last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port.ACLR
reset_n => last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port.ACLR
reset_n => epcs_epcs_control_port_saved_chosen_master_vector[0].ACLR
reset_n => epcs_epcs_control_port_saved_chosen_master_vector[1].ACLR
reset_n => epcs_epcs_control_port_arb_addend[0].PRESET
reset_n => epcs_epcs_control_port_arb_addend[1].ACLR
reset_n => epcs_epcs_control_port_reg_firsttransfer.PRESET


|LED_hello_world|CORE_SOPC:inst|epcs:the_epcs
address[0] => mem_addr[0].IN2
address[1] => mem_addr[1].IN2
address[2] => mem_addr[2].IN2
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
address[8] => epcs_select.IN0
chipselect => epcs_select.IN1
clk => clk.IN2
data0 => MISO.IN1
read_n => read_n.IN1
reset_n => reset_n.IN1
write_n => write_n.IN1
writedata[0] => data_from_cpu[0].IN1
writedata[1] => data_from_cpu[1].IN1
writedata[2] => data_from_cpu[2].IN1
writedata[3] => data_from_cpu[3].IN1
writedata[4] => data_from_cpu[4].IN1
writedata[5] => data_from_cpu[5].IN1
writedata[6] => data_from_cpu[6].IN1
writedata[7] => data_from_cpu[7].IN1
writedata[8] => data_from_cpu[8].IN1
writedata[9] => data_from_cpu[9].IN1
writedata[10] => data_from_cpu[10].IN1
writedata[11] => data_from_cpu[11].IN1
writedata[12] => data_from_cpu[12].IN1
writedata[13] => data_from_cpu[13].IN1
writedata[14] => data_from_cpu[14].IN1
writedata[15] => data_from_cpu[15].IN1
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub
MISO => MISO_reg.DATAA
clk => MISO_reg.CLK
clk => SCLK_reg.CLK
clk => transmitting.CLK
clk => tx_holding_primed.CLK
clk => tx_holding_reg[0].CLK
clk => tx_holding_reg[1].CLK
clk => tx_holding_reg[2].CLK
clk => tx_holding_reg[3].CLK
clk => tx_holding_reg[4].CLK
clk => tx_holding_reg[5].CLK
clk => tx_holding_reg[6].CLK
clk => tx_holding_reg[7].CLK
clk => TOE.CLK
clk => ROE.CLK
clk => RRDY.CLK
clk => EOP.CLK
clk => rx_holding_reg[0].CLK
clk => rx_holding_reg[1].CLK
clk => rx_holding_reg[2].CLK
clk => rx_holding_reg[3].CLK
clk => rx_holding_reg[4].CLK
clk => rx_holding_reg[5].CLK
clk => rx_holding_reg[6].CLK
clk => rx_holding_reg[7].CLK
clk => shift_reg[0].CLK
clk => shift_reg[1].CLK
clk => shift_reg[2].CLK
clk => shift_reg[3].CLK
clk => shift_reg[4].CLK
clk => shift_reg[5].CLK
clk => shift_reg[6].CLK
clk => shift_reg[7].CLK
clk => stateZero.CLK
clk => state[0].CLK
clk => state[1].CLK
clk => state[2].CLK
clk => state[3].CLK
clk => state[4].CLK
clk => data_to_cpu[0]~reg0.CLK
clk => data_to_cpu[1]~reg0.CLK
clk => data_to_cpu[2]~reg0.CLK
clk => data_to_cpu[3]~reg0.CLK
clk => data_to_cpu[4]~reg0.CLK
clk => data_to_cpu[5]~reg0.CLK
clk => data_to_cpu[6]~reg0.CLK
clk => data_to_cpu[7]~reg0.CLK
clk => data_to_cpu[8]~reg0.CLK
clk => data_to_cpu[9]~reg0.CLK
clk => data_to_cpu[10]~reg0.CLK
clk => data_to_cpu[11]~reg0.CLK
clk => data_to_cpu[12]~reg0.CLK
clk => data_to_cpu[13]~reg0.CLK
clk => data_to_cpu[14]~reg0.CLK
clk => data_to_cpu[15]~reg0.CLK
clk => endofpacketvalue_reg[0].CLK
clk => endofpacketvalue_reg[1].CLK
clk => endofpacketvalue_reg[2].CLK
clk => endofpacketvalue_reg[3].CLK
clk => endofpacketvalue_reg[4].CLK
clk => endofpacketvalue_reg[5].CLK
clk => endofpacketvalue_reg[6].CLK
clk => endofpacketvalue_reg[7].CLK
clk => endofpacketvalue_reg[8].CLK
clk => endofpacketvalue_reg[9].CLK
clk => endofpacketvalue_reg[10].CLK
clk => endofpacketvalue_reg[11].CLK
clk => endofpacketvalue_reg[12].CLK
clk => endofpacketvalue_reg[13].CLK
clk => endofpacketvalue_reg[14].CLK
clk => endofpacketvalue_reg[15].CLK
clk => slowcount[0].CLK
clk => slowcount[1].CLK
clk => epcs_slave_select_holding_reg[0].CLK
clk => epcs_slave_select_holding_reg[1].CLK
clk => epcs_slave_select_holding_reg[2].CLK
clk => epcs_slave_select_holding_reg[3].CLK
clk => epcs_slave_select_holding_reg[4].CLK
clk => epcs_slave_select_holding_reg[5].CLK
clk => epcs_slave_select_holding_reg[6].CLK
clk => epcs_slave_select_holding_reg[7].CLK
clk => epcs_slave_select_holding_reg[8].CLK
clk => epcs_slave_select_holding_reg[9].CLK
clk => epcs_slave_select_holding_reg[10].CLK
clk => epcs_slave_select_holding_reg[11].CLK
clk => epcs_slave_select_holding_reg[12].CLK
clk => epcs_slave_select_holding_reg[13].CLK
clk => epcs_slave_select_holding_reg[14].CLK
clk => epcs_slave_select_holding_reg[15].CLK
clk => epcs_slave_select_reg[0].CLK
clk => epcs_slave_select_reg[1].CLK
clk => epcs_slave_select_reg[2].CLK
clk => epcs_slave_select_reg[3].CLK
clk => epcs_slave_select_reg[4].CLK
clk => epcs_slave_select_reg[5].CLK
clk => epcs_slave_select_reg[6].CLK
clk => epcs_slave_select_reg[7].CLK
clk => epcs_slave_select_reg[8].CLK
clk => epcs_slave_select_reg[9].CLK
clk => epcs_slave_select_reg[10].CLK
clk => epcs_slave_select_reg[11].CLK
clk => epcs_slave_select_reg[12].CLK
clk => epcs_slave_select_reg[13].CLK
clk => epcs_slave_select_reg[14].CLK
clk => epcs_slave_select_reg[15].CLK
clk => irq_reg.CLK
clk => SSO_reg.CLK
clk => iROE_reg.CLK
clk => iTOE_reg.CLK
clk => iTRDY_reg.CLK
clk => iRRDY_reg.CLK
clk => iE_reg.CLK
clk => iEOP_reg.CLK
clk => data_wr_strobe.CLK
clk => wr_strobe.CLK
clk => data_rd_strobe.CLK
clk => rd_strobe.CLK
data_from_cpu[0] => Equal8.IN15
data_from_cpu[0] => epcs_slave_select_holding_reg[0].DATAIN
data_from_cpu[0] => endofpacketvalue_reg[0].DATAIN
data_from_cpu[0] => tx_holding_reg[0].DATAIN
data_from_cpu[1] => Equal8.IN14
data_from_cpu[1] => epcs_slave_select_holding_reg[1].DATAIN
data_from_cpu[1] => endofpacketvalue_reg[1].DATAIN
data_from_cpu[1] => tx_holding_reg[1].DATAIN
data_from_cpu[2] => Equal8.IN13
data_from_cpu[2] => epcs_slave_select_holding_reg[2].DATAIN
data_from_cpu[2] => endofpacketvalue_reg[2].DATAIN
data_from_cpu[2] => tx_holding_reg[2].DATAIN
data_from_cpu[3] => Equal8.IN12
data_from_cpu[3] => iROE_reg.DATAIN
data_from_cpu[3] => epcs_slave_select_holding_reg[3].DATAIN
data_from_cpu[3] => endofpacketvalue_reg[3].DATAIN
data_from_cpu[3] => tx_holding_reg[3].DATAIN
data_from_cpu[4] => Equal8.IN11
data_from_cpu[4] => iTOE_reg.DATAIN
data_from_cpu[4] => epcs_slave_select_holding_reg[4].DATAIN
data_from_cpu[4] => endofpacketvalue_reg[4].DATAIN
data_from_cpu[4] => tx_holding_reg[4].DATAIN
data_from_cpu[5] => Equal8.IN10
data_from_cpu[5] => epcs_slave_select_holding_reg[5].DATAIN
data_from_cpu[5] => endofpacketvalue_reg[5].DATAIN
data_from_cpu[5] => tx_holding_reg[5].DATAIN
data_from_cpu[6] => Equal8.IN9
data_from_cpu[6] => iTRDY_reg.DATAIN
data_from_cpu[6] => epcs_slave_select_holding_reg[6].DATAIN
data_from_cpu[6] => endofpacketvalue_reg[6].DATAIN
data_from_cpu[6] => tx_holding_reg[6].DATAIN
data_from_cpu[7] => Equal8.IN8
data_from_cpu[7] => iRRDY_reg.DATAIN
data_from_cpu[7] => epcs_slave_select_holding_reg[7].DATAIN
data_from_cpu[7] => endofpacketvalue_reg[7].DATAIN
data_from_cpu[7] => tx_holding_reg[7].DATAIN
data_from_cpu[8] => iE_reg.DATAIN
data_from_cpu[8] => epcs_slave_select_holding_reg[8].DATAIN
data_from_cpu[8] => endofpacketvalue_reg[8].DATAIN
data_from_cpu[9] => iEOP_reg.DATAIN
data_from_cpu[9] => epcs_slave_select_holding_reg[9].DATAIN
data_from_cpu[9] => endofpacketvalue_reg[9].DATAIN
data_from_cpu[10] => always6.IN1
data_from_cpu[10] => SSO_reg.DATAIN
data_from_cpu[10] => epcs_slave_select_holding_reg[10].DATAIN
data_from_cpu[10] => endofpacketvalue_reg[10].DATAIN
data_from_cpu[11] => epcs_slave_select_holding_reg[11].DATAIN
data_from_cpu[11] => endofpacketvalue_reg[11].DATAIN
data_from_cpu[12] => epcs_slave_select_holding_reg[12].DATAIN
data_from_cpu[12] => endofpacketvalue_reg[12].DATAIN
data_from_cpu[13] => epcs_slave_select_holding_reg[13].DATAIN
data_from_cpu[13] => endofpacketvalue_reg[13].DATAIN
data_from_cpu[14] => epcs_slave_select_holding_reg[14].DATAIN
data_from_cpu[14] => endofpacketvalue_reg[14].DATAIN
data_from_cpu[15] => epcs_slave_select_holding_reg[15].DATAIN
data_from_cpu[15] => endofpacketvalue_reg[15].DATAIN
epcs_select => p1_rd_strobe.IN1
epcs_select => p1_wr_strobe.IN1
mem_addr[0] => Equal0.IN31
mem_addr[0] => Equal1.IN0
mem_addr[0] => Equal3.IN31
mem_addr[0] => Equal4.IN1
mem_addr[0] => Equal5.IN31
mem_addr[0] => Equal6.IN1
mem_addr[1] => Equal0.IN30
mem_addr[1] => Equal1.IN31
mem_addr[1] => Equal3.IN0
mem_addr[1] => Equal4.IN0
mem_addr[1] => Equal5.IN1
mem_addr[1] => Equal6.IN31
mem_addr[2] => Equal0.IN29
mem_addr[2] => Equal1.IN30
mem_addr[2] => Equal3.IN30
mem_addr[2] => Equal4.IN31
mem_addr[2] => Equal5.IN0
mem_addr[2] => Equal6.IN0
read_n => p1_rd_strobe.IN1
reset_n => MISO_reg.ACLR
reset_n => SCLK_reg.ACLR
reset_n => transmitting.ACLR
reset_n => tx_holding_primed.ACLR
reset_n => tx_holding_reg[0].ACLR
reset_n => tx_holding_reg[1].ACLR
reset_n => tx_holding_reg[2].ACLR
reset_n => tx_holding_reg[3].ACLR
reset_n => tx_holding_reg[4].ACLR
reset_n => tx_holding_reg[5].ACLR
reset_n => tx_holding_reg[6].ACLR
reset_n => tx_holding_reg[7].ACLR
reset_n => TOE.ACLR
reset_n => ROE.ACLR
reset_n => RRDY.ACLR
reset_n => EOP.ACLR
reset_n => rx_holding_reg[0].ACLR
reset_n => rx_holding_reg[1].ACLR
reset_n => rx_holding_reg[2].ACLR
reset_n => rx_holding_reg[3].ACLR
reset_n => rx_holding_reg[4].ACLR
reset_n => rx_holding_reg[5].ACLR
reset_n => rx_holding_reg[6].ACLR
reset_n => rx_holding_reg[7].ACLR
reset_n => shift_reg[0].ACLR
reset_n => shift_reg[1].ACLR
reset_n => shift_reg[2].ACLR
reset_n => shift_reg[3].ACLR
reset_n => shift_reg[4].ACLR
reset_n => shift_reg[5].ACLR
reset_n => shift_reg[6].ACLR
reset_n => shift_reg[7].ACLR
reset_n => data_to_cpu[0]~reg0.ACLR
reset_n => data_to_cpu[1]~reg0.ACLR
reset_n => data_to_cpu[2]~reg0.ACLR
reset_n => data_to_cpu[3]~reg0.ACLR
reset_n => data_to_cpu[4]~reg0.ACLR
reset_n => data_to_cpu[5]~reg0.ACLR
reset_n => data_to_cpu[6]~reg0.ACLR
reset_n => data_to_cpu[7]~reg0.ACLR
reset_n => data_to_cpu[8]~reg0.ACLR
reset_n => data_to_cpu[9]~reg0.ACLR
reset_n => data_to_cpu[10]~reg0.ACLR
reset_n => data_to_cpu[11]~reg0.ACLR
reset_n => data_to_cpu[12]~reg0.ACLR
reset_n => data_to_cpu[13]~reg0.ACLR
reset_n => data_to_cpu[14]~reg0.ACLR
reset_n => data_to_cpu[15]~reg0.ACLR
reset_n => irq_reg.ACLR
reset_n => rd_strobe.ACLR
reset_n => data_rd_strobe.ACLR
reset_n => wr_strobe.ACLR
reset_n => data_wr_strobe.ACLR
reset_n => SSO_reg.ACLR
reset_n => iROE_reg.ACLR
reset_n => iTOE_reg.ACLR
reset_n => iTRDY_reg.ACLR
reset_n => iRRDY_reg.ACLR
reset_n => iE_reg.ACLR
reset_n => iEOP_reg.ACLR
reset_n => epcs_slave_select_reg[0].PRESET
reset_n => epcs_slave_select_reg[1].ACLR
reset_n => epcs_slave_select_reg[2].ACLR
reset_n => epcs_slave_select_reg[3].ACLR
reset_n => epcs_slave_select_reg[4].ACLR
reset_n => epcs_slave_select_reg[5].ACLR
reset_n => epcs_slave_select_reg[6].ACLR
reset_n => epcs_slave_select_reg[7].ACLR
reset_n => epcs_slave_select_reg[8].ACLR
reset_n => epcs_slave_select_reg[9].ACLR
reset_n => epcs_slave_select_reg[10].ACLR
reset_n => epcs_slave_select_reg[11].ACLR
reset_n => epcs_slave_select_reg[12].ACLR
reset_n => epcs_slave_select_reg[13].ACLR
reset_n => epcs_slave_select_reg[14].ACLR
reset_n => epcs_slave_select_reg[15].ACLR
reset_n => epcs_slave_select_holding_reg[0].PRESET
reset_n => epcs_slave_select_holding_reg[1].ACLR
reset_n => epcs_slave_select_holding_reg[2].ACLR
reset_n => epcs_slave_select_holding_reg[3].ACLR
reset_n => epcs_slave_select_holding_reg[4].ACLR
reset_n => epcs_slave_select_holding_reg[5].ACLR
reset_n => epcs_slave_select_holding_reg[6].ACLR
reset_n => epcs_slave_select_holding_reg[7].ACLR
reset_n => epcs_slave_select_holding_reg[8].ACLR
reset_n => epcs_slave_select_holding_reg[9].ACLR
reset_n => epcs_slave_select_holding_reg[10].ACLR
reset_n => epcs_slave_select_holding_reg[11].ACLR
reset_n => epcs_slave_select_holding_reg[12].ACLR
reset_n => epcs_slave_select_holding_reg[13].ACLR
reset_n => epcs_slave_select_holding_reg[14].ACLR
reset_n => epcs_slave_select_holding_reg[15].ACLR
reset_n => slowcount[0].ACLR
reset_n => slowcount[1].ACLR
reset_n => endofpacketvalue_reg[0].ACLR
reset_n => endofpacketvalue_reg[1].ACLR
reset_n => endofpacketvalue_reg[2].ACLR
reset_n => endofpacketvalue_reg[3].ACLR
reset_n => endofpacketvalue_reg[4].ACLR
reset_n => endofpacketvalue_reg[5].ACLR
reset_n => endofpacketvalue_reg[6].ACLR
reset_n => endofpacketvalue_reg[7].ACLR
reset_n => endofpacketvalue_reg[8].ACLR
reset_n => endofpacketvalue_reg[9].ACLR
reset_n => endofpacketvalue_reg[10].ACLR
reset_n => endofpacketvalue_reg[11].ACLR
reset_n => endofpacketvalue_reg[12].ACLR
reset_n => endofpacketvalue_reg[13].ACLR
reset_n => endofpacketvalue_reg[14].ACLR
reset_n => endofpacketvalue_reg[15].ACLR
reset_n => stateZero.PRESET
reset_n => state[0].ACLR
reset_n => state[1].ACLR
reset_n => state[2].ACLR
reset_n => state[3].ACLR
reset_n => state[4].ACLR
write_n => p1_wr_strobe.IN1


|LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_a[16] => ~NO_FANOUT~
data_a[17] => ~NO_FANOUT~
data_a[18] => ~NO_FANOUT~
data_a[19] => ~NO_FANOUT~
data_a[20] => ~NO_FANOUT~
data_a[21] => ~NO_FANOUT~
data_a[22] => ~NO_FANOUT~
data_a[23] => ~NO_FANOUT~
data_a[24] => ~NO_FANOUT~
data_a[25] => ~NO_FANOUT~
data_a[26] => ~NO_FANOUT~
data_a[27] => ~NO_FANOUT~
data_a[28] => ~NO_FANOUT~
data_a[29] => ~NO_FANOUT~
data_a[30] => ~NO_FANOUT~
data_a[31] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_sc31:auto_generated.address_a[0]
address_a[1] => altsyncram_sc31:auto_generated.address_a[1]
address_a[2] => altsyncram_sc31:auto_generated.address_a[2]
address_a[3] => altsyncram_sc31:auto_generated.address_a[3]
address_a[4] => altsyncram_sc31:auto_generated.address_a[4]
address_a[5] => altsyncram_sc31:auto_generated.address_a[5]
address_a[6] => altsyncram_sc31:auto_generated.address_a[6]
address_a[7] => altsyncram_sc31:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_sc31:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom|altsyncram_sc31:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0


|LED_hello_world|CORE_SOPC:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave
clk => d1_jtag_uart_avalon_jtag_slave_end_xfer~reg0.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => jtag_uart_avalon_jtag_slave_address.DATAIN
cpu_data_master_address_to_slave[3] => Equal0.IN4
cpu_data_master_address_to_slave[4] => Equal0.IN23
cpu_data_master_address_to_slave[5] => Equal0.IN22
cpu_data_master_address_to_slave[6] => Equal0.IN3
cpu_data_master_address_to_slave[7] => Equal0.IN2
cpu_data_master_address_to_slave[8] => Equal0.IN21
cpu_data_master_address_to_slave[9] => Equal0.IN20
cpu_data_master_address_to_slave[10] => Equal0.IN19
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN18
cpu_data_master_address_to_slave[14] => Equal0.IN17
cpu_data_master_address_to_slave[15] => Equal0.IN16
cpu_data_master_address_to_slave[16] => Equal0.IN15
cpu_data_master_address_to_slave[17] => Equal0.IN14
cpu_data_master_address_to_slave[18] => Equal0.IN13
cpu_data_master_address_to_slave[19] => Equal0.IN12
cpu_data_master_address_to_slave[20] => Equal0.IN11
cpu_data_master_address_to_slave[21] => Equal0.IN10
cpu_data_master_address_to_slave[22] => Equal0.IN9
cpu_data_master_address_to_slave[23] => Equal0.IN8
cpu_data_master_address_to_slave[24] => Equal0.IN7
cpu_data_master_address_to_slave[25] => Equal0.IN6
cpu_data_master_address_to_slave[26] => Equal0.IN5
cpu_data_master_read => cpu_data_master_requests_jtag_uart_avalon_jtag_slave.IN0
cpu_data_master_read => cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave.IN0
cpu_data_master_read => jtag_uart_avalon_jtag_slave_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave.IN0
cpu_data_master_waitrequest => cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave.IN1
cpu_data_master_write => cpu_data_master_requests_jtag_uart_avalon_jtag_slave.IN1
cpu_data_master_write => cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave.IN1
cpu_data_master_write => jtag_uart_avalon_jtag_slave_in_a_write_cycle.IN1
cpu_data_master_writedata[0] => jtag_uart_avalon_jtag_slave_writedata[0].DATAIN
cpu_data_master_writedata[1] => jtag_uart_avalon_jtag_slave_writedata[1].DATAIN
cpu_data_master_writedata[2] => jtag_uart_avalon_jtag_slave_writedata[2].DATAIN
cpu_data_master_writedata[3] => jtag_uart_avalon_jtag_slave_writedata[3].DATAIN
cpu_data_master_writedata[4] => jtag_uart_avalon_jtag_slave_writedata[4].DATAIN
cpu_data_master_writedata[5] => jtag_uart_avalon_jtag_slave_writedata[5].DATAIN
cpu_data_master_writedata[6] => jtag_uart_avalon_jtag_slave_writedata[6].DATAIN
cpu_data_master_writedata[7] => jtag_uart_avalon_jtag_slave_writedata[7].DATAIN
cpu_data_master_writedata[8] => jtag_uart_avalon_jtag_slave_writedata[8].DATAIN
cpu_data_master_writedata[9] => jtag_uart_avalon_jtag_slave_writedata[9].DATAIN
cpu_data_master_writedata[10] => jtag_uart_avalon_jtag_slave_writedata[10].DATAIN
cpu_data_master_writedata[11] => jtag_uart_avalon_jtag_slave_writedata[11].DATAIN
cpu_data_master_writedata[12] => jtag_uart_avalon_jtag_slave_writedata[12].DATAIN
cpu_data_master_writedata[13] => jtag_uart_avalon_jtag_slave_writedata[13].DATAIN
cpu_data_master_writedata[14] => jtag_uart_avalon_jtag_slave_writedata[14].DATAIN
cpu_data_master_writedata[15] => jtag_uart_avalon_jtag_slave_writedata[15].DATAIN
cpu_data_master_writedata[16] => jtag_uart_avalon_jtag_slave_writedata[16].DATAIN
cpu_data_master_writedata[17] => jtag_uart_avalon_jtag_slave_writedata[17].DATAIN
cpu_data_master_writedata[18] => jtag_uart_avalon_jtag_slave_writedata[18].DATAIN
cpu_data_master_writedata[19] => jtag_uart_avalon_jtag_slave_writedata[19].DATAIN
cpu_data_master_writedata[20] => jtag_uart_avalon_jtag_slave_writedata[20].DATAIN
cpu_data_master_writedata[21] => jtag_uart_avalon_jtag_slave_writedata[21].DATAIN
cpu_data_master_writedata[22] => jtag_uart_avalon_jtag_slave_writedata[22].DATAIN
cpu_data_master_writedata[23] => jtag_uart_avalon_jtag_slave_writedata[23].DATAIN
cpu_data_master_writedata[24] => jtag_uart_avalon_jtag_slave_writedata[24].DATAIN
cpu_data_master_writedata[25] => jtag_uart_avalon_jtag_slave_writedata[25].DATAIN
cpu_data_master_writedata[26] => jtag_uart_avalon_jtag_slave_writedata[26].DATAIN
cpu_data_master_writedata[27] => jtag_uart_avalon_jtag_slave_writedata[27].DATAIN
cpu_data_master_writedata[28] => jtag_uart_avalon_jtag_slave_writedata[28].DATAIN
cpu_data_master_writedata[29] => jtag_uart_avalon_jtag_slave_writedata[29].DATAIN
cpu_data_master_writedata[30] => jtag_uart_avalon_jtag_slave_writedata[30].DATAIN
cpu_data_master_writedata[31] => jtag_uart_avalon_jtag_slave_writedata[31].DATAIN
jtag_uart_avalon_jtag_slave_dataavailable => jtag_uart_avalon_jtag_slave_dataavailable_from_sa.DATAIN
jtag_uart_avalon_jtag_slave_irq => jtag_uart_avalon_jtag_slave_irq_from_sa.DATAIN
jtag_uart_avalon_jtag_slave_readdata[0] => jtag_uart_avalon_jtag_slave_readdata_from_sa[0].DATAIN
jtag_uart_avalon_jtag_slave_readdata[1] => jtag_uart_avalon_jtag_slave_readdata_from_sa[1].DATAIN
jtag_uart_avalon_jtag_slave_readdata[2] => jtag_uart_avalon_jtag_slave_readdata_from_sa[2].DATAIN
jtag_uart_avalon_jtag_slave_readdata[3] => jtag_uart_avalon_jtag_slave_readdata_from_sa[3].DATAIN
jtag_uart_avalon_jtag_slave_readdata[4] => jtag_uart_avalon_jtag_slave_readdata_from_sa[4].DATAIN
jtag_uart_avalon_jtag_slave_readdata[5] => jtag_uart_avalon_jtag_slave_readdata_from_sa[5].DATAIN
jtag_uart_avalon_jtag_slave_readdata[6] => jtag_uart_avalon_jtag_slave_readdata_from_sa[6].DATAIN
jtag_uart_avalon_jtag_slave_readdata[7] => jtag_uart_avalon_jtag_slave_readdata_from_sa[7].DATAIN
jtag_uart_avalon_jtag_slave_readdata[8] => jtag_uart_avalon_jtag_slave_readdata_from_sa[8].DATAIN
jtag_uart_avalon_jtag_slave_readdata[9] => jtag_uart_avalon_jtag_slave_readdata_from_sa[9].DATAIN
jtag_uart_avalon_jtag_slave_readdata[10] => jtag_uart_avalon_jtag_slave_readdata_from_sa[10].DATAIN
jtag_uart_avalon_jtag_slave_readdata[11] => jtag_uart_avalon_jtag_slave_readdata_from_sa[11].DATAIN
jtag_uart_avalon_jtag_slave_readdata[12] => jtag_uart_avalon_jtag_slave_readdata_from_sa[12].DATAIN
jtag_uart_avalon_jtag_slave_readdata[13] => jtag_uart_avalon_jtag_slave_readdata_from_sa[13].DATAIN
jtag_uart_avalon_jtag_slave_readdata[14] => jtag_uart_avalon_jtag_slave_readdata_from_sa[14].DATAIN
jtag_uart_avalon_jtag_slave_readdata[15] => jtag_uart_avalon_jtag_slave_readdata_from_sa[15].DATAIN
jtag_uart_avalon_jtag_slave_readdata[16] => jtag_uart_avalon_jtag_slave_readdata_from_sa[16].DATAIN
jtag_uart_avalon_jtag_slave_readdata[17] => jtag_uart_avalon_jtag_slave_readdata_from_sa[17].DATAIN
jtag_uart_avalon_jtag_slave_readdata[18] => jtag_uart_avalon_jtag_slave_readdata_from_sa[18].DATAIN
jtag_uart_avalon_jtag_slave_readdata[19] => jtag_uart_avalon_jtag_slave_readdata_from_sa[19].DATAIN
jtag_uart_avalon_jtag_slave_readdata[20] => jtag_uart_avalon_jtag_slave_readdata_from_sa[20].DATAIN
jtag_uart_avalon_jtag_slave_readdata[21] => jtag_uart_avalon_jtag_slave_readdata_from_sa[21].DATAIN
jtag_uart_avalon_jtag_slave_readdata[22] => jtag_uart_avalon_jtag_slave_readdata_from_sa[22].DATAIN
jtag_uart_avalon_jtag_slave_readdata[23] => jtag_uart_avalon_jtag_slave_readdata_from_sa[23].DATAIN
jtag_uart_avalon_jtag_slave_readdata[24] => jtag_uart_avalon_jtag_slave_readdata_from_sa[24].DATAIN
jtag_uart_avalon_jtag_slave_readdata[25] => jtag_uart_avalon_jtag_slave_readdata_from_sa[25].DATAIN
jtag_uart_avalon_jtag_slave_readdata[26] => jtag_uart_avalon_jtag_slave_readdata_from_sa[26].DATAIN
jtag_uart_avalon_jtag_slave_readdata[27] => jtag_uart_avalon_jtag_slave_readdata_from_sa[27].DATAIN
jtag_uart_avalon_jtag_slave_readdata[28] => jtag_uart_avalon_jtag_slave_readdata_from_sa[28].DATAIN
jtag_uart_avalon_jtag_slave_readdata[29] => jtag_uart_avalon_jtag_slave_readdata_from_sa[29].DATAIN
jtag_uart_avalon_jtag_slave_readdata[30] => jtag_uart_avalon_jtag_slave_readdata_from_sa[30].DATAIN
jtag_uart_avalon_jtag_slave_readdata[31] => jtag_uart_avalon_jtag_slave_readdata_from_sa[31].DATAIN
jtag_uart_avalon_jtag_slave_readyfordata => jtag_uart_avalon_jtag_slave_readyfordata_from_sa.DATAIN
jtag_uart_avalon_jtag_slave_waitrequest => jtag_uart_avalon_jtag_slave_waits_for_read.IN1
jtag_uart_avalon_jtag_slave_waitrequest => jtag_uart_avalon_jtag_slave_waits_for_write.IN1
jtag_uart_avalon_jtag_slave_waitrequest => jtag_uart_avalon_jtag_slave_waitrequest_from_sa.DATAIN
reset_n => jtag_uart_avalon_jtag_slave_reset_n.DATAIN
reset_n => d1_jtag_uart_avalon_jtag_slave_end_xfer~reg0.PRESET


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart
av_address => ien_AF.OUTPUTSELECT
av_address => ien_AE.OUTPUTSELECT
av_address => ac.OUTPUTSELECT
av_address => fifo_wr.OUTPUTSELECT
av_address => woverflow.OUTPUTSELECT
av_address => rvalid.OUTPUTSELECT
av_address => read_0.DATAB
av_address => fifo_rd.IN1
av_chipselect => av_waitrequest.IN1
av_chipselect => always2.IN0
av_chipselect => always2.IN0
av_chipselect => fifo_rd.IN0
av_read_n => always2.IN1
av_read_n => av_waitrequest.IN0
av_read_n => fifo_rd.IN1
av_write_n => always2.IN1
av_write_n => av_waitrequest.IN1
av_writedata[0] => fifo_wdata[0].IN1
av_writedata[1] => fifo_wdata[1].IN1
av_writedata[2] => fifo_wdata[2].IN1
av_writedata[3] => fifo_wdata[3].IN1
av_writedata[4] => fifo_wdata[4].IN1
av_writedata[5] => fifo_wdata[5].IN1
av_writedata[6] => fifo_wdata[6].IN1
av_writedata[7] => fifo_wdata[7].IN1
av_writedata[8] => ~NO_FANOUT~
av_writedata[9] => ~NO_FANOUT~
av_writedata[10] => always2.IN1
av_writedata[11] => ~NO_FANOUT~
av_writedata[12] => ~NO_FANOUT~
av_writedata[13] => ~NO_FANOUT~
av_writedata[14] => ~NO_FANOUT~
av_writedata[15] => ~NO_FANOUT~
av_writedata[16] => ~NO_FANOUT~
av_writedata[17] => ~NO_FANOUT~
av_writedata[18] => ~NO_FANOUT~
av_writedata[19] => ~NO_FANOUT~
av_writedata[20] => ~NO_FANOUT~
av_writedata[21] => ~NO_FANOUT~
av_writedata[22] => ~NO_FANOUT~
av_writedata[23] => ~NO_FANOUT~
av_writedata[24] => ~NO_FANOUT~
av_writedata[25] => ~NO_FANOUT~
av_writedata[26] => ~NO_FANOUT~
av_writedata[27] => ~NO_FANOUT~
av_writedata[28] => ~NO_FANOUT~
av_writedata[29] => ~NO_FANOUT~
av_writedata[30] => ~NO_FANOUT~
av_writedata[31] => ~NO_FANOUT~
clk => clk.IN3
rst_n => rst_n.IN2


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w
clk => clk.IN1
fifo_clear => fifo_clear.IN1
fifo_wdata[0] => fifo_wdata[0].IN1
fifo_wdata[1] => fifo_wdata[1].IN1
fifo_wdata[2] => fifo_wdata[2].IN1
fifo_wdata[3] => fifo_wdata[3].IN1
fifo_wdata[4] => fifo_wdata[4].IN1
fifo_wdata[5] => fifo_wdata[5].IN1
fifo_wdata[6] => fifo_wdata[6].IN1
fifo_wdata[7] => fifo_wdata[7].IN1
fifo_wr => fifo_wr.IN1
rd_wfifo => rd_wfifo.IN1


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
data[0] => scfifo_jr21:auto_generated.data[0]
data[1] => scfifo_jr21:auto_generated.data[1]
data[2] => scfifo_jr21:auto_generated.data[2]
data[3] => scfifo_jr21:auto_generated.data[3]
data[4] => scfifo_jr21:auto_generated.data[4]
data[5] => scfifo_jr21:auto_generated.data[5]
data[6] => scfifo_jr21:auto_generated.data[6]
data[7] => scfifo_jr21:auto_generated.data[7]
wrreq => scfifo_jr21:auto_generated.wrreq
rdreq => scfifo_jr21:auto_generated.rdreq
clock => scfifo_jr21:auto_generated.clock
aclr => scfifo_jr21:auto_generated.aclr
sclr => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated
aclr => a_dpfifo_q131:dpfifo.aclr
clock => a_dpfifo_q131:dpfifo.clock
data[0] => a_dpfifo_q131:dpfifo.data[0]
data[1] => a_dpfifo_q131:dpfifo.data[1]
data[2] => a_dpfifo_q131:dpfifo.data[2]
data[3] => a_dpfifo_q131:dpfifo.data[3]
data[4] => a_dpfifo_q131:dpfifo.data[4]
data[5] => a_dpfifo_q131:dpfifo.data[5]
data[6] => a_dpfifo_q131:dpfifo.data[6]
data[7] => a_dpfifo_q131:dpfifo.data[7]
rdreq => a_dpfifo_q131:dpfifo.rreq
wrreq => a_dpfifo_q131:dpfifo.wreq


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo
aclr => a_fefifo_7cf:fifo_state.aclr
aclr => cntr_1ob:rd_ptr_count.aclr
aclr => cntr_1ob:wr_ptr.aclr
clock => a_fefifo_7cf:fifo_state.clock
clock => dpram_nl21:FIFOram.inclock
clock => dpram_nl21:FIFOram.outclock
clock => cntr_1ob:rd_ptr_count.clock
clock => cntr_1ob:wr_ptr.clock
data[0] => dpram_nl21:FIFOram.data[0]
data[1] => dpram_nl21:FIFOram.data[1]
data[2] => dpram_nl21:FIFOram.data[2]
data[3] => dpram_nl21:FIFOram.data[3]
data[4] => dpram_nl21:FIFOram.data[4]
data[5] => dpram_nl21:FIFOram.data[5]
data[6] => dpram_nl21:FIFOram.data[6]
data[7] => dpram_nl21:FIFOram.data[7]
rreq => a_fefifo_7cf:fifo_state.rreq
rreq => _.IN0
rreq => cntr_1ob:rd_ptr_count.cnt_en
sclr => a_fefifo_7cf:fifo_state.sclr
sclr => _.IN1
sclr => _.IN0
sclr => cntr_1ob:rd_ptr_count.sclr
sclr => cntr_1ob:wr_ptr.sclr
wreq => a_fefifo_7cf:fifo_state.wreq
wreq => dpram_nl21:FIFOram.wren
wreq => cntr_1ob:wr_ptr.cnt_en


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state
aclr => b_full.IN0
aclr => b_non_empty.IN0
aclr => cntr_do7:count_usedw.aclr
clock => cntr_do7:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
rreq => _.IN1
rreq => _.IN0
rreq => _.IN1
rreq => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => cntr_do7:count_usedw.sclr
wreq => _.IN1
wreq => _.IN1
wreq => _.IN0
wreq => _.IN0
wreq => cntr_do7:count_usedw.updown


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw
aclr => counter_reg_bit[5].IN0
clock => counter_reg_bit[5].CLK
clock => counter_reg_bit[4].CLK
clock => counter_reg_bit[3].CLK
clock => counter_reg_bit[2].CLK
clock => counter_reg_bit[1].CLK
clock => counter_reg_bit[0].CLK
cnt_en => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => _.IN0
updown => counter_comb_bita0.DATAB
updown => counter_comb_bita1.DATAB
updown => counter_comb_bita2.DATAB
updown => counter_comb_bita3.DATAB
updown => counter_comb_bita4.DATAB
updown => counter_comb_bita5.DATAB


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram
data[0] => altsyncram_r1m1:altsyncram1.data_a[0]
data[1] => altsyncram_r1m1:altsyncram1.data_a[1]
data[2] => altsyncram_r1m1:altsyncram1.data_a[2]
data[3] => altsyncram_r1m1:altsyncram1.data_a[3]
data[4] => altsyncram_r1m1:altsyncram1.data_a[4]
data[5] => altsyncram_r1m1:altsyncram1.data_a[5]
data[6] => altsyncram_r1m1:altsyncram1.data_a[6]
data[7] => altsyncram_r1m1:altsyncram1.data_a[7]
inclock => altsyncram_r1m1:altsyncram1.clock0
outclock => altsyncram_r1m1:altsyncram1.clock1
outclocken => altsyncram_r1m1:altsyncram1.clocken1
rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0]
rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1]
rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2]
rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3]
rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4]
rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5]
wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0]
wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1]
wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2]
wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3]
wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4]
wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5]
wren => altsyncram_r1m1:altsyncram1.wren_a


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_a[4] => ram_block2a0.PORTAADDR4
address_a[4] => ram_block2a1.PORTAADDR4
address_a[4] => ram_block2a2.PORTAADDR4
address_a[4] => ram_block2a3.PORTAADDR4
address_a[4] => ram_block2a4.PORTAADDR4
address_a[4] => ram_block2a5.PORTAADDR4
address_a[4] => ram_block2a6.PORTAADDR4
address_a[4] => ram_block2a7.PORTAADDR4
address_a[5] => ram_block2a0.PORTAADDR5
address_a[5] => ram_block2a1.PORTAADDR5
address_a[5] => ram_block2a2.PORTAADDR5
address_a[5] => ram_block2a3.PORTAADDR5
address_a[5] => ram_block2a4.PORTAADDR5
address_a[5] => ram_block2a5.PORTAADDR5
address_a[5] => ram_block2a6.PORTAADDR5
address_a[5] => ram_block2a7.PORTAADDR5
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[4] => ram_block2a0.PORTBADDR4
address_b[4] => ram_block2a1.PORTBADDR4
address_b[4] => ram_block2a2.PORTBADDR4
address_b[4] => ram_block2a3.PORTBADDR4
address_b[4] => ram_block2a4.PORTBADDR4
address_b[4] => ram_block2a5.PORTBADDR4
address_b[4] => ram_block2a6.PORTBADDR4
address_b[4] => ram_block2a7.PORTBADDR4
address_b[5] => ram_block2a0.PORTBADDR5
address_b[5] => ram_block2a1.PORTBADDR5
address_b[5] => ram_block2a2.PORTBADDR5
address_b[5] => ram_block2a3.PORTBADDR5
address_b[5] => ram_block2a4.PORTBADDR5
address_b[5] => ram_block2a5.PORTBADDR5
address_b[5] => ram_block2a6.PORTBADDR5
address_b[5] => ram_block2a7.PORTBADDR5
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
data_a[0] => ram_block2a0.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
wren_a => ram_block2a0.PORTAWE
wren_a => ram_block2a0.ENA0
wren_a => ram_block2a1.PORTAWE
wren_a => ram_block2a1.ENA0
wren_a => ram_block2a2.PORTAWE
wren_a => ram_block2a2.ENA0
wren_a => ram_block2a3.PORTAWE
wren_a => ram_block2a3.ENA0
wren_a => ram_block2a4.PORTAWE
wren_a => ram_block2a4.ENA0
wren_a => ram_block2a5.PORTAWE
wren_a => ram_block2a5.ENA0
wren_a => ram_block2a6.PORTAWE
wren_a => ram_block2a6.ENA0
wren_a => ram_block2a7.PORTAWE
wren_a => ram_block2a7.ENA0


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count
aclr => counter_reg_bit[5].IN0
clock => counter_reg_bit[5].CLK
clock => counter_reg_bit[4].CLK
clock => counter_reg_bit[3].CLK
clock => counter_reg_bit[2].CLK
clock => counter_reg_bit[1].CLK
clock => counter_reg_bit[0].CLK
cnt_en => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => _.IN0


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr
aclr => counter_reg_bit[5].IN0
clock => counter_reg_bit[5].CLK
clock => counter_reg_bit[4].CLK
clock => counter_reg_bit[3].CLK
clock => counter_reg_bit[2].CLK
clock => counter_reg_bit[1].CLK
clock => counter_reg_bit[0].CLK
cnt_en => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => _.IN0


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r
clk => clk.IN1
fifo_clear => fifo_clear.IN1
fifo_rd => fifo_rd.IN1
rst_n => ~NO_FANOUT~
t_dat[0] => t_dat[0].IN1
t_dat[1] => t_dat[1].IN1
t_dat[2] => t_dat[2].IN1
t_dat[3] => t_dat[3].IN1
t_dat[4] => t_dat[4].IN1
t_dat[5] => t_dat[5].IN1
t_dat[6] => t_dat[6].IN1
t_dat[7] => t_dat[7].IN1
wr_rfifo => wr_rfifo.IN1


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
data[0] => scfifo_jr21:auto_generated.data[0]
data[1] => scfifo_jr21:auto_generated.data[1]
data[2] => scfifo_jr21:auto_generated.data[2]
data[3] => scfifo_jr21:auto_generated.data[3]
data[4] => scfifo_jr21:auto_generated.data[4]
data[5] => scfifo_jr21:auto_generated.data[5]
data[6] => scfifo_jr21:auto_generated.data[6]
data[7] => scfifo_jr21:auto_generated.data[7]
wrreq => scfifo_jr21:auto_generated.wrreq
rdreq => scfifo_jr21:auto_generated.rdreq
clock => scfifo_jr21:auto_generated.clock
aclr => scfifo_jr21:auto_generated.aclr
sclr => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated
aclr => a_dpfifo_q131:dpfifo.aclr
clock => a_dpfifo_q131:dpfifo.clock
data[0] => a_dpfifo_q131:dpfifo.data[0]
data[1] => a_dpfifo_q131:dpfifo.data[1]
data[2] => a_dpfifo_q131:dpfifo.data[2]
data[3] => a_dpfifo_q131:dpfifo.data[3]
data[4] => a_dpfifo_q131:dpfifo.data[4]
data[5] => a_dpfifo_q131:dpfifo.data[5]
data[6] => a_dpfifo_q131:dpfifo.data[6]
data[7] => a_dpfifo_q131:dpfifo.data[7]
rdreq => a_dpfifo_q131:dpfifo.rreq
wrreq => a_dpfifo_q131:dpfifo.wreq


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo
aclr => a_fefifo_7cf:fifo_state.aclr
aclr => cntr_1ob:rd_ptr_count.aclr
aclr => cntr_1ob:wr_ptr.aclr
clock => a_fefifo_7cf:fifo_state.clock
clock => dpram_nl21:FIFOram.inclock
clock => dpram_nl21:FIFOram.outclock
clock => cntr_1ob:rd_ptr_count.clock
clock => cntr_1ob:wr_ptr.clock
data[0] => dpram_nl21:FIFOram.data[0]
data[1] => dpram_nl21:FIFOram.data[1]
data[2] => dpram_nl21:FIFOram.data[2]
data[3] => dpram_nl21:FIFOram.data[3]
data[4] => dpram_nl21:FIFOram.data[4]
data[5] => dpram_nl21:FIFOram.data[5]
data[6] => dpram_nl21:FIFOram.data[6]
data[7] => dpram_nl21:FIFOram.data[7]
rreq => a_fefifo_7cf:fifo_state.rreq
rreq => _.IN0
rreq => cntr_1ob:rd_ptr_count.cnt_en
sclr => a_fefifo_7cf:fifo_state.sclr
sclr => _.IN1
sclr => _.IN0
sclr => cntr_1ob:rd_ptr_count.sclr
sclr => cntr_1ob:wr_ptr.sclr
wreq => a_fefifo_7cf:fifo_state.wreq
wreq => dpram_nl21:FIFOram.wren
wreq => cntr_1ob:wr_ptr.cnt_en


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state
aclr => b_full.IN0
aclr => b_non_empty.IN0
aclr => cntr_do7:count_usedw.aclr
clock => cntr_do7:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
rreq => _.IN1
rreq => _.IN0
rreq => _.IN1
rreq => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => cntr_do7:count_usedw.sclr
wreq => _.IN1
wreq => _.IN1
wreq => _.IN0
wreq => _.IN0
wreq => cntr_do7:count_usedw.updown


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw
aclr => counter_reg_bit[5].IN0
clock => counter_reg_bit[5].CLK
clock => counter_reg_bit[4].CLK
clock => counter_reg_bit[3].CLK
clock => counter_reg_bit[2].CLK
clock => counter_reg_bit[1].CLK
clock => counter_reg_bit[0].CLK
cnt_en => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => _.IN0
updown => counter_comb_bita0.DATAB
updown => counter_comb_bita1.DATAB
updown => counter_comb_bita2.DATAB
updown => counter_comb_bita3.DATAB
updown => counter_comb_bita4.DATAB
updown => counter_comb_bita5.DATAB


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram
data[0] => altsyncram_r1m1:altsyncram1.data_a[0]
data[1] => altsyncram_r1m1:altsyncram1.data_a[1]
data[2] => altsyncram_r1m1:altsyncram1.data_a[2]
data[3] => altsyncram_r1m1:altsyncram1.data_a[3]
data[4] => altsyncram_r1m1:altsyncram1.data_a[4]
data[5] => altsyncram_r1m1:altsyncram1.data_a[5]
data[6] => altsyncram_r1m1:altsyncram1.data_a[6]
data[7] => altsyncram_r1m1:altsyncram1.data_a[7]
inclock => altsyncram_r1m1:altsyncram1.clock0
outclock => altsyncram_r1m1:altsyncram1.clock1
outclocken => altsyncram_r1m1:altsyncram1.clocken1
rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0]
rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1]
rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2]
rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3]
rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4]
rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5]
wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0]
wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1]
wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2]
wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3]
wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4]
wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5]
wren => altsyncram_r1m1:altsyncram1.wren_a


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_a[4] => ram_block2a0.PORTAADDR4
address_a[4] => ram_block2a1.PORTAADDR4
address_a[4] => ram_block2a2.PORTAADDR4
address_a[4] => ram_block2a3.PORTAADDR4
address_a[4] => ram_block2a4.PORTAADDR4
address_a[4] => ram_block2a5.PORTAADDR4
address_a[4] => ram_block2a6.PORTAADDR4
address_a[4] => ram_block2a7.PORTAADDR4
address_a[5] => ram_block2a0.PORTAADDR5
address_a[5] => ram_block2a1.PORTAADDR5
address_a[5] => ram_block2a2.PORTAADDR5
address_a[5] => ram_block2a3.PORTAADDR5
address_a[5] => ram_block2a4.PORTAADDR5
address_a[5] => ram_block2a5.PORTAADDR5
address_a[5] => ram_block2a6.PORTAADDR5
address_a[5] => ram_block2a7.PORTAADDR5
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[4] => ram_block2a0.PORTBADDR4
address_b[4] => ram_block2a1.PORTBADDR4
address_b[4] => ram_block2a2.PORTBADDR4
address_b[4] => ram_block2a3.PORTBADDR4
address_b[4] => ram_block2a4.PORTBADDR4
address_b[4] => ram_block2a5.PORTBADDR4
address_b[4] => ram_block2a6.PORTBADDR4
address_b[4] => ram_block2a7.PORTBADDR4
address_b[5] => ram_block2a0.PORTBADDR5
address_b[5] => ram_block2a1.PORTBADDR5
address_b[5] => ram_block2a2.PORTBADDR5
address_b[5] => ram_block2a3.PORTBADDR5
address_b[5] => ram_block2a4.PORTBADDR5
address_b[5] => ram_block2a5.PORTBADDR5
address_b[5] => ram_block2a6.PORTBADDR5
address_b[5] => ram_block2a7.PORTBADDR5
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
data_a[0] => ram_block2a0.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
wren_a => ram_block2a0.PORTAWE
wren_a => ram_block2a0.ENA0
wren_a => ram_block2a1.PORTAWE
wren_a => ram_block2a1.ENA0
wren_a => ram_block2a2.PORTAWE
wren_a => ram_block2a2.ENA0
wren_a => ram_block2a3.PORTAWE
wren_a => ram_block2a3.ENA0
wren_a => ram_block2a4.PORTAWE
wren_a => ram_block2a4.ENA0
wren_a => ram_block2a5.PORTAWE
wren_a => ram_block2a5.ENA0
wren_a => ram_block2a6.PORTAWE
wren_a => ram_block2a6.ENA0
wren_a => ram_block2a7.PORTAWE
wren_a => ram_block2a7.ENA0


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count
aclr => counter_reg_bit[5].IN0
clock => counter_reg_bit[5].CLK
clock => counter_reg_bit[4].CLK
clock => counter_reg_bit[3].CLK
clock => counter_reg_bit[2].CLK
clock => counter_reg_bit[1].CLK
clock => counter_reg_bit[0].CLK
cnt_en => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => _.IN0


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr
aclr => counter_reg_bit[5].IN0
clock => counter_reg_bit[5].CLK
clock => counter_reg_bit[4].CLK
clock => counter_reg_bit[3].CLK
clock => counter_reg_bit[2].CLK
clock => counter_reg_bit[1].CLK
clock => counter_reg_bit[0].CLK
cnt_en => _.IN1
sclr => _.IN0
sclr => _.IN0
sclr => _.IN0


|LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
raw_tck => write_stalled.CLK
raw_tck => wdata[0].CLK
raw_tck => wdata[1].CLK
raw_tck => wdata[2].CLK
raw_tck => wdata[3].CLK
raw_tck => wdata[4].CLK
raw_tck => wdata[5].CLK
raw_tck => wdata[6].CLK
raw_tck => wdata[7].CLK
raw_tck => read_write.CLK
raw_tck => read_req.CLK
raw_tck => write_valid.CLK
raw_tck => count[0].CLK
raw_tck => count[1].CLK
raw_tck => count[2].CLK
raw_tck => count[3].CLK
raw_tck => count[4].CLK
raw_tck => count[5].CLK
raw_tck => count[6].CLK
raw_tck => count[7].CLK
raw_tck => count[8].CLK
raw_tck => count[9].CLK
raw_tck => state.CLK
raw_tck => user_saw_rvalid.CLK
raw_tck => td_shift[0].CLK
raw_tck => td_shift[1].CLK
raw_tck => td_shift[2].CLK
raw_tck => td_shift[3].CLK
raw_tck => td_shift[4].CLK
raw_tck => td_shift[5].CLK
raw_tck => td_shift[6].CLK
raw_tck => td_shift[7].CLK
raw_tck => td_shift[8].CLK
raw_tck => td_shift[9].CLK
raw_tck => td_shift[10].CLK
raw_tck => jupdate.CLK
tck => ~NO_FANOUT~
tdi => td_shift.OUTPUTSELECT
tdi => count.OUTPUTSELECT
tdi => state.OUTPUTSELECT
tdi => wdata.DATAB
tdi => always0.IN1
tdi => wdata.DATAB
tdi => td_shift.DATAB
rti => ~NO_FANOUT~
shift => ~NO_FANOUT~
update => ~NO_FANOUT~
usr1 => always0.IN0
clr => jupdate.ACLR
clr => write_stalled.ACLR
clr => wdata[0].ACLR
clr => wdata[1].ACLR
clr => wdata[2].ACLR
clr => wdata[3].ACLR
clr => wdata[4].ACLR
clr => wdata[5].ACLR
clr => wdata[6].ACLR
clr => wdata[7].ACLR
clr => read_write.ACLR
clr => read_req.ACLR
clr => write_valid.ACLR
clr => count[0].ACLR
clr => count[1].ACLR
clr => count[2].ACLR
clr => count[3].ACLR
clr => count[4].ACLR
clr => count[5].ACLR
clr => count[6].ACLR
clr => count[7].ACLR
clr => count[8].ACLR
clr => count[9].PRESET
clr => state.ACLR
clr => user_saw_rvalid.ACLR
clr => td_shift[0].ACLR
clr => td_shift[1].ACLR
clr => td_shift[2].ACLR
clr => td_shift[3].ACLR
clr => td_shift[4].ACLR
clr => td_shift[5].ACLR
clr => td_shift[6].ACLR
clr => td_shift[7].ACLR
clr => td_shift[8].ACLR
clr => td_shift[9].ACLR
clr => td_shift[10].ACLR
ena => always0.IN1
ir_in[0] => Decoder1.IN0
ir_in[0] => ir_out[0].DATAIN
jtag_state_cdr => state.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => count.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_cdr => td_shift.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => count.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => td_shift.OUTPUTSELECT
jtag_state_sdr => read_write.OUTPUTSELECT
jtag_state_sdr => wdata.OUTPUTSELECT
jtag_state_sdr => wdata.OUTPUTSELECT
jtag_state_sdr => wdata.OUTPUTSELECT
jtag_state_sdr => wdata.OUTPUTSELECT
jtag_state_sdr => wdata.OUTPUTSELECT
jtag_state_sdr => wdata.OUTPUTSELECT
jtag_state_sdr => wdata.OUTPUTSELECT
jtag_state_sdr => wdata.OUTPUTSELECT
jtag_state_sdr => user_saw_rvalid.OUTPUTSELECT
jtag_state_sdr => write_valid.OUTPUTSELECT
jtag_state_sdr => read_req.OUTPUTSELECT
jtag_state_sdr => write_stalled.OUTPUTSELECT
jtag_state_sdr => state.OUTPUTSELECT
jtag_state_udr => jupdate.OUTPUTSELECT
clk => t_pause~reg0.CLK
clk => t_ena~reg0.CLK
clk => rdata[0].CLK
clk => rdata[1].CLK
clk => rdata[2].CLK
clk => rdata[3].CLK
clk => rdata[4].CLK
clk => rdata[5].CLK
clk => rdata[6].CLK
clk => rdata[7].CLK
clk => rvalid.CLK
clk => rvalid0.CLK
clk => r_ena1.CLK
clk => jupdate2.CLK
clk => jupdate1.CLK
clk => read_write2.CLK
clk => read_write1.CLK
clk => rst2.CLK
clk => rst1.CLK
rst_n => t_pause~reg0.ACLR
rst_n => t_ena~reg0.ACLR
rst_n => rdata[0].ACLR
rst_n => rdata[1].ACLR
rst_n => rdata[2].ACLR
rst_n => rdata[3].ACLR
rst_n => rdata[4].ACLR
rst_n => rdata[5].ACLR
rst_n => rdata[6].ACLR
rst_n => rdata[7].ACLR
rst_n => rvalid.ACLR
rst_n => rvalid0.ACLR
rst_n => r_ena1.ACLR
rst_n => jupdate2.ACLR
rst_n => jupdate1.ACLR
rst_n => read_write2.ACLR
rst_n => read_write1.ACLR
rst_n => rst2.PRESET
rst_n => rst1.PRESET
r_val => r_ena.IN1
r_dat[0] => rdata[0].DATAIN
r_dat[1] => rdata[1].DATAIN
r_dat[2] => rdata[2].DATAIN
r_dat[3] => rdata[3].DATAIN
r_dat[4] => rdata[4].DATAIN
r_dat[5] => rdata[5].DATAIN
r_dat[6] => rdata[6].DATAIN
r_dat[7] => rdata[7].DATAIN
t_dav => td_shift.DATAB
t_dav => always2.IN1
t_dav => always0.IN1


|LED_hello_world|CORE_SOPC:inst|lcd32_data_s1_arbitrator:the_lcd32_data_s1
clk => d1_lcd32_data_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => lcd32_data_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => lcd32_data_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN22
cpu_data_master_address_to_slave[5] => Equal0.IN21
cpu_data_master_address_to_slave[6] => Equal0.IN20
cpu_data_master_address_to_slave[7] => Equal0.IN2
cpu_data_master_address_to_slave[8] => Equal0.IN19
cpu_data_master_address_to_slave[9] => Equal0.IN18
cpu_data_master_address_to_slave[10] => Equal0.IN17
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN16
cpu_data_master_address_to_slave[14] => Equal0.IN15
cpu_data_master_address_to_slave[15] => Equal0.IN14
cpu_data_master_address_to_slave[16] => Equal0.IN13
cpu_data_master_address_to_slave[17] => Equal0.IN12
cpu_data_master_address_to_slave[18] => Equal0.IN11
cpu_data_master_address_to_slave[19] => Equal0.IN10
cpu_data_master_address_to_slave[20] => Equal0.IN9
cpu_data_master_address_to_slave[21] => Equal0.IN8
cpu_data_master_address_to_slave[22] => Equal0.IN7
cpu_data_master_address_to_slave[23] => Equal0.IN6
cpu_data_master_address_to_slave[24] => Equal0.IN5
cpu_data_master_address_to_slave[25] => Equal0.IN4
cpu_data_master_address_to_slave[26] => Equal0.IN3
cpu_data_master_read => cpu_data_master_requests_lcd32_data_s1.IN0
cpu_data_master_read => lcd32_data_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_lcd32_data_s1.IN0
cpu_data_master_write => cpu_data_master_requests_lcd32_data_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_lcd32_data_s1.IN1
cpu_data_master_write => lcd32_data_s1_write_n.IN1
cpu_data_master_writedata[0] => lcd32_data_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => lcd32_data_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => lcd32_data_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => lcd32_data_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => lcd32_data_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => lcd32_data_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => lcd32_data_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => lcd32_data_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => lcd32_data_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => lcd32_data_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => lcd32_data_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => lcd32_data_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => lcd32_data_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => lcd32_data_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => lcd32_data_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => lcd32_data_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => lcd32_data_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => lcd32_data_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => lcd32_data_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => lcd32_data_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => lcd32_data_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => lcd32_data_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => lcd32_data_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => lcd32_data_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => lcd32_data_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => lcd32_data_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => lcd32_data_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => lcd32_data_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => lcd32_data_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => lcd32_data_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => lcd32_data_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => lcd32_data_s1_writedata[31].DATAIN
lcd32_data_s1_readdata[0] => lcd32_data_s1_readdata_from_sa[0].DATAIN
lcd32_data_s1_readdata[1] => lcd32_data_s1_readdata_from_sa[1].DATAIN
lcd32_data_s1_readdata[2] => lcd32_data_s1_readdata_from_sa[2].DATAIN
lcd32_data_s1_readdata[3] => lcd32_data_s1_readdata_from_sa[3].DATAIN
lcd32_data_s1_readdata[4] => lcd32_data_s1_readdata_from_sa[4].DATAIN
lcd32_data_s1_readdata[5] => lcd32_data_s1_readdata_from_sa[5].DATAIN
lcd32_data_s1_readdata[6] => lcd32_data_s1_readdata_from_sa[6].DATAIN
lcd32_data_s1_readdata[7] => lcd32_data_s1_readdata_from_sa[7].DATAIN
lcd32_data_s1_readdata[8] => lcd32_data_s1_readdata_from_sa[8].DATAIN
lcd32_data_s1_readdata[9] => lcd32_data_s1_readdata_from_sa[9].DATAIN
lcd32_data_s1_readdata[10] => lcd32_data_s1_readdata_from_sa[10].DATAIN
lcd32_data_s1_readdata[11] => lcd32_data_s1_readdata_from_sa[11].DATAIN
lcd32_data_s1_readdata[12] => lcd32_data_s1_readdata_from_sa[12].DATAIN
lcd32_data_s1_readdata[13] => lcd32_data_s1_readdata_from_sa[13].DATAIN
lcd32_data_s1_readdata[14] => lcd32_data_s1_readdata_from_sa[14].DATAIN
lcd32_data_s1_readdata[15] => lcd32_data_s1_readdata_from_sa[15].DATAIN
lcd32_data_s1_readdata[16] => lcd32_data_s1_readdata_from_sa[16].DATAIN
lcd32_data_s1_readdata[17] => lcd32_data_s1_readdata_from_sa[17].DATAIN
lcd32_data_s1_readdata[18] => lcd32_data_s1_readdata_from_sa[18].DATAIN
lcd32_data_s1_readdata[19] => lcd32_data_s1_readdata_from_sa[19].DATAIN
lcd32_data_s1_readdata[20] => lcd32_data_s1_readdata_from_sa[20].DATAIN
lcd32_data_s1_readdata[21] => lcd32_data_s1_readdata_from_sa[21].DATAIN
lcd32_data_s1_readdata[22] => lcd32_data_s1_readdata_from_sa[22].DATAIN
lcd32_data_s1_readdata[23] => lcd32_data_s1_readdata_from_sa[23].DATAIN
lcd32_data_s1_readdata[24] => lcd32_data_s1_readdata_from_sa[24].DATAIN
lcd32_data_s1_readdata[25] => lcd32_data_s1_readdata_from_sa[25].DATAIN
lcd32_data_s1_readdata[26] => lcd32_data_s1_readdata_from_sa[26].DATAIN
lcd32_data_s1_readdata[27] => lcd32_data_s1_readdata_from_sa[27].DATAIN
lcd32_data_s1_readdata[28] => lcd32_data_s1_readdata_from_sa[28].DATAIN
lcd32_data_s1_readdata[29] => lcd32_data_s1_readdata_from_sa[29].DATAIN
lcd32_data_s1_readdata[30] => lcd32_data_s1_readdata_from_sa[30].DATAIN
lcd32_data_s1_readdata[31] => lcd32_data_s1_readdata_from_sa[31].DATAIN
reset_n => lcd32_data_s1_reset_n.DATAIN
reset_n => d1_lcd32_data_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR


|LED_hello_world|CORE_SOPC:inst|lcd32_data:the_lcd32_data
address[0] => Equal0.IN31
address[0] => Equal1.IN61
address[1] => Equal0.IN30
address[1] => Equal1.IN30
chipselect => always2.IN0
clk => data_dir[0].CLK
clk => data_dir[1].CLK
clk => data_dir[2].CLK
clk => data_dir[3].CLK
clk => data_dir[4].CLK
clk => data_dir[5].CLK
clk => data_dir[6].CLK
clk => data_dir[7].CLK
clk => data_dir[8].CLK
clk => data_dir[9].CLK
clk => data_dir[10].CLK
clk => data_dir[11].CLK
clk => data_dir[12].CLK
clk => data_dir[13].CLK
clk => data_dir[14].CLK
clk => data_dir[15].CLK
clk => data_out[0].CLK
clk => data_out[1].CLK
clk => data_out[2].CLK
clk => data_out[3].CLK
clk => data_out[4].CLK
clk => data_out[5].CLK
clk => data_out[6].CLK
clk => data_out[7].CLK
clk => data_out[8].CLK
clk => data_out[9].CLK
clk => data_out[10].CLK
clk => data_out[11].CLK
clk => data_out[12].CLK
clk => data_out[13].CLK
clk => data_out[14].CLK
clk => data_out[15].CLK
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
reset_n => data_dir[0].ACLR
reset_n => data_dir[1].ACLR
reset_n => data_dir[2].ACLR
reset_n => data_dir[3].ACLR
reset_n => data_dir[4].ACLR
reset_n => data_dir[5].ACLR
reset_n => data_dir[6].ACLR
reset_n => data_dir[7].ACLR
reset_n => data_dir[8].ACLR
reset_n => data_dir[9].ACLR
reset_n => data_dir[10].ACLR
reset_n => data_dir[11].ACLR
reset_n => data_dir[12].ACLR
reset_n => data_dir[13].ACLR
reset_n => data_dir[14].ACLR
reset_n => data_dir[15].ACLR
reset_n => data_out[0].ACLR
reset_n => data_out[1].ACLR
reset_n => data_out[2].ACLR
reset_n => data_out[3].ACLR
reset_n => data_out[4].ACLR
reset_n => data_out[5].ACLR
reset_n => data_out[6].ACLR
reset_n => data_out[7].ACLR
reset_n => data_out[8].ACLR
reset_n => data_out[9].ACLR
reset_n => data_out[10].ACLR
reset_n => data_out[11].ACLR
reset_n => data_out[12].ACLR
reset_n => data_out[13].ACLR
reset_n => data_out[14].ACLR
reset_n => data_out[15].ACLR
write_n => always2.IN1
writedata[0] => data_dir[0].DATAIN
writedata[0] => data_out[0].DATAIN
writedata[1] => data_out[1].DATAIN
writedata[1] => data_dir[1].DATAIN
writedata[2] => data_out[2].DATAIN
writedata[2] => data_dir[2].DATAIN
writedata[3] => data_out[3].DATAIN
writedata[3] => data_dir[3].DATAIN
writedata[4] => data_out[4].DATAIN
writedata[4] => data_dir[4].DATAIN
writedata[5] => data_out[5].DATAIN
writedata[5] => data_dir[5].DATAIN
writedata[6] => data_out[6].DATAIN
writedata[6] => data_dir[6].DATAIN
writedata[7] => data_out[7].DATAIN
writedata[7] => data_dir[7].DATAIN
writedata[8] => data_out[8].DATAIN
writedata[8] => data_dir[8].DATAIN
writedata[9] => data_out[9].DATAIN
writedata[9] => data_dir[9].DATAIN
writedata[10] => data_out[10].DATAIN
writedata[10] => data_dir[10].DATAIN
writedata[11] => data_out[11].DATAIN
writedata[11] => data_dir[11].DATAIN
writedata[12] => data_out[12].DATAIN
writedata[12] => data_dir[12].DATAIN
writedata[13] => data_out[13].DATAIN
writedata[13] => data_dir[13].DATAIN
writedata[14] => data_out[14].DATAIN
writedata[14] => data_dir[14].DATAIN
writedata[15] => data_out[15].DATAIN
writedata[15] => data_dir[15].DATAIN
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~
bidir_port[0] <> bidir_port[0]
bidir_port[1] <> bidir_port[1]
bidir_port[2] <> bidir_port[2]
bidir_port[3] <> bidir_port[3]
bidir_port[4] <> bidir_port[4]
bidir_port[5] <> bidir_port[5]
bidir_port[6] <> bidir_port[6]
bidir_port[7] <> bidir_port[7]
bidir_port[8] <> bidir_port[8]
bidir_port[9] <> bidir_port[9]
bidir_port[10] <> bidir_port[10]
bidir_port[11] <> bidir_port[11]
bidir_port[12] <> bidir_port[12]
bidir_port[13] <> bidir_port[13]
bidir_port[14] <> bidir_port[14]
bidir_port[15] <> bidir_port[15]


|LED_hello_world|CORE_SOPC:inst|lcd_cs_s1_arbitrator:the_lcd_cs_s1
clk => d1_lcd_cs_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => lcd_cs_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => lcd_cs_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN22
cpu_data_master_address_to_slave[5] => Equal0.IN2
cpu_data_master_address_to_slave[6] => Equal0.IN21
cpu_data_master_address_to_slave[7] => Equal0.IN20
cpu_data_master_address_to_slave[8] => Equal0.IN19
cpu_data_master_address_to_slave[9] => Equal0.IN18
cpu_data_master_address_to_slave[10] => Equal0.IN17
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN16
cpu_data_master_address_to_slave[14] => Equal0.IN15
cpu_data_master_address_to_slave[15] => Equal0.IN14
cpu_data_master_address_to_slave[16] => Equal0.IN13
cpu_data_master_address_to_slave[17] => Equal0.IN12
cpu_data_master_address_to_slave[18] => Equal0.IN11
cpu_data_master_address_to_slave[19] => Equal0.IN10
cpu_data_master_address_to_slave[20] => Equal0.IN9
cpu_data_master_address_to_slave[21] => Equal0.IN8
cpu_data_master_address_to_slave[22] => Equal0.IN7
cpu_data_master_address_to_slave[23] => Equal0.IN6
cpu_data_master_address_to_slave[24] => Equal0.IN5
cpu_data_master_address_to_slave[25] => Equal0.IN4
cpu_data_master_address_to_slave[26] => Equal0.IN3
cpu_data_master_read => cpu_data_master_requests_lcd_cs_s1.IN0
cpu_data_master_read => lcd_cs_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_lcd_cs_s1.IN0
cpu_data_master_write => cpu_data_master_requests_lcd_cs_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_lcd_cs_s1.IN1
cpu_data_master_write => lcd_cs_s1_write_n.IN1
cpu_data_master_writedata[0] => lcd_cs_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => lcd_cs_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => lcd_cs_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => lcd_cs_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => lcd_cs_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => lcd_cs_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => lcd_cs_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => lcd_cs_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => lcd_cs_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => lcd_cs_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => lcd_cs_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => lcd_cs_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => lcd_cs_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => lcd_cs_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => lcd_cs_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => lcd_cs_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => lcd_cs_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => lcd_cs_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => lcd_cs_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => lcd_cs_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => lcd_cs_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => lcd_cs_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => lcd_cs_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => lcd_cs_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => lcd_cs_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => lcd_cs_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => lcd_cs_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => lcd_cs_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => lcd_cs_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => lcd_cs_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => lcd_cs_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => lcd_cs_s1_writedata[31].DATAIN
lcd_cs_s1_readdata[0] => lcd_cs_s1_readdata_from_sa[0].DATAIN
lcd_cs_s1_readdata[1] => lcd_cs_s1_readdata_from_sa[1].DATAIN
lcd_cs_s1_readdata[2] => lcd_cs_s1_readdata_from_sa[2].DATAIN
lcd_cs_s1_readdata[3] => lcd_cs_s1_readdata_from_sa[3].DATAIN
lcd_cs_s1_readdata[4] => lcd_cs_s1_readdata_from_sa[4].DATAIN
lcd_cs_s1_readdata[5] => lcd_cs_s1_readdata_from_sa[5].DATAIN
lcd_cs_s1_readdata[6] => lcd_cs_s1_readdata_from_sa[6].DATAIN
lcd_cs_s1_readdata[7] => lcd_cs_s1_readdata_from_sa[7].DATAIN
lcd_cs_s1_readdata[8] => lcd_cs_s1_readdata_from_sa[8].DATAIN
lcd_cs_s1_readdata[9] => lcd_cs_s1_readdata_from_sa[9].DATAIN
lcd_cs_s1_readdata[10] => lcd_cs_s1_readdata_from_sa[10].DATAIN
lcd_cs_s1_readdata[11] => lcd_cs_s1_readdata_from_sa[11].DATAIN
lcd_cs_s1_readdata[12] => lcd_cs_s1_readdata_from_sa[12].DATAIN
lcd_cs_s1_readdata[13] => lcd_cs_s1_readdata_from_sa[13].DATAIN
lcd_cs_s1_readdata[14] => lcd_cs_s1_readdata_from_sa[14].DATAIN
lcd_cs_s1_readdata[15] => lcd_cs_s1_readdata_from_sa[15].DATAIN
lcd_cs_s1_readdata[16] => lcd_cs_s1_readdata_from_sa[16].DATAIN
lcd_cs_s1_readdata[17] => lcd_cs_s1_readdata_from_sa[17].DATAIN
lcd_cs_s1_readdata[18] => lcd_cs_s1_readdata_from_sa[18].DATAIN
lcd_cs_s1_readdata[19] => lcd_cs_s1_readdata_from_sa[19].DATAIN
lcd_cs_s1_readdata[20] => lcd_cs_s1_readdata_from_sa[20].DATAIN
lcd_cs_s1_readdata[21] => lcd_cs_s1_readdata_from_sa[21].DATAIN
lcd_cs_s1_readdata[22] => lcd_cs_s1_readdata_from_sa[22].DATAIN
lcd_cs_s1_readdata[23] => lcd_cs_s1_readdata_from_sa[23].DATAIN
lcd_cs_s1_readdata[24] => lcd_cs_s1_readdata_from_sa[24].DATAIN
lcd_cs_s1_readdata[25] => lcd_cs_s1_readdata_from_sa[25].DATAIN
lcd_cs_s1_readdata[26] => lcd_cs_s1_readdata_from_sa[26].DATAIN
lcd_cs_s1_readdata[27] => lcd_cs_s1_readdata_from_sa[27].DATAIN
lcd_cs_s1_readdata[28] => lcd_cs_s1_readdata_from_sa[28].DATAIN
lcd_cs_s1_readdata[29] => lcd_cs_s1_readdata_from_sa[29].DATAIN
lcd_cs_s1_readdata[30] => lcd_cs_s1_readdata_from_sa[30].DATAIN
lcd_cs_s1_readdata[31] => lcd_cs_s1_readdata_from_sa[31].DATAIN
reset_n => lcd_cs_s1_reset_n.DATAIN
reset_n => d1_lcd_cs_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR


|LED_hello_world|CORE_SOPC:inst|lcd_cs:the_lcd_cs
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|lcd_rd_s1_arbitrator:the_lcd_rd_s1
clk => d1_lcd_rd_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => lcd_rd_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => lcd_rd_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN3
cpu_data_master_address_to_slave[5] => Equal0.IN22
cpu_data_master_address_to_slave[6] => Equal0.IN21
cpu_data_master_address_to_slave[7] => Equal0.IN2
cpu_data_master_address_to_slave[8] => Equal0.IN20
cpu_data_master_address_to_slave[9] => Equal0.IN19
cpu_data_master_address_to_slave[10] => Equal0.IN18
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN17
cpu_data_master_address_to_slave[14] => Equal0.IN16
cpu_data_master_address_to_slave[15] => Equal0.IN15
cpu_data_master_address_to_slave[16] => Equal0.IN14
cpu_data_master_address_to_slave[17] => Equal0.IN13
cpu_data_master_address_to_slave[18] => Equal0.IN12
cpu_data_master_address_to_slave[19] => Equal0.IN11
cpu_data_master_address_to_slave[20] => Equal0.IN10
cpu_data_master_address_to_slave[21] => Equal0.IN9
cpu_data_master_address_to_slave[22] => Equal0.IN8
cpu_data_master_address_to_slave[23] => Equal0.IN7
cpu_data_master_address_to_slave[24] => Equal0.IN6
cpu_data_master_address_to_slave[25] => Equal0.IN5
cpu_data_master_address_to_slave[26] => Equal0.IN4
cpu_data_master_read => cpu_data_master_requests_lcd_rd_s1.IN0
cpu_data_master_read => lcd_rd_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_lcd_rd_s1.IN0
cpu_data_master_write => cpu_data_master_requests_lcd_rd_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_lcd_rd_s1.IN1
cpu_data_master_write => lcd_rd_s1_write_n.IN1
cpu_data_master_writedata[0] => lcd_rd_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => lcd_rd_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => lcd_rd_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => lcd_rd_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => lcd_rd_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => lcd_rd_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => lcd_rd_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => lcd_rd_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => lcd_rd_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => lcd_rd_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => lcd_rd_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => lcd_rd_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => lcd_rd_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => lcd_rd_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => lcd_rd_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => lcd_rd_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => lcd_rd_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => lcd_rd_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => lcd_rd_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => lcd_rd_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => lcd_rd_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => lcd_rd_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => lcd_rd_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => lcd_rd_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => lcd_rd_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => lcd_rd_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => lcd_rd_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => lcd_rd_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => lcd_rd_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => lcd_rd_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => lcd_rd_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => lcd_rd_s1_writedata[31].DATAIN
lcd_rd_s1_readdata[0] => lcd_rd_s1_readdata_from_sa[0].DATAIN
lcd_rd_s1_readdata[1] => lcd_rd_s1_readdata_from_sa[1].DATAIN
lcd_rd_s1_readdata[2] => lcd_rd_s1_readdata_from_sa[2].DATAIN
lcd_rd_s1_readdata[3] => lcd_rd_s1_readdata_from_sa[3].DATAIN
lcd_rd_s1_readdata[4] => lcd_rd_s1_readdata_from_sa[4].DATAIN
lcd_rd_s1_readdata[5] => lcd_rd_s1_readdata_from_sa[5].DATAIN
lcd_rd_s1_readdata[6] => lcd_rd_s1_readdata_from_sa[6].DATAIN
lcd_rd_s1_readdata[7] => lcd_rd_s1_readdata_from_sa[7].DATAIN
lcd_rd_s1_readdata[8] => lcd_rd_s1_readdata_from_sa[8].DATAIN
lcd_rd_s1_readdata[9] => lcd_rd_s1_readdata_from_sa[9].DATAIN
lcd_rd_s1_readdata[10] => lcd_rd_s1_readdata_from_sa[10].DATAIN
lcd_rd_s1_readdata[11] => lcd_rd_s1_readdata_from_sa[11].DATAIN
lcd_rd_s1_readdata[12] => lcd_rd_s1_readdata_from_sa[12].DATAIN
lcd_rd_s1_readdata[13] => lcd_rd_s1_readdata_from_sa[13].DATAIN
lcd_rd_s1_readdata[14] => lcd_rd_s1_readdata_from_sa[14].DATAIN
lcd_rd_s1_readdata[15] => lcd_rd_s1_readdata_from_sa[15].DATAIN
lcd_rd_s1_readdata[16] => lcd_rd_s1_readdata_from_sa[16].DATAIN
lcd_rd_s1_readdata[17] => lcd_rd_s1_readdata_from_sa[17].DATAIN
lcd_rd_s1_readdata[18] => lcd_rd_s1_readdata_from_sa[18].DATAIN
lcd_rd_s1_readdata[19] => lcd_rd_s1_readdata_from_sa[19].DATAIN
lcd_rd_s1_readdata[20] => lcd_rd_s1_readdata_from_sa[20].DATAIN
lcd_rd_s1_readdata[21] => lcd_rd_s1_readdata_from_sa[21].DATAIN
lcd_rd_s1_readdata[22] => lcd_rd_s1_readdata_from_sa[22].DATAIN
lcd_rd_s1_readdata[23] => lcd_rd_s1_readdata_from_sa[23].DATAIN
lcd_rd_s1_readdata[24] => lcd_rd_s1_readdata_from_sa[24].DATAIN
lcd_rd_s1_readdata[25] => lcd_rd_s1_readdata_from_sa[25].DATAIN
lcd_rd_s1_readdata[26] => lcd_rd_s1_readdata_from_sa[26].DATAIN
lcd_rd_s1_readdata[27] => lcd_rd_s1_readdata_from_sa[27].DATAIN
lcd_rd_s1_readdata[28] => lcd_rd_s1_readdata_from_sa[28].DATAIN
lcd_rd_s1_readdata[29] => lcd_rd_s1_readdata_from_sa[29].DATAIN
lcd_rd_s1_readdata[30] => lcd_rd_s1_readdata_from_sa[30].DATAIN
lcd_rd_s1_readdata[31] => lcd_rd_s1_readdata_from_sa[31].DATAIN
reset_n => lcd_rd_s1_reset_n.DATAIN
reset_n => d1_lcd_rd_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR


|LED_hello_world|CORE_SOPC:inst|lcd_rd:the_lcd_rd
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|lcd_rs_s1_arbitrator:the_lcd_rs_s1
clk => d1_lcd_rs_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => lcd_rs_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => lcd_rs_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN22
cpu_data_master_address_to_slave[5] => Equal0.IN21
cpu_data_master_address_to_slave[6] => Equal0.IN2
cpu_data_master_address_to_slave[7] => Equal0.IN20
cpu_data_master_address_to_slave[8] => Equal0.IN19
cpu_data_master_address_to_slave[9] => Equal0.IN18
cpu_data_master_address_to_slave[10] => Equal0.IN17
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN16
cpu_data_master_address_to_slave[14] => Equal0.IN15
cpu_data_master_address_to_slave[15] => Equal0.IN14
cpu_data_master_address_to_slave[16] => Equal0.IN13
cpu_data_master_address_to_slave[17] => Equal0.IN12
cpu_data_master_address_to_slave[18] => Equal0.IN11
cpu_data_master_address_to_slave[19] => Equal0.IN10
cpu_data_master_address_to_slave[20] => Equal0.IN9
cpu_data_master_address_to_slave[21] => Equal0.IN8
cpu_data_master_address_to_slave[22] => Equal0.IN7
cpu_data_master_address_to_slave[23] => Equal0.IN6
cpu_data_master_address_to_slave[24] => Equal0.IN5
cpu_data_master_address_to_slave[25] => Equal0.IN4
cpu_data_master_address_to_slave[26] => Equal0.IN3
cpu_data_master_read => cpu_data_master_requests_lcd_rs_s1.IN0
cpu_data_master_read => lcd_rs_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_lcd_rs_s1.IN0
cpu_data_master_write => cpu_data_master_requests_lcd_rs_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_lcd_rs_s1.IN1
cpu_data_master_write => lcd_rs_s1_write_n.IN1
cpu_data_master_writedata[0] => lcd_rs_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => lcd_rs_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => lcd_rs_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => lcd_rs_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => lcd_rs_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => lcd_rs_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => lcd_rs_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => lcd_rs_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => lcd_rs_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => lcd_rs_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => lcd_rs_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => lcd_rs_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => lcd_rs_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => lcd_rs_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => lcd_rs_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => lcd_rs_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => lcd_rs_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => lcd_rs_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => lcd_rs_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => lcd_rs_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => lcd_rs_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => lcd_rs_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => lcd_rs_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => lcd_rs_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => lcd_rs_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => lcd_rs_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => lcd_rs_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => lcd_rs_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => lcd_rs_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => lcd_rs_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => lcd_rs_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => lcd_rs_s1_writedata[31].DATAIN
lcd_rs_s1_readdata[0] => lcd_rs_s1_readdata_from_sa[0].DATAIN
lcd_rs_s1_readdata[1] => lcd_rs_s1_readdata_from_sa[1].DATAIN
lcd_rs_s1_readdata[2] => lcd_rs_s1_readdata_from_sa[2].DATAIN
lcd_rs_s1_readdata[3] => lcd_rs_s1_readdata_from_sa[3].DATAIN
lcd_rs_s1_readdata[4] => lcd_rs_s1_readdata_from_sa[4].DATAIN
lcd_rs_s1_readdata[5] => lcd_rs_s1_readdata_from_sa[5].DATAIN
lcd_rs_s1_readdata[6] => lcd_rs_s1_readdata_from_sa[6].DATAIN
lcd_rs_s1_readdata[7] => lcd_rs_s1_readdata_from_sa[7].DATAIN
lcd_rs_s1_readdata[8] => lcd_rs_s1_readdata_from_sa[8].DATAIN
lcd_rs_s1_readdata[9] => lcd_rs_s1_readdata_from_sa[9].DATAIN
lcd_rs_s1_readdata[10] => lcd_rs_s1_readdata_from_sa[10].DATAIN
lcd_rs_s1_readdata[11] => lcd_rs_s1_readdata_from_sa[11].DATAIN
lcd_rs_s1_readdata[12] => lcd_rs_s1_readdata_from_sa[12].DATAIN
lcd_rs_s1_readdata[13] => lcd_rs_s1_readdata_from_sa[13].DATAIN
lcd_rs_s1_readdata[14] => lcd_rs_s1_readdata_from_sa[14].DATAIN
lcd_rs_s1_readdata[15] => lcd_rs_s1_readdata_from_sa[15].DATAIN
lcd_rs_s1_readdata[16] => lcd_rs_s1_readdata_from_sa[16].DATAIN
lcd_rs_s1_readdata[17] => lcd_rs_s1_readdata_from_sa[17].DATAIN
lcd_rs_s1_readdata[18] => lcd_rs_s1_readdata_from_sa[18].DATAIN
lcd_rs_s1_readdata[19] => lcd_rs_s1_readdata_from_sa[19].DATAIN
lcd_rs_s1_readdata[20] => lcd_rs_s1_readdata_from_sa[20].DATAIN
lcd_rs_s1_readdata[21] => lcd_rs_s1_readdata_from_sa[21].DATAIN
lcd_rs_s1_readdata[22] => lcd_rs_s1_readdata_from_sa[22].DATAIN
lcd_rs_s1_readdata[23] => lcd_rs_s1_readdata_from_sa[23].DATAIN
lcd_rs_s1_readdata[24] => lcd_rs_s1_readdata_from_sa[24].DATAIN
lcd_rs_s1_readdata[25] => lcd_rs_s1_readdata_from_sa[25].DATAIN
lcd_rs_s1_readdata[26] => lcd_rs_s1_readdata_from_sa[26].DATAIN
lcd_rs_s1_readdata[27] => lcd_rs_s1_readdata_from_sa[27].DATAIN
lcd_rs_s1_readdata[28] => lcd_rs_s1_readdata_from_sa[28].DATAIN
lcd_rs_s1_readdata[29] => lcd_rs_s1_readdata_from_sa[29].DATAIN
lcd_rs_s1_readdata[30] => lcd_rs_s1_readdata_from_sa[30].DATAIN
lcd_rs_s1_readdata[31] => lcd_rs_s1_readdata_from_sa[31].DATAIN
reset_n => lcd_rs_s1_reset_n.DATAIN
reset_n => d1_lcd_rs_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR


|LED_hello_world|CORE_SOPC:inst|lcd_rs:the_lcd_rs
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|lcd_wr_s1_arbitrator:the_lcd_wr_s1
clk => d1_lcd_wr_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => lcd_wr_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => lcd_wr_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN4
cpu_data_master_address_to_slave[5] => Equal0.IN3
cpu_data_master_address_to_slave[6] => Equal0.IN2
cpu_data_master_address_to_slave[7] => Equal0.IN22
cpu_data_master_address_to_slave[8] => Equal0.IN21
cpu_data_master_address_to_slave[9] => Equal0.IN20
cpu_data_master_address_to_slave[10] => Equal0.IN19
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN18
cpu_data_master_address_to_slave[14] => Equal0.IN17
cpu_data_master_address_to_slave[15] => Equal0.IN16
cpu_data_master_address_to_slave[16] => Equal0.IN15
cpu_data_master_address_to_slave[17] => Equal0.IN14
cpu_data_master_address_to_slave[18] => Equal0.IN13
cpu_data_master_address_to_slave[19] => Equal0.IN12
cpu_data_master_address_to_slave[20] => Equal0.IN11
cpu_data_master_address_to_slave[21] => Equal0.IN10
cpu_data_master_address_to_slave[22] => Equal0.IN9
cpu_data_master_address_to_slave[23] => Equal0.IN8
cpu_data_master_address_to_slave[24] => Equal0.IN7
cpu_data_master_address_to_slave[25] => Equal0.IN6
cpu_data_master_address_to_slave[26] => Equal0.IN5
cpu_data_master_read => cpu_data_master_requests_lcd_wr_s1.IN0
cpu_data_master_read => lcd_wr_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_lcd_wr_s1.IN0
cpu_data_master_write => cpu_data_master_requests_lcd_wr_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_lcd_wr_s1.IN1
cpu_data_master_write => lcd_wr_s1_write_n.IN1
cpu_data_master_writedata[0] => lcd_wr_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => lcd_wr_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => lcd_wr_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => lcd_wr_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => lcd_wr_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => lcd_wr_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => lcd_wr_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => lcd_wr_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => lcd_wr_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => lcd_wr_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => lcd_wr_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => lcd_wr_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => lcd_wr_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => lcd_wr_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => lcd_wr_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => lcd_wr_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => lcd_wr_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => lcd_wr_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => lcd_wr_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => lcd_wr_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => lcd_wr_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => lcd_wr_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => lcd_wr_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => lcd_wr_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => lcd_wr_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => lcd_wr_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => lcd_wr_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => lcd_wr_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => lcd_wr_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => lcd_wr_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => lcd_wr_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => lcd_wr_s1_writedata[31].DATAIN
lcd_wr_s1_readdata[0] => lcd_wr_s1_readdata_from_sa[0].DATAIN
lcd_wr_s1_readdata[1] => lcd_wr_s1_readdata_from_sa[1].DATAIN
lcd_wr_s1_readdata[2] => lcd_wr_s1_readdata_from_sa[2].DATAIN
lcd_wr_s1_readdata[3] => lcd_wr_s1_readdata_from_sa[3].DATAIN
lcd_wr_s1_readdata[4] => lcd_wr_s1_readdata_from_sa[4].DATAIN
lcd_wr_s1_readdata[5] => lcd_wr_s1_readdata_from_sa[5].DATAIN
lcd_wr_s1_readdata[6] => lcd_wr_s1_readdata_from_sa[6].DATAIN
lcd_wr_s1_readdata[7] => lcd_wr_s1_readdata_from_sa[7].DATAIN
lcd_wr_s1_readdata[8] => lcd_wr_s1_readdata_from_sa[8].DATAIN
lcd_wr_s1_readdata[9] => lcd_wr_s1_readdata_from_sa[9].DATAIN
lcd_wr_s1_readdata[10] => lcd_wr_s1_readdata_from_sa[10].DATAIN
lcd_wr_s1_readdata[11] => lcd_wr_s1_readdata_from_sa[11].DATAIN
lcd_wr_s1_readdata[12] => lcd_wr_s1_readdata_from_sa[12].DATAIN
lcd_wr_s1_readdata[13] => lcd_wr_s1_readdata_from_sa[13].DATAIN
lcd_wr_s1_readdata[14] => lcd_wr_s1_readdata_from_sa[14].DATAIN
lcd_wr_s1_readdata[15] => lcd_wr_s1_readdata_from_sa[15].DATAIN
lcd_wr_s1_readdata[16] => lcd_wr_s1_readdata_from_sa[16].DATAIN
lcd_wr_s1_readdata[17] => lcd_wr_s1_readdata_from_sa[17].DATAIN
lcd_wr_s1_readdata[18] => lcd_wr_s1_readdata_from_sa[18].DATAIN
lcd_wr_s1_readdata[19] => lcd_wr_s1_readdata_from_sa[19].DATAIN
lcd_wr_s1_readdata[20] => lcd_wr_s1_readdata_from_sa[20].DATAIN
lcd_wr_s1_readdata[21] => lcd_wr_s1_readdata_from_sa[21].DATAIN
lcd_wr_s1_readdata[22] => lcd_wr_s1_readdata_from_sa[22].DATAIN
lcd_wr_s1_readdata[23] => lcd_wr_s1_readdata_from_sa[23].DATAIN
lcd_wr_s1_readdata[24] => lcd_wr_s1_readdata_from_sa[24].DATAIN
lcd_wr_s1_readdata[25] => lcd_wr_s1_readdata_from_sa[25].DATAIN
lcd_wr_s1_readdata[26] => lcd_wr_s1_readdata_from_sa[26].DATAIN
lcd_wr_s1_readdata[27] => lcd_wr_s1_readdata_from_sa[27].DATAIN
lcd_wr_s1_readdata[28] => lcd_wr_s1_readdata_from_sa[28].DATAIN
lcd_wr_s1_readdata[29] => lcd_wr_s1_readdata_from_sa[29].DATAIN
lcd_wr_s1_readdata[30] => lcd_wr_s1_readdata_from_sa[30].DATAIN
lcd_wr_s1_readdata[31] => lcd_wr_s1_readdata_from_sa[31].DATAIN
reset_n => lcd_wr_s1_reset_n.DATAIN
reset_n => d1_lcd_wr_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR


|LED_hello_world|CORE_SOPC:inst|lcd_wr:the_lcd_wr
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|reset_s1_arbitrator:the_reset_s1
clk => d1_reset_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => reset_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => reset_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN22
cpu_data_master_address_to_slave[5] => Equal0.IN3
cpu_data_master_address_to_slave[6] => Equal0.IN2
cpu_data_master_address_to_slave[7] => Equal0.IN21
cpu_data_master_address_to_slave[8] => Equal0.IN20
cpu_data_master_address_to_slave[9] => Equal0.IN19
cpu_data_master_address_to_slave[10] => Equal0.IN18
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN17
cpu_data_master_address_to_slave[14] => Equal0.IN16
cpu_data_master_address_to_slave[15] => Equal0.IN15
cpu_data_master_address_to_slave[16] => Equal0.IN14
cpu_data_master_address_to_slave[17] => Equal0.IN13
cpu_data_master_address_to_slave[18] => Equal0.IN12
cpu_data_master_address_to_slave[19] => Equal0.IN11
cpu_data_master_address_to_slave[20] => Equal0.IN10
cpu_data_master_address_to_slave[21] => Equal0.IN9
cpu_data_master_address_to_slave[22] => Equal0.IN8
cpu_data_master_address_to_slave[23] => Equal0.IN7
cpu_data_master_address_to_slave[24] => Equal0.IN6
cpu_data_master_address_to_slave[25] => Equal0.IN5
cpu_data_master_address_to_slave[26] => Equal0.IN4
cpu_data_master_read => cpu_data_master_requests_reset_s1.IN0
cpu_data_master_read => reset_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_reset_s1.IN0
cpu_data_master_write => cpu_data_master_requests_reset_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_reset_s1.IN1
cpu_data_master_write => reset_s1_write_n.IN1
cpu_data_master_writedata[0] => reset_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => reset_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => reset_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => reset_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => reset_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => reset_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => reset_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => reset_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => reset_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => reset_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => reset_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => reset_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => reset_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => reset_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => reset_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => reset_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => reset_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => reset_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => reset_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => reset_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => reset_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => reset_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => reset_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => reset_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => reset_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => reset_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => reset_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => reset_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => reset_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => reset_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => reset_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => reset_s1_writedata[31].DATAIN
reset_n => reset_s1_reset_n.DATAIN
reset_n => d1_reset_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR
reset_s1_readdata[0] => reset_s1_readdata_from_sa[0].DATAIN
reset_s1_readdata[1] => reset_s1_readdata_from_sa[1].DATAIN
reset_s1_readdata[2] => reset_s1_readdata_from_sa[2].DATAIN
reset_s1_readdata[3] => reset_s1_readdata_from_sa[3].DATAIN
reset_s1_readdata[4] => reset_s1_readdata_from_sa[4].DATAIN
reset_s1_readdata[5] => reset_s1_readdata_from_sa[5].DATAIN
reset_s1_readdata[6] => reset_s1_readdata_from_sa[6].DATAIN
reset_s1_readdata[7] => reset_s1_readdata_from_sa[7].DATAIN
reset_s1_readdata[8] => reset_s1_readdata_from_sa[8].DATAIN
reset_s1_readdata[9] => reset_s1_readdata_from_sa[9].DATAIN
reset_s1_readdata[10] => reset_s1_readdata_from_sa[10].DATAIN
reset_s1_readdata[11] => reset_s1_readdata_from_sa[11].DATAIN
reset_s1_readdata[12] => reset_s1_readdata_from_sa[12].DATAIN
reset_s1_readdata[13] => reset_s1_readdata_from_sa[13].DATAIN
reset_s1_readdata[14] => reset_s1_readdata_from_sa[14].DATAIN
reset_s1_readdata[15] => reset_s1_readdata_from_sa[15].DATAIN
reset_s1_readdata[16] => reset_s1_readdata_from_sa[16].DATAIN
reset_s1_readdata[17] => reset_s1_readdata_from_sa[17].DATAIN
reset_s1_readdata[18] => reset_s1_readdata_from_sa[18].DATAIN
reset_s1_readdata[19] => reset_s1_readdata_from_sa[19].DATAIN
reset_s1_readdata[20] => reset_s1_readdata_from_sa[20].DATAIN
reset_s1_readdata[21] => reset_s1_readdata_from_sa[21].DATAIN
reset_s1_readdata[22] => reset_s1_readdata_from_sa[22].DATAIN
reset_s1_readdata[23] => reset_s1_readdata_from_sa[23].DATAIN
reset_s1_readdata[24] => reset_s1_readdata_from_sa[24].DATAIN
reset_s1_readdata[25] => reset_s1_readdata_from_sa[25].DATAIN
reset_s1_readdata[26] => reset_s1_readdata_from_sa[26].DATAIN
reset_s1_readdata[27] => reset_s1_readdata_from_sa[27].DATAIN
reset_s1_readdata[28] => reset_s1_readdata_from_sa[28].DATAIN
reset_s1_readdata[29] => reset_s1_readdata_from_sa[29].DATAIN
reset_s1_readdata[30] => reset_s1_readdata_from_sa[30].DATAIN
reset_s1_readdata[31] => reset_s1_readdata_from_sa[31].DATAIN


|LED_hello_world|CORE_SOPC:inst|reset:the_reset
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1
clk => clk.IN2
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[3] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[4] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[5] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[6] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[7] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[8] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[9] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[10] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[11] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[12] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[13] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[14] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[15] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[16] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[17] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[18] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[19] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[20] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[21] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[22] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[23] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[24] => sdram_s1_address.DATAB
cpu_data_master_address_to_slave[25] => Equal0.IN1
cpu_data_master_address_to_slave[26] => Equal0.IN0
cpu_data_master_byteenable[0] => cpu_data_master_byteenable_sdram_s1.DATAB
cpu_data_master_byteenable[1] => cpu_data_master_byteenable_sdram_s1.DATAB
cpu_data_master_byteenable[2] => cpu_data_master_byteenable_sdram_s1.DATAA
cpu_data_master_byteenable[3] => cpu_data_master_byteenable_sdram_s1.DATAA
cpu_data_master_dbs_address[0] => ~NO_FANOUT~
cpu_data_master_dbs_address[1] => sdram_s1_address.DATAB
cpu_data_master_dbs_address[1] => cpu_data_master_byteenable_sdram_s1.OUTPUTSELECT
cpu_data_master_dbs_address[1] => cpu_data_master_byteenable_sdram_s1.OUTPUTSELECT
cpu_data_master_dbs_write_16[0] => sdram_s1_writedata[0].DATAIN
cpu_data_master_dbs_write_16[1] => sdram_s1_writedata[1].DATAIN
cpu_data_master_dbs_write_16[2] => sdram_s1_writedata[2].DATAIN
cpu_data_master_dbs_write_16[3] => sdram_s1_writedata[3].DATAIN
cpu_data_master_dbs_write_16[4] => sdram_s1_writedata[4].DATAIN
cpu_data_master_dbs_write_16[5] => sdram_s1_writedata[5].DATAIN
cpu_data_master_dbs_write_16[6] => sdram_s1_writedata[6].DATAIN
cpu_data_master_dbs_write_16[7] => sdram_s1_writedata[7].DATAIN
cpu_data_master_dbs_write_16[8] => sdram_s1_writedata[8].DATAIN
cpu_data_master_dbs_write_16[9] => sdram_s1_writedata[9].DATAIN
cpu_data_master_dbs_write_16[10] => sdram_s1_writedata[10].DATAIN
cpu_data_master_dbs_write_16[11] => sdram_s1_writedata[11].DATAIN
cpu_data_master_dbs_write_16[12] => sdram_s1_writedata[12].DATAIN
cpu_data_master_dbs_write_16[13] => sdram_s1_writedata[13].DATAIN
cpu_data_master_dbs_write_16[14] => sdram_s1_writedata[14].DATAIN
cpu_data_master_dbs_write_16[15] => sdram_s1_writedata[15].DATAIN
cpu_data_master_no_byte_enables_and_last_term => cpu_data_master_qualified_request_sdram_s1.IN0
cpu_data_master_read => cpu_data_master_requests_sdram_s1.IN0
cpu_data_master_read => cpu_data_master_qualified_request_sdram_s1.IN1
cpu_data_master_read => sdram_s1_in_a_read_cycle.IN0
cpu_data_master_waitrequest => cpu_data_master_qualified_request_sdram_s1.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_sdram_s1.IN1
cpu_data_master_write => cpu_data_master_requests_sdram_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_sdram_s1.IN1
cpu_data_master_write => in_a_write_cycle.IN0
cpu_instruction_master_address_to_slave[0] => ~NO_FANOUT~
cpu_instruction_master_address_to_slave[1] => ~NO_FANOUT~
cpu_instruction_master_address_to_slave[2] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[3] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[4] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[5] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[6] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[7] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[8] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[9] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[10] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[11] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[12] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[13] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[14] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[15] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[16] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[17] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[18] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[19] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[20] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[21] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[22] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[23] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[24] => sdram_s1_address.DATAA
cpu_instruction_master_address_to_slave[25] => Equal1.IN1
cpu_instruction_master_address_to_slave[26] => Equal1.IN0
cpu_instruction_master_dbs_address[0] => ~NO_FANOUT~
cpu_instruction_master_dbs_address[1] => sdram_s1_address.DATAA
cpu_instruction_master_latency_counter => LessThan0.IN2
cpu_instruction_master_latency_counter => cpu_instruction_master_qualified_request_sdram_s1.IN1
cpu_instruction_master_read => cpu_instruction_master_requests_sdram_s1.IN1
cpu_instruction_master_read => cpu_instruction_master_requests_sdram_s1.IN1
cpu_instruction_master_read => cpu_instruction_master_qualified_request_sdram_s1.IN1
cpu_instruction_master_read => sdram_s1_in_a_read_cycle.IN0
reset_n => reset_n.IN2
sdram_s1_readdata[0] => sdram_s1_readdata_from_sa[0].DATAIN
sdram_s1_readdata[1] => sdram_s1_readdata_from_sa[1].DATAIN
sdram_s1_readdata[2] => sdram_s1_readdata_from_sa[2].DATAIN
sdram_s1_readdata[3] => sdram_s1_readdata_from_sa[3].DATAIN
sdram_s1_readdata[4] => sdram_s1_readdata_from_sa[4].DATAIN
sdram_s1_readdata[5] => sdram_s1_readdata_from_sa[5].DATAIN
sdram_s1_readdata[6] => sdram_s1_readdata_from_sa[6].DATAIN
sdram_s1_readdata[7] => sdram_s1_readdata_from_sa[7].DATAIN
sdram_s1_readdata[8] => sdram_s1_readdata_from_sa[8].DATAIN
sdram_s1_readdata[9] => sdram_s1_readdata_from_sa[9].DATAIN
sdram_s1_readdata[10] => sdram_s1_readdata_from_sa[10].DATAIN
sdram_s1_readdata[11] => sdram_s1_readdata_from_sa[11].DATAIN
sdram_s1_readdata[12] => sdram_s1_readdata_from_sa[12].DATAIN
sdram_s1_readdata[13] => sdram_s1_readdata_from_sa[13].DATAIN
sdram_s1_readdata[14] => sdram_s1_readdata_from_sa[14].DATAIN
sdram_s1_readdata[15] => sdram_s1_readdata_from_sa[15].DATAIN
sdram_s1_readdatavalid => sdram_s1_move_on_to_next_transaction.IN2
sdram_s1_waitrequest => sdram_s1_waits_for_read.IN1
sdram_s1_waitrequest => sdram_s1_waits_for_write.IN1
sdram_s1_waitrequest => sdram_s1_waitrequest_from_sa.DATAIN


|LED_hello_world|CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1
clear_fifo => always1.IN1
clear_fifo => full_6.OUTPUTSELECT
clear_fifo => full_5.OUTPUTSELECT
clear_fifo => full_4.OUTPUTSELECT
clear_fifo => full_3.OUTPUTSELECT
clear_fifo => full_2.OUTPUTSELECT
clear_fifo => full_1.OUTPUTSELECT
clear_fifo => always12.IN0
clear_fifo => always13.IN0
clear_fifo => p0_stage_0.IN1
clear_fifo => p5_stage_5.IN1
clear_fifo => p4_stage_4.IN1
clear_fifo => p3_stage_3.IN1
clear_fifo => p2_stage_2.IN1
clear_fifo => p1_stage_1.IN1
clk => fifo_contains_ones_n~reg0.CLK
clk => how_many_ones[0].CLK
clk => how_many_ones[1].CLK
clk => how_many_ones[2].CLK
clk => how_many_ones[3].CLK
clk => full_0.CLK
clk => stage_0.CLK
clk => full_1.CLK
clk => stage_1.CLK
clk => full_2.CLK
clk => stage_2.CLK
clk => full_3.CLK
clk => stage_3.CLK
clk => full_4.CLK
clk => stage_4.CLK
clk => full_5.CLK
clk => stage_5.CLK
clk => full_6.CLK
clk => stage_6.CLK
data_in => p5_stage_5.DATAB
data_in => p4_stage_4.DATAB
data_in => p3_stage_3.DATAB
data_in => p2_stage_2.DATAB
data_in => p1_stage_1.DATAB
data_in => p0_stage_0.DATAB
data_in => updated_one_count.IN0
data_in => updated_one_count.IN0
data_in => updated_one_count.DATAB
data_in => stage_6.DATAA
read => p6_full_6.IN0
read => always1.IN0
read => always2.IN1
read => always4.IN1
read => always6.IN1
read => always8.IN1
read => always10.IN1
read => always12.IN1
read => always12.IN1
read => updated_one_count.IN1
read => updated_one_count.IN1
read => always0.IN0
reset_n => stage_0.ACLR
reset_n => fifo_contains_ones_n~reg0.PRESET
reset_n => full_6.ACLR
reset_n => stage_6.ACLR
reset_n => stage_5.ACLR
reset_n => full_5.ACLR
reset_n => stage_4.ACLR
reset_n => full_4.ACLR
reset_n => stage_3.ACLR
reset_n => full_3.ACLR
reset_n => stage_2.ACLR
reset_n => full_2.ACLR
reset_n => stage_1.ACLR
reset_n => full_1.ACLR
reset_n => full_0.ACLR
reset_n => how_many_ones[0].ACLR
reset_n => how_many_ones[1].ACLR
reset_n => how_many_ones[2].ACLR
reset_n => how_many_ones[3].ACLR
sync_reset => always0.IN1
sync_reset => always2.IN1
sync_reset => always4.IN1
sync_reset => always6.IN1
sync_reset => always8.IN1
sync_reset => always10.IN1
sync_reset => always12.IN1
sync_reset => always12.IN1
write => always0.IN1
write => always0.IN1
write => always1.IN1
write => always1.IN1
write => always2.IN1
write => always2.IN1
write => always4.IN1
write => always4.IN1
write => always6.IN1
write => always6.IN1
write => always8.IN1
write => always8.IN1
write => always10.IN1
write => always10.IN1
write => always12.IN1
write => always12.IN1
write => updated_one_count.IN1
write => updated_one_count.IN1
write => updated_one_count.IN1
write => always15.IN1
write => updated_one_count.IN1
write => p6_full_6.IN1
write => always13.IN1


|LED_hello_world|CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1
clear_fifo => always1.IN1
clear_fifo => full_6.OUTPUTSELECT
clear_fifo => full_5.OUTPUTSELECT
clear_fifo => full_4.OUTPUTSELECT
clear_fifo => full_3.OUTPUTSELECT
clear_fifo => full_2.OUTPUTSELECT
clear_fifo => full_1.OUTPUTSELECT
clear_fifo => always12.IN0
clear_fifo => always13.IN0
clear_fifo => p0_stage_0.IN1
clear_fifo => p5_stage_5.IN1
clear_fifo => p4_stage_4.IN1
clear_fifo => p3_stage_3.IN1
clear_fifo => p2_stage_2.IN1
clear_fifo => p1_stage_1.IN1
clk => fifo_contains_ones_n~reg0.CLK
clk => how_many_ones[0].CLK
clk => how_many_ones[1].CLK
clk => how_many_ones[2].CLK
clk => how_many_ones[3].CLK
clk => full_0.CLK
clk => stage_0.CLK
clk => full_1.CLK
clk => stage_1.CLK
clk => full_2.CLK
clk => stage_2.CLK
clk => full_3.CLK
clk => stage_3.CLK
clk => full_4.CLK
clk => stage_4.CLK
clk => full_5.CLK
clk => stage_5.CLK
clk => full_6.CLK
clk => stage_6.CLK
data_in => p5_stage_5.DATAB
data_in => p4_stage_4.DATAB
data_in => p3_stage_3.DATAB
data_in => p2_stage_2.DATAB
data_in => p1_stage_1.DATAB
data_in => p0_stage_0.DATAB
data_in => updated_one_count.IN0
data_in => updated_one_count.IN0
data_in => updated_one_count.DATAB
data_in => stage_6.DATAA
read => p6_full_6.IN0
read => always1.IN0
read => always2.IN1
read => always4.IN1
read => always6.IN1
read => always8.IN1
read => always10.IN1
read => always12.IN1
read => always12.IN1
read => updated_one_count.IN1
read => updated_one_count.IN1
read => always0.IN0
reset_n => stage_0.ACLR
reset_n => fifo_contains_ones_n~reg0.PRESET
reset_n => full_6.ACLR
reset_n => stage_6.ACLR
reset_n => stage_5.ACLR
reset_n => full_5.ACLR
reset_n => stage_4.ACLR
reset_n => full_4.ACLR
reset_n => stage_3.ACLR
reset_n => full_3.ACLR
reset_n => stage_2.ACLR
reset_n => full_2.ACLR
reset_n => stage_1.ACLR
reset_n => full_1.ACLR
reset_n => full_0.ACLR
reset_n => how_many_ones[0].ACLR
reset_n => how_many_ones[1].ACLR
reset_n => how_many_ones[2].ACLR
reset_n => how_many_ones[3].ACLR
sync_reset => always0.IN1
sync_reset => always2.IN1
sync_reset => always4.IN1
sync_reset => always6.IN1
sync_reset => always8.IN1
sync_reset => always10.IN1
sync_reset => always12.IN1
sync_reset => always12.IN1
write => always0.IN1
write => always0.IN1
write => always1.IN1
write => always1.IN1
write => always2.IN1
write => always2.IN1
write => always4.IN1
write => always4.IN1
write => always6.IN1
write => always6.IN1
write => always8.IN1
write => always8.IN1
write => always10.IN1
write => always10.IN1
write => always12.IN1
write => always12.IN1
write => updated_one_count.IN1
write => updated_one_count.IN1
write => updated_one_count.IN1
write => always15.IN1
write => updated_one_count.IN1
write => p6_full_6.IN1
write => always13.IN1


|LED_hello_world|CORE_SOPC:inst|sdram:the_sdram
az_addr[0] => az_addr[0].IN1
az_addr[1] => az_addr[1].IN1
az_addr[2] => az_addr[2].IN1
az_addr[3] => az_addr[3].IN1
az_addr[4] => az_addr[4].IN1
az_addr[5] => az_addr[5].IN1
az_addr[6] => az_addr[6].IN1
az_addr[7] => az_addr[7].IN1
az_addr[8] => az_addr[8].IN1
az_addr[9] => az_addr[9].IN1
az_addr[10] => az_addr[10].IN1
az_addr[11] => az_addr[11].IN1
az_addr[12] => az_addr[12].IN1
az_addr[13] => az_addr[13].IN1
az_addr[14] => az_addr[14].IN1
az_addr[15] => az_addr[15].IN1
az_addr[16] => az_addr[16].IN1
az_addr[17] => az_addr[17].IN1
az_addr[18] => az_addr[18].IN1
az_addr[19] => az_addr[19].IN1
az_addr[20] => az_addr[20].IN1
az_addr[21] => az_addr[21].IN1
az_addr[22] => az_addr[22].IN1
az_addr[23] => az_addr[23].IN1
az_be_n[0] => comb.DATAA
az_be_n[1] => comb.DATAA
az_cs => ~NO_FANOUT~
az_data[0] => az_data[0].IN1
az_data[1] => az_data[1].IN1
az_data[2] => az_data[2].IN1
az_data[3] => az_data[3].IN1
az_data[4] => az_data[4].IN1
az_data[5] => az_data[5].IN1
az_data[6] => az_data[6].IN1
az_data[7] => az_data[7].IN1
az_data[8] => az_data[8].IN1
az_data[9] => az_data[9].IN1
az_data[10] => az_data[10].IN1
az_data[11] => az_data[11].IN1
az_data[12] => az_data[12].IN1
az_data[13] => az_data[13].IN1
az_data[14] => az_data[14].IN1
az_data[15] => az_data[15].IN1
az_rd_n => comb.IN0
az_wr_n => az_wr_n.IN1
clk => clk.IN1
reset_n => reset_n.IN1
zs_dq[0] <> zs_dq[0]
zs_dq[1] <> zs_dq[1]
zs_dq[2] <> zs_dq[2]
zs_dq[3] <> zs_dq[3]
zs_dq[4] <> zs_dq[4]
zs_dq[5] <> zs_dq[5]
zs_dq[6] <> zs_dq[6]
zs_dq[7] <> zs_dq[7]
zs_dq[8] <> zs_dq[8]
zs_dq[9] <> zs_dq[9]
zs_dq[10] <> zs_dq[10]
zs_dq[11] <> zs_dq[11]
zs_dq[12] <> zs_dq[12]
zs_dq[13] <> zs_dq[13]
zs_dq[14] <> zs_dq[14]
zs_dq[15] <> zs_dq[15]


|LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module
clk => entry_0[0].CLK
clk => entry_0[1].CLK
clk => entry_0[2].CLK
clk => entry_0[3].CLK
clk => entry_0[4].CLK
clk => entry_0[5].CLK
clk => entry_0[6].CLK
clk => entry_0[7].CLK
clk => entry_0[8].CLK
clk => entry_0[9].CLK
clk => entry_0[10].CLK
clk => entry_0[11].CLK
clk => entry_0[12].CLK
clk => entry_0[13].CLK
clk => entry_0[14].CLK
clk => entry_0[15].CLK
clk => entry_0[16].CLK
clk => entry_0[17].CLK
clk => entry_0[18].CLK
clk => entry_0[19].CLK
clk => entry_0[20].CLK
clk => entry_0[21].CLK
clk => entry_0[22].CLK
clk => entry_0[23].CLK
clk => entry_0[24].CLK
clk => entry_0[25].CLK
clk => entry_0[26].CLK
clk => entry_0[27].CLK
clk => entry_0[28].CLK
clk => entry_0[29].CLK
clk => entry_0[30].CLK
clk => entry_0[31].CLK
clk => entry_0[32].CLK
clk => entry_0[33].CLK
clk => entry_0[34].CLK
clk => entry_0[35].CLK
clk => entry_0[36].CLK
clk => entry_0[37].CLK
clk => entry_0[38].CLK
clk => entry_0[39].CLK
clk => entry_0[40].CLK
clk => entry_0[41].CLK
clk => entry_0[42].CLK
clk => entry_1[0].CLK
clk => entry_1[1].CLK
clk => entry_1[2].CLK
clk => entry_1[3].CLK
clk => entry_1[4].CLK
clk => entry_1[5].CLK
clk => entry_1[6].CLK
clk => entry_1[7].CLK
clk => entry_1[8].CLK
clk => entry_1[9].CLK
clk => entry_1[10].CLK
clk => entry_1[11].CLK
clk => entry_1[12].CLK
clk => entry_1[13].CLK
clk => entry_1[14].CLK
clk => entry_1[15].CLK
clk => entry_1[16].CLK
clk => entry_1[17].CLK
clk => entry_1[18].CLK
clk => entry_1[19].CLK
clk => entry_1[20].CLK
clk => entry_1[21].CLK
clk => entry_1[22].CLK
clk => entry_1[23].CLK
clk => entry_1[24].CLK
clk => entry_1[25].CLK
clk => entry_1[26].CLK
clk => entry_1[27].CLK
clk => entry_1[28].CLK
clk => entry_1[29].CLK
clk => entry_1[30].CLK
clk => entry_1[31].CLK
clk => entry_1[32].CLK
clk => entry_1[33].CLK
clk => entry_1[34].CLK
clk => entry_1[35].CLK
clk => entry_1[36].CLK
clk => entry_1[37].CLK
clk => entry_1[38].CLK
clk => entry_1[39].CLK
clk => entry_1[40].CLK
clk => entry_1[41].CLK
clk => entry_1[42].CLK
clk => entries[0].CLK
clk => entries[1].CLK
clk => rd_address.CLK
clk => wr_address.CLK
rd => Mux0.IN2
rd => Mux1.IN4
rd => Mux2.IN4
rd => Mux3.IN4
reset_n => entries[0].ACLR
reset_n => entries[1].ACLR
reset_n => rd_address.ACLR
reset_n => wr_address.ACLR
wr => Mux0.IN3
wr => Mux1.IN5
wr => Mux2.IN5
wr => Mux3.IN5
wr => always2.IN1
wr_data[0] => entry_1.DATAB
wr_data[0] => entry_0.DATAA
wr_data[1] => entry_1.DATAB
wr_data[1] => entry_0.DATAA
wr_data[2] => entry_1.DATAB
wr_data[2] => entry_0.DATAA
wr_data[3] => entry_1.DATAB
wr_data[3] => entry_0.DATAA
wr_data[4] => entry_1.DATAB
wr_data[4] => entry_0.DATAA
wr_data[5] => entry_1.DATAB
wr_data[5] => entry_0.DATAA
wr_data[6] => entry_1.DATAB
wr_data[6] => entry_0.DATAA
wr_data[7] => entry_1.DATAB
wr_data[7] => entry_0.DATAA
wr_data[8] => entry_1.DATAB
wr_data[8] => entry_0.DATAA
wr_data[9] => entry_1.DATAB
wr_data[9] => entry_0.DATAA
wr_data[10] => entry_1.DATAB
wr_data[10] => entry_0.DATAA
wr_data[11] => entry_1.DATAB
wr_data[11] => entry_0.DATAA
wr_data[12] => entry_1.DATAB
wr_data[12] => entry_0.DATAA
wr_data[13] => entry_1.DATAB
wr_data[13] => entry_0.DATAA
wr_data[14] => entry_1.DATAB
wr_data[14] => entry_0.DATAA
wr_data[15] => entry_1.DATAB
wr_data[15] => entry_0.DATAA
wr_data[16] => entry_1.DATAB
wr_data[16] => entry_0.DATAA
wr_data[17] => entry_1.DATAB
wr_data[17] => entry_0.DATAA
wr_data[18] => entry_1.DATAB
wr_data[18] => entry_0.DATAA
wr_data[19] => entry_1.DATAB
wr_data[19] => entry_0.DATAA
wr_data[20] => entry_1.DATAB
wr_data[20] => entry_0.DATAA
wr_data[21] => entry_1.DATAB
wr_data[21] => entry_0.DATAA
wr_data[22] => entry_1.DATAB
wr_data[22] => entry_0.DATAA
wr_data[23] => entry_1.DATAB
wr_data[23] => entry_0.DATAA
wr_data[24] => entry_1.DATAB
wr_data[24] => entry_0.DATAA
wr_data[25] => entry_1.DATAB
wr_data[25] => entry_0.DATAA
wr_data[26] => entry_1.DATAB
wr_data[26] => entry_0.DATAA
wr_data[27] => entry_1.DATAB
wr_data[27] => entry_0.DATAA
wr_data[28] => entry_1.DATAB
wr_data[28] => entry_0.DATAA
wr_data[29] => entry_1.DATAB
wr_data[29] => entry_0.DATAA
wr_data[30] => entry_1.DATAB
wr_data[30] => entry_0.DATAA
wr_data[31] => entry_1.DATAB
wr_data[31] => entry_0.DATAA
wr_data[32] => entry_1.DATAB
wr_data[32] => entry_0.DATAA
wr_data[33] => entry_1.DATAB
wr_data[33] => entry_0.DATAA
wr_data[34] => entry_1.DATAB
wr_data[34] => entry_0.DATAA
wr_data[35] => entry_1.DATAB
wr_data[35] => entry_0.DATAA
wr_data[36] => entry_1.DATAB
wr_data[36] => entry_0.DATAA
wr_data[37] => entry_1.DATAB
wr_data[37] => entry_0.DATAA
wr_data[38] => entry_1.DATAB
wr_data[38] => entry_0.DATAA
wr_data[39] => entry_1.DATAB
wr_data[39] => entry_0.DATAA
wr_data[40] => entry_1.DATAB
wr_data[40] => entry_0.DATAA
wr_data[41] => entry_1.DATAB
wr_data[41] => entry_0.DATAA
wr_data[42] => entry_1.DATAB
wr_data[42] => entry_0.DATAA


|LED_hello_world|CORE_SOPC:inst|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port
clk => d1_spi_touch_spi_control_port_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => spi_touch_spi_control_port_address[0].DATAIN
cpu_data_master_address_to_slave[3] => spi_touch_spi_control_port_address[1].DATAIN
cpu_data_master_address_to_slave[4] => spi_touch_spi_control_port_address[2].DATAIN
cpu_data_master_address_to_slave[5] => Equal0.IN21
cpu_data_master_address_to_slave[6] => Equal0.IN20
cpu_data_master_address_to_slave[7] => Equal0.IN19
cpu_data_master_address_to_slave[8] => Equal0.IN18
cpu_data_master_address_to_slave[9] => Equal0.IN17
cpu_data_master_address_to_slave[10] => Equal0.IN16
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN15
cpu_data_master_address_to_slave[14] => Equal0.IN14
cpu_data_master_address_to_slave[15] => Equal0.IN13
cpu_data_master_address_to_slave[16] => Equal0.IN12
cpu_data_master_address_to_slave[17] => Equal0.IN11
cpu_data_master_address_to_slave[18] => Equal0.IN10
cpu_data_master_address_to_slave[19] => Equal0.IN9
cpu_data_master_address_to_slave[20] => Equal0.IN8
cpu_data_master_address_to_slave[21] => Equal0.IN7
cpu_data_master_address_to_slave[22] => Equal0.IN6
cpu_data_master_address_to_slave[23] => Equal0.IN5
cpu_data_master_address_to_slave[24] => Equal0.IN4
cpu_data_master_address_to_slave[25] => Equal0.IN3
cpu_data_master_address_to_slave[26] => Equal0.IN2
cpu_data_master_read => cpu_data_master_requests_spi_touch_spi_control_port.IN0
cpu_data_master_read => spi_touch_spi_control_port_in_a_read_cycle.IN1
cpu_data_master_write => cpu_data_master_requests_spi_touch_spi_control_port.IN1
cpu_data_master_write => spi_touch_spi_control_port_in_a_write_cycle.IN1
cpu_data_master_writedata[0] => spi_touch_spi_control_port_writedata[0].DATAIN
cpu_data_master_writedata[1] => spi_touch_spi_control_port_writedata[1].DATAIN
cpu_data_master_writedata[2] => spi_touch_spi_control_port_writedata[2].DATAIN
cpu_data_master_writedata[3] => spi_touch_spi_control_port_writedata[3].DATAIN
cpu_data_master_writedata[4] => spi_touch_spi_control_port_writedata[4].DATAIN
cpu_data_master_writedata[5] => spi_touch_spi_control_port_writedata[5].DATAIN
cpu_data_master_writedata[6] => spi_touch_spi_control_port_writedata[6].DATAIN
cpu_data_master_writedata[7] => spi_touch_spi_control_port_writedata[7].DATAIN
cpu_data_master_writedata[8] => spi_touch_spi_control_port_writedata[8].DATAIN
cpu_data_master_writedata[9] => spi_touch_spi_control_port_writedata[9].DATAIN
cpu_data_master_writedata[10] => spi_touch_spi_control_port_writedata[10].DATAIN
cpu_data_master_writedata[11] => spi_touch_spi_control_port_writedata[11].DATAIN
cpu_data_master_writedata[12] => spi_touch_spi_control_port_writedata[12].DATAIN
cpu_data_master_writedata[13] => spi_touch_spi_control_port_writedata[13].DATAIN
cpu_data_master_writedata[14] => spi_touch_spi_control_port_writedata[14].DATAIN
cpu_data_master_writedata[15] => spi_touch_spi_control_port_writedata[15].DATAIN
cpu_data_master_writedata[16] => ~NO_FANOUT~
cpu_data_master_writedata[17] => ~NO_FANOUT~
cpu_data_master_writedata[18] => ~NO_FANOUT~
cpu_data_master_writedata[19] => ~NO_FANOUT~
cpu_data_master_writedata[20] => ~NO_FANOUT~
cpu_data_master_writedata[21] => ~NO_FANOUT~
cpu_data_master_writedata[22] => ~NO_FANOUT~
cpu_data_master_writedata[23] => ~NO_FANOUT~
cpu_data_master_writedata[24] => ~NO_FANOUT~
cpu_data_master_writedata[25] => ~NO_FANOUT~
cpu_data_master_writedata[26] => ~NO_FANOUT~
cpu_data_master_writedata[27] => ~NO_FANOUT~
cpu_data_master_writedata[28] => ~NO_FANOUT~
cpu_data_master_writedata[29] => ~NO_FANOUT~
cpu_data_master_writedata[30] => ~NO_FANOUT~
cpu_data_master_writedata[31] => ~NO_FANOUT~
reset_n => spi_touch_spi_control_port_reset_n.DATAIN
reset_n => d1_spi_touch_spi_control_port_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR
spi_touch_spi_control_port_dataavailable => spi_touch_spi_control_port_dataavailable_from_sa.DATAIN
spi_touch_spi_control_port_endofpacket => spi_touch_spi_control_port_endofpacket_from_sa.DATAIN
spi_touch_spi_control_port_irq => spi_touch_spi_control_port_irq_from_sa.DATAIN
spi_touch_spi_control_port_readdata[0] => spi_touch_spi_control_port_readdata_from_sa[0].DATAIN
spi_touch_spi_control_port_readdata[1] => spi_touch_spi_control_port_readdata_from_sa[1].DATAIN
spi_touch_spi_control_port_readdata[2] => spi_touch_spi_control_port_readdata_from_sa[2].DATAIN
spi_touch_spi_control_port_readdata[3] => spi_touch_spi_control_port_readdata_from_sa[3].DATAIN
spi_touch_spi_control_port_readdata[4] => spi_touch_spi_control_port_readdata_from_sa[4].DATAIN
spi_touch_spi_control_port_readdata[5] => spi_touch_spi_control_port_readdata_from_sa[5].DATAIN
spi_touch_spi_control_port_readdata[6] => spi_touch_spi_control_port_readdata_from_sa[6].DATAIN
spi_touch_spi_control_port_readdata[7] => spi_touch_spi_control_port_readdata_from_sa[7].DATAIN
spi_touch_spi_control_port_readdata[8] => spi_touch_spi_control_port_readdata_from_sa[8].DATAIN
spi_touch_spi_control_port_readdata[9] => spi_touch_spi_control_port_readdata_from_sa[9].DATAIN
spi_touch_spi_control_port_readdata[10] => spi_touch_spi_control_port_readdata_from_sa[10].DATAIN
spi_touch_spi_control_port_readdata[11] => spi_touch_spi_control_port_readdata_from_sa[11].DATAIN
spi_touch_spi_control_port_readdata[12] => spi_touch_spi_control_port_readdata_from_sa[12].DATAIN
spi_touch_spi_control_port_readdata[13] => spi_touch_spi_control_port_readdata_from_sa[13].DATAIN
spi_touch_spi_control_port_readdata[14] => spi_touch_spi_control_port_readdata_from_sa[14].DATAIN
spi_touch_spi_control_port_readdata[15] => spi_touch_spi_control_port_readdata_from_sa[15].DATAIN
spi_touch_spi_control_port_readyfordata => spi_touch_spi_control_port_readyfordata_from_sa.DATAIN


|LED_hello_world|CORE_SOPC:inst|spi_touch:the_spi_touch
MISO => MISO_reg.DATAA
clk => MISO_reg.CLK
clk => SCLK_reg.CLK
clk => transmitting.CLK
clk => tx_holding_primed.CLK
clk => tx_holding_reg[0].CLK
clk => tx_holding_reg[1].CLK
clk => tx_holding_reg[2].CLK
clk => tx_holding_reg[3].CLK
clk => tx_holding_reg[4].CLK
clk => tx_holding_reg[5].CLK
clk => tx_holding_reg[6].CLK
clk => tx_holding_reg[7].CLK
clk => TOE.CLK
clk => ROE.CLK
clk => RRDY.CLK
clk => EOP.CLK
clk => rx_holding_reg[0].CLK
clk => rx_holding_reg[1].CLK
clk => rx_holding_reg[2].CLK
clk => rx_holding_reg[3].CLK
clk => rx_holding_reg[4].CLK
clk => rx_holding_reg[5].CLK
clk => rx_holding_reg[6].CLK
clk => rx_holding_reg[7].CLK
clk => shift_reg[0].CLK
clk => shift_reg[1].CLK
clk => shift_reg[2].CLK
clk => shift_reg[3].CLK
clk => shift_reg[4].CLK
clk => shift_reg[5].CLK
clk => shift_reg[6].CLK
clk => shift_reg[7].CLK
clk => stateZero.CLK
clk => state[0].CLK
clk => state[1].CLK
clk => state[2].CLK
clk => state[3].CLK
clk => state[4].CLK
clk => data_to_cpu[0]~reg0.CLK
clk => data_to_cpu[1]~reg0.CLK
clk => data_to_cpu[2]~reg0.CLK
clk => data_to_cpu[3]~reg0.CLK
clk => data_to_cpu[4]~reg0.CLK
clk => data_to_cpu[5]~reg0.CLK
clk => data_to_cpu[6]~reg0.CLK
clk => data_to_cpu[7]~reg0.CLK
clk => data_to_cpu[8]~reg0.CLK
clk => data_to_cpu[9]~reg0.CLK
clk => data_to_cpu[10]~reg0.CLK
clk => data_to_cpu[11]~reg0.CLK
clk => data_to_cpu[12]~reg0.CLK
clk => data_to_cpu[13]~reg0.CLK
clk => data_to_cpu[14]~reg0.CLK
clk => data_to_cpu[15]~reg0.CLK
clk => endofpacketvalue_reg[0].CLK
clk => endofpacketvalue_reg[1].CLK
clk => endofpacketvalue_reg[2].CLK
clk => endofpacketvalue_reg[3].CLK
clk => endofpacketvalue_reg[4].CLK
clk => endofpacketvalue_reg[5].CLK
clk => endofpacketvalue_reg[6].CLK
clk => endofpacketvalue_reg[7].CLK
clk => endofpacketvalue_reg[8].CLK
clk => endofpacketvalue_reg[9].CLK
clk => endofpacketvalue_reg[10].CLK
clk => endofpacketvalue_reg[11].CLK
clk => endofpacketvalue_reg[12].CLK
clk => endofpacketvalue_reg[13].CLK
clk => endofpacketvalue_reg[14].CLK
clk => endofpacketvalue_reg[15].CLK
clk => slowcount[0].CLK
clk => slowcount[1].CLK
clk => slowcount[2].CLK
clk => slowcount[3].CLK
clk => slowcount[4].CLK
clk => spi_slave_select_holding_reg[0].CLK
clk => spi_slave_select_holding_reg[1].CLK
clk => spi_slave_select_holding_reg[2].CLK
clk => spi_slave_select_holding_reg[3].CLK
clk => spi_slave_select_holding_reg[4].CLK
clk => spi_slave_select_holding_reg[5].CLK
clk => spi_slave_select_holding_reg[6].CLK
clk => spi_slave_select_holding_reg[7].CLK
clk => spi_slave_select_holding_reg[8].CLK
clk => spi_slave_select_holding_reg[9].CLK
clk => spi_slave_select_holding_reg[10].CLK
clk => spi_slave_select_holding_reg[11].CLK
clk => spi_slave_select_holding_reg[12].CLK
clk => spi_slave_select_holding_reg[13].CLK
clk => spi_slave_select_holding_reg[14].CLK
clk => spi_slave_select_holding_reg[15].CLK
clk => spi_slave_select_reg[0].CLK
clk => spi_slave_select_reg[1].CLK
clk => spi_slave_select_reg[2].CLK
clk => spi_slave_select_reg[3].CLK
clk => spi_slave_select_reg[4].CLK
clk => spi_slave_select_reg[5].CLK
clk => spi_slave_select_reg[6].CLK
clk => spi_slave_select_reg[7].CLK
clk => spi_slave_select_reg[8].CLK
clk => spi_slave_select_reg[9].CLK
clk => spi_slave_select_reg[10].CLK
clk => spi_slave_select_reg[11].CLK
clk => spi_slave_select_reg[12].CLK
clk => spi_slave_select_reg[13].CLK
clk => spi_slave_select_reg[14].CLK
clk => spi_slave_select_reg[15].CLK
clk => irq_reg.CLK
clk => SSO_reg.CLK
clk => iROE_reg.CLK
clk => iTOE_reg.CLK
clk => iTRDY_reg.CLK
clk => iRRDY_reg.CLK
clk => iE_reg.CLK
clk => iEOP_reg.CLK
clk => data_wr_strobe.CLK
clk => wr_strobe.CLK
clk => data_rd_strobe.CLK
clk => rd_strobe.CLK
data_from_cpu[0] => Equal8.IN15
data_from_cpu[0] => spi_slave_select_holding_reg[0].DATAIN
data_from_cpu[0] => endofpacketvalue_reg[0].DATAIN
data_from_cpu[0] => tx_holding_reg[0].DATAIN
data_from_cpu[1] => Equal8.IN14
data_from_cpu[1] => spi_slave_select_holding_reg[1].DATAIN
data_from_cpu[1] => endofpacketvalue_reg[1].DATAIN
data_from_cpu[1] => tx_holding_reg[1].DATAIN
data_from_cpu[2] => Equal8.IN13
data_from_cpu[2] => spi_slave_select_holding_reg[2].DATAIN
data_from_cpu[2] => endofpacketvalue_reg[2].DATAIN
data_from_cpu[2] => tx_holding_reg[2].DATAIN
data_from_cpu[3] => Equal8.IN12
data_from_cpu[3] => iROE_reg.DATAIN
data_from_cpu[3] => spi_slave_select_holding_reg[3].DATAIN
data_from_cpu[3] => endofpacketvalue_reg[3].DATAIN
data_from_cpu[3] => tx_holding_reg[3].DATAIN
data_from_cpu[4] => Equal8.IN11
data_from_cpu[4] => iTOE_reg.DATAIN
data_from_cpu[4] => spi_slave_select_holding_reg[4].DATAIN
data_from_cpu[4] => endofpacketvalue_reg[4].DATAIN
data_from_cpu[4] => tx_holding_reg[4].DATAIN
data_from_cpu[5] => Equal8.IN10
data_from_cpu[5] => spi_slave_select_holding_reg[5].DATAIN
data_from_cpu[5] => endofpacketvalue_reg[5].DATAIN
data_from_cpu[5] => tx_holding_reg[5].DATAIN
data_from_cpu[6] => Equal8.IN9
data_from_cpu[6] => iTRDY_reg.DATAIN
data_from_cpu[6] => spi_slave_select_holding_reg[6].DATAIN
data_from_cpu[6] => endofpacketvalue_reg[6].DATAIN
data_from_cpu[6] => tx_holding_reg[6].DATAIN
data_from_cpu[7] => Equal8.IN8
data_from_cpu[7] => iRRDY_reg.DATAIN
data_from_cpu[7] => spi_slave_select_holding_reg[7].DATAIN
data_from_cpu[7] => endofpacketvalue_reg[7].DATAIN
data_from_cpu[7] => tx_holding_reg[7].DATAIN
data_from_cpu[8] => iE_reg.DATAIN
data_from_cpu[8] => spi_slave_select_holding_reg[8].DATAIN
data_from_cpu[8] => endofpacketvalue_reg[8].DATAIN
data_from_cpu[9] => iEOP_reg.DATAIN
data_from_cpu[9] => spi_slave_select_holding_reg[9].DATAIN
data_from_cpu[9] => endofpacketvalue_reg[9].DATAIN
data_from_cpu[10] => always6.IN1
data_from_cpu[10] => SSO_reg.DATAIN
data_from_cpu[10] => spi_slave_select_holding_reg[10].DATAIN
data_from_cpu[10] => endofpacketvalue_reg[10].DATAIN
data_from_cpu[11] => spi_slave_select_holding_reg[11].DATAIN
data_from_cpu[11] => endofpacketvalue_reg[11].DATAIN
data_from_cpu[12] => spi_slave_select_holding_reg[12].DATAIN
data_from_cpu[12] => endofpacketvalue_reg[12].DATAIN
data_from_cpu[13] => spi_slave_select_holding_reg[13].DATAIN
data_from_cpu[13] => endofpacketvalue_reg[13].DATAIN
data_from_cpu[14] => spi_slave_select_holding_reg[14].DATAIN
data_from_cpu[14] => endofpacketvalue_reg[14].DATAIN
data_from_cpu[15] => spi_slave_select_holding_reg[15].DATAIN
data_from_cpu[15] => endofpacketvalue_reg[15].DATAIN
mem_addr[0] => Equal0.IN31
mem_addr[0] => Equal1.IN0
mem_addr[0] => Equal3.IN31
mem_addr[0] => Equal4.IN1
mem_addr[0] => Equal5.IN31
mem_addr[0] => Equal6.IN1
mem_addr[1] => Equal0.IN30
mem_addr[1] => Equal1.IN31
mem_addr[1] => Equal3.IN0
mem_addr[1] => Equal4.IN0
mem_addr[1] => Equal5.IN1
mem_addr[1] => Equal6.IN31
mem_addr[2] => Equal0.IN29
mem_addr[2] => Equal1.IN30
mem_addr[2] => Equal3.IN30
mem_addr[2] => Equal4.IN31
mem_addr[2] => Equal5.IN0
mem_addr[2] => Equal6.IN0
read_n => p1_rd_strobe.IN1
reset_n => MISO_reg.ACLR
reset_n => SCLK_reg.ACLR
reset_n => transmitting.ACLR
reset_n => tx_holding_primed.ACLR
reset_n => tx_holding_reg[0].ACLR
reset_n => tx_holding_reg[1].ACLR
reset_n => tx_holding_reg[2].ACLR
reset_n => tx_holding_reg[3].ACLR
reset_n => tx_holding_reg[4].ACLR
reset_n => tx_holding_reg[5].ACLR
reset_n => tx_holding_reg[6].ACLR
reset_n => tx_holding_reg[7].ACLR
reset_n => TOE.ACLR
reset_n => ROE.ACLR
reset_n => RRDY.ACLR
reset_n => EOP.ACLR
reset_n => rx_holding_reg[0].ACLR
reset_n => rx_holding_reg[1].ACLR
reset_n => rx_holding_reg[2].ACLR
reset_n => rx_holding_reg[3].ACLR
reset_n => rx_holding_reg[4].ACLR
reset_n => rx_holding_reg[5].ACLR
reset_n => rx_holding_reg[6].ACLR
reset_n => rx_holding_reg[7].ACLR
reset_n => shift_reg[0].ACLR
reset_n => shift_reg[1].ACLR
reset_n => shift_reg[2].ACLR
reset_n => shift_reg[3].ACLR
reset_n => shift_reg[4].ACLR
reset_n => shift_reg[5].ACLR
reset_n => shift_reg[6].ACLR
reset_n => shift_reg[7].ACLR
reset_n => data_to_cpu[0]~reg0.ACLR
reset_n => data_to_cpu[1]~reg0.ACLR
reset_n => data_to_cpu[2]~reg0.ACLR
reset_n => data_to_cpu[3]~reg0.ACLR
reset_n => data_to_cpu[4]~reg0.ACLR
reset_n => data_to_cpu[5]~reg0.ACLR
reset_n => data_to_cpu[6]~reg0.ACLR
reset_n => data_to_cpu[7]~reg0.ACLR
reset_n => data_to_cpu[8]~reg0.ACLR
reset_n => data_to_cpu[9]~reg0.ACLR
reset_n => data_to_cpu[10]~reg0.ACLR
reset_n => data_to_cpu[11]~reg0.ACLR
reset_n => data_to_cpu[12]~reg0.ACLR
reset_n => data_to_cpu[13]~reg0.ACLR
reset_n => data_to_cpu[14]~reg0.ACLR
reset_n => data_to_cpu[15]~reg0.ACLR
reset_n => irq_reg.ACLR
reset_n => rd_strobe.ACLR
reset_n => data_rd_strobe.ACLR
reset_n => wr_strobe.ACLR
reset_n => data_wr_strobe.ACLR
reset_n => SSO_reg.ACLR
reset_n => iROE_reg.ACLR
reset_n => iTOE_reg.ACLR
reset_n => iTRDY_reg.ACLR
reset_n => iRRDY_reg.ACLR
reset_n => iE_reg.ACLR
reset_n => iEOP_reg.ACLR
reset_n => spi_slave_select_reg[0].PRESET
reset_n => spi_slave_select_reg[1].ACLR
reset_n => spi_slave_select_reg[2].ACLR
reset_n => spi_slave_select_reg[3].ACLR
reset_n => spi_slave_select_reg[4].ACLR
reset_n => spi_slave_select_reg[5].ACLR
reset_n => spi_slave_select_reg[6].ACLR
reset_n => spi_slave_select_reg[7].ACLR
reset_n => spi_slave_select_reg[8].ACLR
reset_n => spi_slave_select_reg[9].ACLR
reset_n => spi_slave_select_reg[10].ACLR
reset_n => spi_slave_select_reg[11].ACLR
reset_n => spi_slave_select_reg[12].ACLR
reset_n => spi_slave_select_reg[13].ACLR
reset_n => spi_slave_select_reg[14].ACLR
reset_n => spi_slave_select_reg[15].ACLR
reset_n => spi_slave_select_holding_reg[0].PRESET
reset_n => spi_slave_select_holding_reg[1].ACLR
reset_n => spi_slave_select_holding_reg[2].ACLR
reset_n => spi_slave_select_holding_reg[3].ACLR
reset_n => spi_slave_select_holding_reg[4].ACLR
reset_n => spi_slave_select_holding_reg[5].ACLR
reset_n => spi_slave_select_holding_reg[6].ACLR
reset_n => spi_slave_select_holding_reg[7].ACLR
reset_n => spi_slave_select_holding_reg[8].ACLR
reset_n => spi_slave_select_holding_reg[9].ACLR
reset_n => spi_slave_select_holding_reg[10].ACLR
reset_n => spi_slave_select_holding_reg[11].ACLR
reset_n => spi_slave_select_holding_reg[12].ACLR
reset_n => spi_slave_select_holding_reg[13].ACLR
reset_n => spi_slave_select_holding_reg[14].ACLR
reset_n => spi_slave_select_holding_reg[15].ACLR
reset_n => slowcount[0].ACLR
reset_n => slowcount[1].ACLR
reset_n => slowcount[2].ACLR
reset_n => slowcount[3].ACLR
reset_n => slowcount[4].ACLR
reset_n => endofpacketvalue_reg[0].ACLR
reset_n => endofpacketvalue_reg[1].ACLR
reset_n => endofpacketvalue_reg[2].ACLR
reset_n => endofpacketvalue_reg[3].ACLR
reset_n => endofpacketvalue_reg[4].ACLR
reset_n => endofpacketvalue_reg[5].ACLR
reset_n => endofpacketvalue_reg[6].ACLR
reset_n => endofpacketvalue_reg[7].ACLR
reset_n => endofpacketvalue_reg[8].ACLR
reset_n => endofpacketvalue_reg[9].ACLR
reset_n => endofpacketvalue_reg[10].ACLR
reset_n => endofpacketvalue_reg[11].ACLR
reset_n => endofpacketvalue_reg[12].ACLR
reset_n => endofpacketvalue_reg[13].ACLR
reset_n => endofpacketvalue_reg[14].ACLR
reset_n => endofpacketvalue_reg[15].ACLR
reset_n => stateZero.PRESET
reset_n => state[0].ACLR
reset_n => state[1].ACLR
reset_n => state[2].ACLR
reset_n => state[3].ACLR
reset_n => state[4].ACLR
spi_select => p1_rd_strobe.IN1
spi_select => p1_wr_strobe.IN1
write_n => p1_wr_strobe.IN1


|LED_hello_world|CORE_SOPC:inst|sysid_control_slave_arbitrator:the_sysid_control_slave
clk => d1_sysid_control_slave_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => sysid_control_slave_address.DATAIN
cpu_data_master_address_to_slave[3] => Equal0.IN23
cpu_data_master_address_to_slave[4] => Equal0.IN22
cpu_data_master_address_to_slave[5] => Equal0.IN21
cpu_data_master_address_to_slave[6] => Equal0.IN3
cpu_data_master_address_to_slave[7] => Equal0.IN2
cpu_data_master_address_to_slave[8] => Equal0.IN20
cpu_data_master_address_to_slave[9] => Equal0.IN19
cpu_data_master_address_to_slave[10] => Equal0.IN18
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN17
cpu_data_master_address_to_slave[14] => Equal0.IN16
cpu_data_master_address_to_slave[15] => Equal0.IN15
cpu_data_master_address_to_slave[16] => Equal0.IN14
cpu_data_master_address_to_slave[17] => Equal0.IN13
cpu_data_master_address_to_slave[18] => Equal0.IN12
cpu_data_master_address_to_slave[19] => Equal0.IN11
cpu_data_master_address_to_slave[20] => Equal0.IN10
cpu_data_master_address_to_slave[21] => Equal0.IN9
cpu_data_master_address_to_slave[22] => Equal0.IN8
cpu_data_master_address_to_slave[23] => Equal0.IN7
cpu_data_master_address_to_slave[24] => Equal0.IN6
cpu_data_master_address_to_slave[25] => Equal0.IN5
cpu_data_master_address_to_slave[26] => Equal0.IN4
cpu_data_master_read => cpu_data_master_requests_sysid_control_slave.IN0
cpu_data_master_read => cpu_data_master_requests_sysid_control_slave.IN1
cpu_data_master_read => sysid_control_slave_in_a_read_cycle.IN1
cpu_data_master_write => cpu_data_master_requests_sysid_control_slave.IN1
reset_n => sysid_control_slave_reset_n.DATAIN
reset_n => d1_sysid_control_slave_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR
sysid_control_slave_readdata[0] => sysid_control_slave_readdata_from_sa[0].DATAIN
sysid_control_slave_readdata[1] => sysid_control_slave_readdata_from_sa[1].DATAIN
sysid_control_slave_readdata[2] => sysid_control_slave_readdata_from_sa[2].DATAIN
sysid_control_slave_readdata[3] => sysid_control_slave_readdata_from_sa[3].DATAIN
sysid_control_slave_readdata[4] => sysid_control_slave_readdata_from_sa[4].DATAIN
sysid_control_slave_readdata[5] => sysid_control_slave_readdata_from_sa[5].DATAIN
sysid_control_slave_readdata[6] => sysid_control_slave_readdata_from_sa[6].DATAIN
sysid_control_slave_readdata[7] => sysid_control_slave_readdata_from_sa[7].DATAIN
sysid_control_slave_readdata[8] => sysid_control_slave_readdata_from_sa[8].DATAIN
sysid_control_slave_readdata[9] => sysid_control_slave_readdata_from_sa[9].DATAIN
sysid_control_slave_readdata[10] => sysid_control_slave_readdata_from_sa[10].DATAIN
sysid_control_slave_readdata[11] => sysid_control_slave_readdata_from_sa[11].DATAIN
sysid_control_slave_readdata[12] => sysid_control_slave_readdata_from_sa[12].DATAIN
sysid_control_slave_readdata[13] => sysid_control_slave_readdata_from_sa[13].DATAIN
sysid_control_slave_readdata[14] => sysid_control_slave_readdata_from_sa[14].DATAIN
sysid_control_slave_readdata[15] => sysid_control_slave_readdata_from_sa[15].DATAIN
sysid_control_slave_readdata[16] => sysid_control_slave_readdata_from_sa[16].DATAIN
sysid_control_slave_readdata[17] => sysid_control_slave_readdata_from_sa[17].DATAIN
sysid_control_slave_readdata[18] => sysid_control_slave_readdata_from_sa[18].DATAIN
sysid_control_slave_readdata[19] => sysid_control_slave_readdata_from_sa[19].DATAIN
sysid_control_slave_readdata[20] => sysid_control_slave_readdata_from_sa[20].DATAIN
sysid_control_slave_readdata[21] => sysid_control_slave_readdata_from_sa[21].DATAIN
sysid_control_slave_readdata[22] => sysid_control_slave_readdata_from_sa[22].DATAIN
sysid_control_slave_readdata[23] => sysid_control_slave_readdata_from_sa[23].DATAIN
sysid_control_slave_readdata[24] => sysid_control_slave_readdata_from_sa[24].DATAIN
sysid_control_slave_readdata[25] => sysid_control_slave_readdata_from_sa[25].DATAIN
sysid_control_slave_readdata[26] => sysid_control_slave_readdata_from_sa[26].DATAIN
sysid_control_slave_readdata[27] => sysid_control_slave_readdata_from_sa[27].DATAIN
sysid_control_slave_readdata[28] => sysid_control_slave_readdata_from_sa[28].DATAIN
sysid_control_slave_readdata[29] => sysid_control_slave_readdata_from_sa[29].DATAIN
sysid_control_slave_readdata[30] => sysid_control_slave_readdata_from_sa[30].DATAIN
sysid_control_slave_readdata[31] => sysid_control_slave_readdata_from_sa[31].DATAIN


|LED_hello_world|CORE_SOPC:inst|sysid:the_sysid
address => readdata[30].DATAIN
address => readdata[28].DATAIN
address => readdata[22].DATAIN
address => readdata[19].DATAIN
address => readdata[14].DATAIN
address => readdata[13].DATAIN
address => readdata[10].DATAIN
address => readdata[9].DATAIN
address => readdata[7].DATAIN
address => readdata[6].DATAIN
address => readdata[4].DATAIN
address => readdata[2].DATAIN
address => readdata[1].DATAIN
clock => ~NO_FANOUT~
reset_n => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|touch_cs_s1_arbitrator:the_touch_cs_s1
clk => d1_touch_cs_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => touch_cs_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => touch_cs_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN3
cpu_data_master_address_to_slave[5] => Equal0.IN2
cpu_data_master_address_to_slave[6] => Equal0.IN22
cpu_data_master_address_to_slave[7] => Equal0.IN21
cpu_data_master_address_to_slave[8] => Equal0.IN20
cpu_data_master_address_to_slave[9] => Equal0.IN19
cpu_data_master_address_to_slave[10] => Equal0.IN18
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN17
cpu_data_master_address_to_slave[14] => Equal0.IN16
cpu_data_master_address_to_slave[15] => Equal0.IN15
cpu_data_master_address_to_slave[16] => Equal0.IN14
cpu_data_master_address_to_slave[17] => Equal0.IN13
cpu_data_master_address_to_slave[18] => Equal0.IN12
cpu_data_master_address_to_slave[19] => Equal0.IN11
cpu_data_master_address_to_slave[20] => Equal0.IN10
cpu_data_master_address_to_slave[21] => Equal0.IN9
cpu_data_master_address_to_slave[22] => Equal0.IN8
cpu_data_master_address_to_slave[23] => Equal0.IN7
cpu_data_master_address_to_slave[24] => Equal0.IN6
cpu_data_master_address_to_slave[25] => Equal0.IN5
cpu_data_master_address_to_slave[26] => Equal0.IN4
cpu_data_master_read => cpu_data_master_requests_touch_cs_s1.IN0
cpu_data_master_read => touch_cs_s1_in_a_read_cycle.IN1
cpu_data_master_waitrequest => cpu_data_master_qualified_request_touch_cs_s1.IN0
cpu_data_master_write => cpu_data_master_requests_touch_cs_s1.IN1
cpu_data_master_write => cpu_data_master_qualified_request_touch_cs_s1.IN1
cpu_data_master_write => touch_cs_s1_write_n.IN1
cpu_data_master_writedata[0] => touch_cs_s1_writedata[0].DATAIN
cpu_data_master_writedata[1] => touch_cs_s1_writedata[1].DATAIN
cpu_data_master_writedata[2] => touch_cs_s1_writedata[2].DATAIN
cpu_data_master_writedata[3] => touch_cs_s1_writedata[3].DATAIN
cpu_data_master_writedata[4] => touch_cs_s1_writedata[4].DATAIN
cpu_data_master_writedata[5] => touch_cs_s1_writedata[5].DATAIN
cpu_data_master_writedata[6] => touch_cs_s1_writedata[6].DATAIN
cpu_data_master_writedata[7] => touch_cs_s1_writedata[7].DATAIN
cpu_data_master_writedata[8] => touch_cs_s1_writedata[8].DATAIN
cpu_data_master_writedata[9] => touch_cs_s1_writedata[9].DATAIN
cpu_data_master_writedata[10] => touch_cs_s1_writedata[10].DATAIN
cpu_data_master_writedata[11] => touch_cs_s1_writedata[11].DATAIN
cpu_data_master_writedata[12] => touch_cs_s1_writedata[12].DATAIN
cpu_data_master_writedata[13] => touch_cs_s1_writedata[13].DATAIN
cpu_data_master_writedata[14] => touch_cs_s1_writedata[14].DATAIN
cpu_data_master_writedata[15] => touch_cs_s1_writedata[15].DATAIN
cpu_data_master_writedata[16] => touch_cs_s1_writedata[16].DATAIN
cpu_data_master_writedata[17] => touch_cs_s1_writedata[17].DATAIN
cpu_data_master_writedata[18] => touch_cs_s1_writedata[18].DATAIN
cpu_data_master_writedata[19] => touch_cs_s1_writedata[19].DATAIN
cpu_data_master_writedata[20] => touch_cs_s1_writedata[20].DATAIN
cpu_data_master_writedata[21] => touch_cs_s1_writedata[21].DATAIN
cpu_data_master_writedata[22] => touch_cs_s1_writedata[22].DATAIN
cpu_data_master_writedata[23] => touch_cs_s1_writedata[23].DATAIN
cpu_data_master_writedata[24] => touch_cs_s1_writedata[24].DATAIN
cpu_data_master_writedata[25] => touch_cs_s1_writedata[25].DATAIN
cpu_data_master_writedata[26] => touch_cs_s1_writedata[26].DATAIN
cpu_data_master_writedata[27] => touch_cs_s1_writedata[27].DATAIN
cpu_data_master_writedata[28] => touch_cs_s1_writedata[28].DATAIN
cpu_data_master_writedata[29] => touch_cs_s1_writedata[29].DATAIN
cpu_data_master_writedata[30] => touch_cs_s1_writedata[30].DATAIN
cpu_data_master_writedata[31] => touch_cs_s1_writedata[31].DATAIN
reset_n => touch_cs_s1_reset_n.DATAIN
reset_n => d1_touch_cs_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR
touch_cs_s1_readdata[0] => touch_cs_s1_readdata_from_sa[0].DATAIN
touch_cs_s1_readdata[1] => touch_cs_s1_readdata_from_sa[1].DATAIN
touch_cs_s1_readdata[2] => touch_cs_s1_readdata_from_sa[2].DATAIN
touch_cs_s1_readdata[3] => touch_cs_s1_readdata_from_sa[3].DATAIN
touch_cs_s1_readdata[4] => touch_cs_s1_readdata_from_sa[4].DATAIN
touch_cs_s1_readdata[5] => touch_cs_s1_readdata_from_sa[5].DATAIN
touch_cs_s1_readdata[6] => touch_cs_s1_readdata_from_sa[6].DATAIN
touch_cs_s1_readdata[7] => touch_cs_s1_readdata_from_sa[7].DATAIN
touch_cs_s1_readdata[8] => touch_cs_s1_readdata_from_sa[8].DATAIN
touch_cs_s1_readdata[9] => touch_cs_s1_readdata_from_sa[9].DATAIN
touch_cs_s1_readdata[10] => touch_cs_s1_readdata_from_sa[10].DATAIN
touch_cs_s1_readdata[11] => touch_cs_s1_readdata_from_sa[11].DATAIN
touch_cs_s1_readdata[12] => touch_cs_s1_readdata_from_sa[12].DATAIN
touch_cs_s1_readdata[13] => touch_cs_s1_readdata_from_sa[13].DATAIN
touch_cs_s1_readdata[14] => touch_cs_s1_readdata_from_sa[14].DATAIN
touch_cs_s1_readdata[15] => touch_cs_s1_readdata_from_sa[15].DATAIN
touch_cs_s1_readdata[16] => touch_cs_s1_readdata_from_sa[16].DATAIN
touch_cs_s1_readdata[17] => touch_cs_s1_readdata_from_sa[17].DATAIN
touch_cs_s1_readdata[18] => touch_cs_s1_readdata_from_sa[18].DATAIN
touch_cs_s1_readdata[19] => touch_cs_s1_readdata_from_sa[19].DATAIN
touch_cs_s1_readdata[20] => touch_cs_s1_readdata_from_sa[20].DATAIN
touch_cs_s1_readdata[21] => touch_cs_s1_readdata_from_sa[21].DATAIN
touch_cs_s1_readdata[22] => touch_cs_s1_readdata_from_sa[22].DATAIN
touch_cs_s1_readdata[23] => touch_cs_s1_readdata_from_sa[23].DATAIN
touch_cs_s1_readdata[24] => touch_cs_s1_readdata_from_sa[24].DATAIN
touch_cs_s1_readdata[25] => touch_cs_s1_readdata_from_sa[25].DATAIN
touch_cs_s1_readdata[26] => touch_cs_s1_readdata_from_sa[26].DATAIN
touch_cs_s1_readdata[27] => touch_cs_s1_readdata_from_sa[27].DATAIN
touch_cs_s1_readdata[28] => touch_cs_s1_readdata_from_sa[28].DATAIN
touch_cs_s1_readdata[29] => touch_cs_s1_readdata_from_sa[29].DATAIN
touch_cs_s1_readdata[30] => touch_cs_s1_readdata_from_sa[30].DATAIN
touch_cs_s1_readdata[31] => touch_cs_s1_readdata_from_sa[31].DATAIN


|LED_hello_world|CORE_SOPC:inst|touch_cs:the_touch_cs
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~


|LED_hello_world|CORE_SOPC:inst|touch_irq_s1_arbitrator:the_touch_irq_s1
clk => d1_touch_irq_s1_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_data_master_address_to_slave[2] => touch_irq_s1_address[0].DATAIN
cpu_data_master_address_to_slave[3] => touch_irq_s1_address[1].DATAIN
cpu_data_master_address_to_slave[4] => Equal0.IN3
cpu_data_master_address_to_slave[5] => Equal0.IN22
cpu_data_master_address_to_slave[6] => Equal0.IN2
cpu_data_master_address_to_slave[7] => Equal0.IN21
cpu_data_master_address_to_slave[8] => Equal0.IN20
cpu_data_master_address_to_slave[9] => Equal0.IN19
cpu_data_master_address_to_slave[10] => Equal0.IN18
cpu_data_master_address_to_slave[11] => Equal0.IN1
cpu_data_master_address_to_slave[12] => Equal0.IN0
cpu_data_master_address_to_slave[13] => Equal0.IN17
cpu_data_master_address_to_slave[14] => Equal0.IN16
cpu_data_master_address_to_slave[15] => Equal0.IN15
cpu_data_master_address_to_slave[16] => Equal0.IN14
cpu_data_master_address_to_slave[17] => Equal0.IN13
cpu_data_master_address_to_slave[18] => Equal0.IN12
cpu_data_master_address_to_slave[19] => Equal0.IN11
cpu_data_master_address_to_slave[20] => Equal0.IN10
cpu_data_master_address_to_slave[21] => Equal0.IN9
cpu_data_master_address_to_slave[22] => Equal0.IN8
cpu_data_master_address_to_slave[23] => Equal0.IN7
cpu_data_master_address_to_slave[24] => Equal0.IN6
cpu_data_master_address_to_slave[25] => Equal0.IN5
cpu_data_master_address_to_slave[26] => Equal0.IN4
cpu_data_master_read => cpu_data_master_requests_touch_irq_s1.IN0
cpu_data_master_read => cpu_data_master_requests_touch_irq_s1.IN1
cpu_data_master_read => touch_irq_s1_in_a_read_cycle.IN1
cpu_data_master_write => cpu_data_master_requests_touch_irq_s1.IN1
reset_n => touch_irq_s1_reset_n.DATAIN
reset_n => d1_touch_irq_s1_end_xfer~reg0.PRESET
reset_n => d1_reasons_to_wait.ACLR
touch_irq_s1_readdata[0] => touch_irq_s1_readdata_from_sa[0].DATAIN
touch_irq_s1_readdata[1] => touch_irq_s1_readdata_from_sa[1].DATAIN
touch_irq_s1_readdata[2] => touch_irq_s1_readdata_from_sa[2].DATAIN
touch_irq_s1_readdata[3] => touch_irq_s1_readdata_from_sa[3].DATAIN
touch_irq_s1_readdata[4] => touch_irq_s1_readdata_from_sa[4].DATAIN
touch_irq_s1_readdata[5] => touch_irq_s1_readdata_from_sa[5].DATAIN
touch_irq_s1_readdata[6] => touch_irq_s1_readdata_from_sa[6].DATAIN
touch_irq_s1_readdata[7] => touch_irq_s1_readdata_from_sa[7].DATAIN
touch_irq_s1_readdata[8] => touch_irq_s1_readdata_from_sa[8].DATAIN
touch_irq_s1_readdata[9] => touch_irq_s1_readdata_from_sa[9].DATAIN
touch_irq_s1_readdata[10] => touch_irq_s1_readdata_from_sa[10].DATAIN
touch_irq_s1_readdata[11] => touch_irq_s1_readdata_from_sa[11].DATAIN
touch_irq_s1_readdata[12] => touch_irq_s1_readdata_from_sa[12].DATAIN
touch_irq_s1_readdata[13] => touch_irq_s1_readdata_from_sa[13].DATAIN
touch_irq_s1_readdata[14] => touch_irq_s1_readdata_from_sa[14].DATAIN
touch_irq_s1_readdata[15] => touch_irq_s1_readdata_from_sa[15].DATAIN
touch_irq_s1_readdata[16] => touch_irq_s1_readdata_from_sa[16].DATAIN
touch_irq_s1_readdata[17] => touch_irq_s1_readdata_from_sa[17].DATAIN
touch_irq_s1_readdata[18] => touch_irq_s1_readdata_from_sa[18].DATAIN
touch_irq_s1_readdata[19] => touch_irq_s1_readdata_from_sa[19].DATAIN
touch_irq_s1_readdata[20] => touch_irq_s1_readdata_from_sa[20].DATAIN
touch_irq_s1_readdata[21] => touch_irq_s1_readdata_from_sa[21].DATAIN
touch_irq_s1_readdata[22] => touch_irq_s1_readdata_from_sa[22].DATAIN
touch_irq_s1_readdata[23] => touch_irq_s1_readdata_from_sa[23].DATAIN
touch_irq_s1_readdata[24] => touch_irq_s1_readdata_from_sa[24].DATAIN
touch_irq_s1_readdata[25] => touch_irq_s1_readdata_from_sa[25].DATAIN
touch_irq_s1_readdata[26] => touch_irq_s1_readdata_from_sa[26].DATAIN
touch_irq_s1_readdata[27] => touch_irq_s1_readdata_from_sa[27].DATAIN
touch_irq_s1_readdata[28] => touch_irq_s1_readdata_from_sa[28].DATAIN
touch_irq_s1_readdata[29] => touch_irq_s1_readdata_from_sa[29].DATAIN
touch_irq_s1_readdata[30] => touch_irq_s1_readdata_from_sa[30].DATAIN
touch_irq_s1_readdata[31] => touch_irq_s1_readdata_from_sa[31].DATAIN


|LED_hello_world|CORE_SOPC:inst|touch_irq:the_touch_irq
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port => read_mux_out.IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR


|LED_hello_world|CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch
clk => data_out~reg0.CLK
clk => data_in_d1.CLK
data_in => data_in_d1.DATAIN
reset_n => data_out~reg0.ACLR
reset_n => data_in_d1.ACLR


