{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 157 04/27/2011 SJ Full Version " "Info: Version 11.0 Build 157 04/27/2011 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 25 15:08:06 2013 " "Info: Processing started: Mon Feb 25 15:08:06 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off LED_hello_world -c LED_hello_world " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LED_hello_world -c LED_hello_world" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "LED_hello_world EP4CE10F17C8 " "Info: Selected device EP4CE10F17C8 for design \"LED_hello_world\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Info: Implemented PLL \"PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[0\] 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[0\] port" {  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[1\] 1 1 -100 -5556 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -100 degrees (-5556 ps) for PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[1\] port" {  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 77 -1 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Info: Device EP4CE6F17C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Info: Device EP4CE15F17C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Info: Device EP4CE22F17C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "Info: DATA\[0\] dual-purpose pin not reserved" {  } {  } 0 0 "DATA\[0\] dual-purpose pin not reserved" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_IGNORED_SPI_RESERVE_PIN_ASSIGNMENT" "DCLK " "Warning: Ignored reserve pin assignment to SPI programming pin DCLK" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { EPCS_CLK } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "EPCS_CLK" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 232 1008 1184 248 "EPCS_CLK" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPCS_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 183 5573 6591 0}  }  } }  } 0 0 "Ignored reserve pin assignment to SPI programming pin %1!s!" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "3 74 " "Critical Warning: No exact pin location assignment(s) for 3 pins of 74 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "out_port_from_the_bl_n " "Info: Pin out_port_from_the_bl_n not assigned to an exact location on the device" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { out_port_from_the_bl_n } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 168 1008 1224 184 "out_port_from_the_bl_n" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { out_port_from_the_bl_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 195 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "out_port_from_the_bl_p " "Info: Pin out_port_from_the_bl_p not assigned to an exact location on the device" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { out_port_from_the_bl_p } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 200 1008 1224 216 "out_port_from_the_bl_p" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { out_port_from_the_bl_p } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 196 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SS_n_from_the_spi_touch " "Info: Pin SS_n_from_the_spi_touch not assigned to an exact location on the device" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { SS_n_from_the_spi_touch } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 680 1008 1237 696 "SS_n_from_the_spi_touch" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { SS_n_from_the_spi_touch } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 204 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Info: Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Info: Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "Info: set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "cpu.sdc " "Info: Reading SDC File: 'cpu.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLK " "Warning: Node: CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1}  } {  } 1 0 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Info: Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " "Info:  100.000 altera_reserved_tck" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2) " "Info: Automatically promoted node PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 77 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 4903 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C1 of PLL_2) " "Info: Automatically promoted node PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C1 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 77 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 4903 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 5109 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CORE_SOPC:inst\|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch\|data_out  " "Info: Automatically promoted node CORE_SOPC:inst\|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|active_cs_n~0 " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|active_cs_n~0" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 210 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|active_cs_n~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 5754 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|active_rnw~1 " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|active_rnw~1" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 213 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|active_rnw~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 5763 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|jtag_break~1 " "Info: Destination node CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|jtag_break~1" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 393 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 6601 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[0\] " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[0\]" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 354 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|i_refs[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 608 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[2\] " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[2\]" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 354 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|i_refs[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 606 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[1\] " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[1\]" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 354 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|i_refs[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 607 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|resetlatch~0 " "Info: Destination node CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|resetlatch~0" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 376 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetlatch~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 8092 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6427 -1 0 } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CORE_SOPC:inst\|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch\|data_out" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 253 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CORE_SOPC:inst\|reset_n_sources~0  " "Info: Automatically promoted node CORE_SOPC:inst\|reset_n_sources~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6777 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|reset_n_sources~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 5677 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 0 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Warning" "WFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS" "" "Warning: Ignoring some wildcard destinations of fast I/O register assignments" { { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[8\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[8\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[0\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[1\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[2\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[0\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[10\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[10\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[11\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[11\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[12\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[12\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[13\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[13\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[14\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[14\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[15\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[15\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[1\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[2\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[3\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[3\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[4\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[4\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[5\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[5\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[6\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[6\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[7\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[7\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[9\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[9\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Enable Register ON oe " "Info: Wildcard assignment \"Fast Output Enable Register=ON\" to \"oe\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1}  } {  } 0 0 "Ignoring some wildcard destinations of fast I/O register assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "10 EC " "Extra Info: Packed 10 registers into blocks of type EC" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Extra Info: Packed 64 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 I/O Input Buffer " "Extra Info: Packed 16 registers into blocks of type I/O Input Buffer" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "53 I/O Output Buffer " "Extra Info: Packed 53 registers into blocks of type I/O Output Buffer" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "66 " "Extra Info: Created 66 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 3.3V 0 3 0 " "Info: Number of I/O pins in group: 3 (unused VREF, 3.3V VCCIO, 0 input, 3 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 8 13 " "Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used --  13 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 12 7 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 12 total pin(s) used --  7 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 20 6 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 21 6 " "Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 21 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 11 14 " "Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 11 total pin(s) used --  14 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 3 11 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1 clk\[1\] S_CLK~output " "Warning: PLL \"PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"S_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/pll.v" 94 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 64 152 392 232 "inst1" "" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 56 536 712 72 "S_CLK" "" } } } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:06 " "Info: Fitter preparation operations ending: elapsed time is 00:00:06" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "14 " "Info: Router estimated average interconnect usage is 14% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X11_Y0 X22_Y11 " "Info: Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" {  } {  } 0 0 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Info: Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 0 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_FIOMGR_MUST_USE_EXTERNAL_CLAMPING_DIODE_TOP_LEVEL" "1 " "Warning: Following 1 pins must use external clamping diodes." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "EPCS_DATA0 3.3-V LVTTL H2 " "Info: Pin EPCS_DATA0 uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { EPCS_DATA0 } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 304 320 496 320 "EPCS_DATA0" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPCS_DATA0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 185 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins must use external clamping diodes." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "36 Cyclone IV E " "Warning: 36 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[15\] 3.3-V LVTTL T7 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[15\] uses I/O standard 3.3-V LVTTL at T7" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[15] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[15\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 132 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[14\] 3.3-V LVTTL R6 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[14\] uses I/O standard 3.3-V LVTTL at R6" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[14] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[14\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 133 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[13\] 3.3-V LVTTL T8 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[13\] uses I/O standard 3.3-V LVTTL at T8" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[13] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[13\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 134 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[12\] 3.3-V LVTTL R7 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[12\] uses I/O standard 3.3-V LVTTL at R7" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[12] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[12\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 135 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[11\] 3.3-V LVTTL T9 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[11\] uses I/O standard 3.3-V LVTTL at T9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[11] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[11\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 136 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[10\] 3.3-V LVTTL R8 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[10\] uses I/O standard 3.3-V LVTTL at R8" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[10] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[10\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 137 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[9\] 3.3-V LVTTL T10 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[9\] uses I/O standard 3.3-V LVTTL at T10" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[9] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[9\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 138 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[8\] 3.3-V LVTTL R9 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[8\] uses I/O standard 3.3-V LVTTL at R9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[8] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[8\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 139 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[7\] 3.3-V LVTTL T11 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[7\] uses I/O standard 3.3-V LVTTL at T11" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[7] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[7\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 140 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[6\] 3.3-V LVTTL R10 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[6\] uses I/O standard 3.3-V LVTTL at R10" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[6] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[6\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 141 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[5\] 3.3-V LVTTL N9 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[5\] uses I/O standard 3.3-V LVTTL at N9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[5] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[5\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 142 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[4\] 3.3-V LVTTL P9 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[4\] uses I/O standard 3.3-V LVTTL at P9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[4] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[4\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 143 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[3\] 3.3-V LVTTL N11 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[3\] uses I/O standard 3.3-V LVTTL at N11" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[3] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[3\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 144 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[2\] 3.3-V LVTTL P11 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[2\] uses I/O standard 3.3-V LVTTL at P11" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[2] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[2\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 145 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[1\] 3.3-V LVTTL N12 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[1\] uses I/O standard 3.3-V LVTTL at N12" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[1] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[1\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 146 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[0\] 3.3-V LVTTL R11 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[0\] uses I/O standard 3.3-V LVTTL at R11" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[0] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[0\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 147 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[15\] 3.3-V LVTTL G15 " "Info: Pin DQ\[15\] uses I/O standard 3.3-V LVTTL at G15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[15] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[15\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 148 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[14\] 3.3-V LVTTL J15 " "Info: Pin DQ\[14\] uses I/O standard 3.3-V LVTTL at J15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[14] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[14\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 149 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[13\] 3.3-V LVTTL J16 " "Info: Pin DQ\[13\] uses I/O standard 3.3-V LVTTL at J16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[13] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[13\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 150 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[12\] 3.3-V LVTTL K15 " "Info: Pin DQ\[12\] uses I/O standard 3.3-V LVTTL at K15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[12] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[12\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 151 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[11\] 3.3-V LVTTL K16 " "Info: Pin DQ\[11\] uses I/O standard 3.3-V LVTTL at K16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[11] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[11\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 152 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[10\] 3.3-V LVTTL L15 " "Info: Pin DQ\[10\] uses I/O standard 3.3-V LVTTL at L15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[10] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[10\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 153 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[9\] 3.3-V LVTTL L16 " "Info: Pin DQ\[9\] uses I/O standard 3.3-V LVTTL at L16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[9] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[9\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 154 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[8\] 3.3-V LVTTL N15 " "Info: Pin DQ\[8\] uses I/O standard 3.3-V LVTTL at N15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[8] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[8\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 155 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[7\] 3.3-V LVTTL P1 " "Info: Pin DQ\[7\] uses I/O standard 3.3-V LVTTL at P1" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[7] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[7\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 156 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[6\] 3.3-V LVTTL P2 " "Info: Pin DQ\[6\] uses I/O standard 3.3-V LVTTL at P2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[6] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[6\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 157 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[5\] 3.3-V LVTTL N1 " "Info: Pin DQ\[5\] uses I/O standard 3.3-V LVTTL at N1" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[5] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[5\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 158 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[4\] 3.3-V LVTTL N2 " "Info: Pin DQ\[4\] uses I/O standard 3.3-V LVTTL at N2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[4] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[4\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 159 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[3\] 3.3-V LVTTL L1 " "Info: Pin DQ\[3\] uses I/O standard 3.3-V LVTTL at L1" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[3] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[3\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 160 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[2\] 3.3-V LVTTL L2 " "Info: Pin DQ\[2\] uses I/O standard 3.3-V LVTTL at L2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[2] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[2\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 161 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[1\] 3.3-V LVTTL K1 " "Info: Pin DQ\[1\] uses I/O standard 3.3-V LVTTL at K1" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[1] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[1\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 162 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[0\] 3.3-V LVTTL K2 " "Info: Pin DQ\[0\] uses I/O standard 3.3-V LVTTL at K2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[0] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[0\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 163 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLK 3.3-V LVTTL E16 " "Info: Pin CLK uses I/O standard 3.3-V LVTTL at E16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { CLK } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 120 -32 136 136 "CLK" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 182 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "RESET 3.3-V LVTTL B16 " "Info: Pin RESET uses I/O standard 3.3-V LVTTL at B16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { RESET } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "RESET" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 272 -72 96 288 "RESET" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 184 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_port_to_the_touch_irq 3.3-V LVTTL T4 " "Info: Pin in_port_to_the_touch_irq uses I/O standard 3.3-V LVTTL at T4" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { in_port_to_the_touch_irq } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "in_port_to_the_touch_irq" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 744 376 600 760 "in_port_to_the_touch_irq" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { in_port_to_the_touch_irq } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 187 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "MISO_to_the_spi_touch 3.3-V LVTTL L9 " "Info: Pin MISO_to_the_spi_touch uses I/O standard 3.3-V LVTTL at L9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { MISO_to_the_spi_touch } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "MISO_to_the_spi_touch" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 648 384 600 664 "MISO_to_the_spi_touch" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO_to_the_spi_touch } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 186 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_FOR_CONFIGURATION_PIN_TOP_LEVEL" "1 " "Warning: PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "EPCS_DATA0 3.3-V LVTTL H2 " "Info: Pin EPCS_DATA0 uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { EPCS_DATA0 } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 304 320 496 320 "EPCS_DATA0" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPCS_DATA0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 185 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "PCI-clamp diode is not supported in this mode. The following %1!d! pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.fit.smsg " "Info: Generated suppressed messages file E:/Program/EP4CE10/nios/LCD32/LED_hello_world.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 18 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "357 " "Info: Peak virtual memory: 357 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 25 15:08:25 2013 " "Info: Processing ended: Mon Feb 25 15:08:25 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Info: Total CPU time (on all processors): 00:00:20" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
