# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# applicable agreement for further details.
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# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 11.0 Build 157 04/27/2011 SJ Full Version
# Date created = 09:52:03  September 01, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		LED_hello_world_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE10F17C8
set_global_assignment -name TOP_LEVEL_ENTITY LED_hello_world
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:52:03  SEPTEMBER 01, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION 11.0
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS PROGRAMMING PIN"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_E16 -to CLK
set_location_assignment PIN_B16 -to RESET
set_location_assignment PIN_G15 -to DQ[15]
set_location_assignment PIN_J15 -to DQ[14]
set_location_assignment PIN_J16 -to DQ[13]
set_location_assignment PIN_K15 -to DQ[12]
set_location_assignment PIN_K16 -to DQ[11]
set_location_assignment PIN_L15 -to DQ[10]
set_location_assignment PIN_L16 -to DQ[9]
set_location_assignment PIN_N15 -to DQ[8]
set_location_assignment PIN_P1 -to DQ[7]
set_location_assignment PIN_P2 -to DQ[6]
set_location_assignment PIN_N1 -to DQ[5]
set_location_assignment PIN_N2 -to DQ[4]
set_location_assignment PIN_L1 -to DQ[3]
set_location_assignment PIN_L2 -to DQ[2]
set_location_assignment PIN_K1 -to DQ[1]
set_location_assignment PIN_K2 -to DQ[0]
set_location_assignment PIN_R1 -to WE
set_location_assignment PIN_N16 -to S_DQM[1]
set_location_assignment PIN_T2 -to S_DQM[0]
set_location_assignment PIN_P15 -to S_CLK
set_location_assignment PIN_T15 -to RA[12]
set_location_assignment PIN_R16 -to RA[11]
set_location_assignment PIN_N5 -to RA[10]
set_location_assignment PIN_T14 -to RA[9]
set_location_assignment PIN_R14 -to RA[8]
set_location_assignment PIN_T13 -to RA[7]
set_location_assignment PIN_R13 -to RA[6]
set_location_assignment PIN_T12 -to RA[5]
set_location_assignment PIN_R12 -to RA[4]
set_location_assignment PIN_N8 -to RA[3]
set_location_assignment PIN_L6 -to RA[2]
set_location_assignment PIN_P6 -to RA[1]
set_location_assignment PIN_P8 -to RA[0]
set_location_assignment PIN_L3 -to RAS
set_location_assignment PIN_P3 -to CS
set_location_assignment PIN_P16 -to CKE
set_location_assignment PIN_L4 -to CAS
set_location_assignment PIN_N6 -to BA[1]
set_location_assignment PIN_N3 -to BA[0]
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO OFF
set_global_assignment -name VERILOG_FILE ../../verilog/LED/LED_4.v
set_global_assignment -name QIP_FILE CORE_SOPC.qip
set_global_assignment -name BDF_FILE LED_hello_world.bdf
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_instance_assignment -name DCLK_PIN ON -to EPCS_CLK
set_instance_assignment -name DATA0_PIN ON -to EPCS_DATA0
set_instance_assignment -name SCE_PIN ON -to EPCS_SCE
set_instance_assignment -name SDO_PIN ON -to EPCS_SDO
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to LED[3]
set_location_assignment PIN_R11 -to bidir_port_to_and_from_the_lcd32_data[0]
set_location_assignment PIN_N12 -to bidir_port_to_and_from_the_lcd32_data[1]
set_location_assignment PIN_P11 -to bidir_port_to_and_from_the_lcd32_data[2]
set_location_assignment PIN_N11 -to bidir_port_to_and_from_the_lcd32_data[3]
set_location_assignment PIN_P9 -to bidir_port_to_and_from_the_lcd32_data[4]
set_location_assignment PIN_N9 -to bidir_port_to_and_from_the_lcd32_data[5]
set_location_assignment PIN_R10 -to bidir_port_to_and_from_the_lcd32_data[6]
set_location_assignment PIN_T11 -to bidir_port_to_and_from_the_lcd32_data[7]
set_location_assignment PIN_R9 -to bidir_port_to_and_from_the_lcd32_data[8]
set_location_assignment PIN_T10 -to bidir_port_to_and_from_the_lcd32_data[9]
set_location_assignment PIN_R8 -to bidir_port_to_and_from_the_lcd32_data[10]
set_location_assignment PIN_T9 -to bidir_port_to_and_from_the_lcd32_data[11]
set_location_assignment PIN_R7 -to bidir_port_to_and_from_the_lcd32_data[12]
set_location_assignment PIN_T8 -to bidir_port_to_and_from_the_lcd32_data[13]
set_location_assignment PIN_R6 -to bidir_port_to_and_from_the_lcd32_data[14]
set_location_assignment PIN_T7 -to bidir_port_to_and_from_the_lcd32_data[15]
set_location_assignment PIN_M9 -to out_port_from_the_touch_cs
set_location_assignment PIN_R5 -to out_port_from_the_lcd_cs
set_location_assignment PIN_T6 -to out_port_from_the_lcd_rs
set_location_assignment PIN_R4 -to out_port_from_the_lcd_wr
set_location_assignment PIN_T5 -to out_port_from_the_lcd_rd
set_location_assignment PIN_R3 -to out_port_from_the_reset
set_location_assignment PIN_T4 -to in_port_to_the_touch_irq
set_location_assignment PIN_T3 -to SCLK_from_the_spi_touch
set_location_assignment PIN_K9 -to MOSI_from_the_spi_touch
set_location_assignment PIN_L9 -to MISO_to_the_spi_touch
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top