/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * e:\program\FPGA\LCD32\software\LCD32_Test_syslib\..\..\CORE_SOPC.ptf
 *
 * Generated: 2014-06-11 18:40:15.406
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "CORE_SOPC"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEIVE"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x000018c8
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x000018c8
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x000018c8
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL
#define ALT_LEGACY_INTERRUPT_API_PRESENT

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_BIG_ENDIAN 0
#define NIOS2_INTERRUPT_CONTROLLER_ID 0

#define NIOS2_ICACHE_SIZE 2048
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x04000020
#define NIOS2_RESET_ADDR 0x00000000
#define NIOS2_BREAK_ADDR 0x00001020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_SYSID
#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_SPI
#define __ALTERA_AVALON_PIO

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x000018c0
#define SYSID_SPAN 8
#define SYSID_ID 0u
#define SYSID_TIMESTAMP 1346922198u
#define SYSID_REGENERATE_VALUES 0
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid

/*
 * epcs configuration
 *
 */

#define EPCS_NAME "/dev/epcs"
#define EPCS_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_BASE 0x00000000
#define EPCS_SPAN 2048
#define EPCS_IRQ 0
#define EPCS_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCS_DATABITS 8
#define EPCS_TARGETCLOCK 20
#define EPCS_CLOCKUNITS "MHz"
#define EPCS_CLOCKMULT 1000000
#define EPCS_NUMSLAVES 1
#define EPCS_ISMASTER 1
#define EPCS_CLOCKPOLARITY 0
#define EPCS_CLOCKPHASE 0
#define EPCS_LSBFIRST 0
#define EPCS_EXTRADELAY 0
#define EPCS_TARGETSSDELAY 100
#define EPCS_DELAYUNITS "us"
#define EPCS_DELAYMULT "1e-006"
#define EPCS_PREFIX "epcs_"
#define EPCS_REGISTER_OFFSET 0x400
#define EPCS_IGNORE_LEGACY_CHECK 1
#define EPCS_USE_ASMI_ATOM 0
#define EPCS_CLOCKUNIT "kHz"
#define EPCS_DELAYUNIT "us"
#define EPCS_DISABLEAVALONFLOWCONTROL 0
#define EPCS_INSERT_SYNC 0
#define EPCS_SYNC_REG_DEPTH 2
#define ALT_MODULE_CLASS_epcs altera_avalon_epcs_flash_controller

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x04000000
#define SDRAM_SPAN 33554432
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 0
#define SDRAM_SDRAM_DATA_WIDTH 16
#define SDRAM_SDRAM_ADDR_WIDTH 13
#define SDRAM_SDRAM_ROW_WIDTH 13
#define SDRAM_SDRAM_COL_WIDTH 9
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 100.0
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 70.0
#define SDRAM_T_RP 20.0
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20.0
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 14.0
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0.0
#define SDRAM_SHARED_DATA 0
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_IS_INITIALIZED 1
#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x000018c8
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 1
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_RELATIVEPATH 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 1
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

/*
 * spi_touch configuration
 *
 */

#define SPI_TOUCH_NAME "/dev/spi_touch"
#define SPI_TOUCH_TYPE "altera_avalon_spi"
#define SPI_TOUCH_BASE 0x00001800
#define SPI_TOUCH_SPAN 32
#define SPI_TOUCH_IRQ 2
#define SPI_TOUCH_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_TOUCH_DATABITS 8
#define SPI_TOUCH_DATAWIDTH 16
#define SPI_TOUCH_TARGETCLOCK 1000000
#define SPI_TOUCH_CLOCKUNITS "Hz"
#define SPI_TOUCH_CLOCKMULT 1
#define SPI_TOUCH_NUMSLAVES 1
#define SPI_TOUCH_ISMASTER 1
#define SPI_TOUCH_CLOCKPOLARITY 0
#define SPI_TOUCH_CLOCKPHASE 0
#define SPI_TOUCH_LSBFIRST 0
#define SPI_TOUCH_EXTRADELAY 0
#define SPI_TOUCH_INSERT_SYNC 0
#define SPI_TOUCH_SYNC_REG_DEPTH 2
#define SPI_TOUCH_DISABLEAVALONFLOWCONTROL 0
#define SPI_TOUCH_TARGETSSDELAY 0.0
#define SPI_TOUCH_DELAYUNITS "ns"
#define SPI_TOUCH_DELAYMULT "1e-009"
#define SPI_TOUCH_PREFIX "spi_"
#define SPI_TOUCH_CLOCKUNIT "kHz"
#define SPI_TOUCH_DELAYUNIT "us"
#define ALT_MODULE_CLASS_spi_touch altera_avalon_spi

/*
 * lcd_cs configuration
 *
 */

#define LCD_CS_NAME "/dev/lcd_cs"
#define LCD_CS_TYPE "altera_avalon_pio"
#define LCD_CS_BASE 0x00001820
#define LCD_CS_SPAN 16
#define LCD_CS_DO_TEST_BENCH_WIRING 0
#define LCD_CS_DRIVEN_SIM_VALUE 0
#define LCD_CS_HAS_TRI 0
#define LCD_CS_HAS_OUT 1
#define LCD_CS_HAS_IN 0
#define LCD_CS_CAPTURE 0
#define LCD_CS_DATA_WIDTH 1
#define LCD_CS_RESET_VALUE 0
#define LCD_CS_EDGE_TYPE "NONE"
#define LCD_CS_IRQ_TYPE "NONE"
#define LCD_CS_BIT_CLEARING_EDGE_REGISTER 0
#define LCD_CS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LCD_CS_FREQ 50000000
#define ALT_MODULE_CLASS_lcd_cs altera_avalon_pio

/*
 * touch_cs configuration
 *
 */

#define TOUCH_CS_NAME "/dev/touch_cs"
#define TOUCH_CS_TYPE "altera_avalon_pio"
#define TOUCH_CS_BASE 0x00001830
#define TOUCH_CS_SPAN 16
#define TOUCH_CS_DO_TEST_BENCH_WIRING 0
#define TOUCH_CS_DRIVEN_SIM_VALUE 0
#define TOUCH_CS_HAS_TRI 0
#define TOUCH_CS_HAS_OUT 1
#define TOUCH_CS_HAS_IN 0
#define TOUCH_CS_CAPTURE 0
#define TOUCH_CS_DATA_WIDTH 1
#define TOUCH_CS_RESET_VALUE 0
#define TOUCH_CS_EDGE_TYPE "NONE"
#define TOUCH_CS_IRQ_TYPE "NONE"
#define TOUCH_CS_BIT_CLEARING_EDGE_REGISTER 0
#define TOUCH_CS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define TOUCH_CS_FREQ 50000000
#define ALT_MODULE_CLASS_touch_cs altera_avalon_pio

/*
 * lcd_rs configuration
 *
 */

#define LCD_RS_NAME "/dev/lcd_rs"
#define LCD_RS_TYPE "altera_avalon_pio"
#define LCD_RS_BASE 0x00001840
#define LCD_RS_SPAN 16
#define LCD_RS_DO_TEST_BENCH_WIRING 0
#define LCD_RS_DRIVEN_SIM_VALUE 0
#define LCD_RS_HAS_TRI 0
#define LCD_RS_HAS_OUT 1
#define LCD_RS_HAS_IN 0
#define LCD_RS_CAPTURE 0
#define LCD_RS_DATA_WIDTH 1
#define LCD_RS_RESET_VALUE 0
#define LCD_RS_EDGE_TYPE "NONE"
#define LCD_RS_IRQ_TYPE "NONE"
#define LCD_RS_BIT_CLEARING_EDGE_REGISTER 0
#define LCD_RS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LCD_RS_FREQ 50000000
#define ALT_MODULE_CLASS_lcd_rs altera_avalon_pio

/*
 * touch_irq configuration
 *
 */

#define TOUCH_IRQ_NAME "/dev/touch_irq"
#define TOUCH_IRQ_TYPE "altera_avalon_pio"
#define TOUCH_IRQ_BASE 0x00001850
#define TOUCH_IRQ_SPAN 16
#define TOUCH_IRQ_DO_TEST_BENCH_WIRING 0
#define TOUCH_IRQ_DRIVEN_SIM_VALUE 0
#define TOUCH_IRQ_HAS_TRI 0
#define TOUCH_IRQ_HAS_OUT 0
#define TOUCH_IRQ_HAS_IN 1
#define TOUCH_IRQ_CAPTURE 0
#define TOUCH_IRQ_DATA_WIDTH 1
#define TOUCH_IRQ_RESET_VALUE 0
#define TOUCH_IRQ_EDGE_TYPE "NONE"
#define TOUCH_IRQ_IRQ_TYPE "NONE"
#define TOUCH_IRQ_BIT_CLEARING_EDGE_REGISTER 0
#define TOUCH_IRQ_BIT_MODIFYING_OUTPUT_REGISTER 0
#define TOUCH_IRQ_FREQ 50000000
#define ALT_MODULE_CLASS_touch_irq altera_avalon_pio

/*
 * reset configuration
 *
 */

#define RESET_NAME "/dev/reset"
#define RESET_TYPE "altera_avalon_pio"
#define RESET_BASE 0x00001860
#define RESET_SPAN 16
#define RESET_DO_TEST_BENCH_WIRING 0
#define RESET_DRIVEN_SIM_VALUE 0
#define RESET_HAS_TRI 0
#define RESET_HAS_OUT 1
#define RESET_HAS_IN 0
#define RESET_CAPTURE 0
#define RESET_DATA_WIDTH 1
#define RESET_RESET_VALUE 0
#define RESET_EDGE_TYPE "NONE"
#define RESET_IRQ_TYPE "NONE"
#define RESET_BIT_CLEARING_EDGE_REGISTER 0
#define RESET_BIT_MODIFYING_OUTPUT_REGISTER 0
#define RESET_FREQ 50000000
#define ALT_MODULE_CLASS_reset altera_avalon_pio

/*
 * lcd_wr configuration
 *
 */

#define LCD_WR_NAME "/dev/lcd_wr"
#define LCD_WR_TYPE "altera_avalon_pio"
#define LCD_WR_BASE 0x00001870
#define LCD_WR_SPAN 16
#define LCD_WR_DO_TEST_BENCH_WIRING 0
#define LCD_WR_DRIVEN_SIM_VALUE 0
#define LCD_WR_HAS_TRI 0
#define LCD_WR_HAS_OUT 1
#define LCD_WR_HAS_IN 0
#define LCD_WR_CAPTURE 0
#define LCD_WR_DATA_WIDTH 1
#define LCD_WR_RESET_VALUE 0
#define LCD_WR_EDGE_TYPE "NONE"
#define LCD_WR_IRQ_TYPE "NONE"
#define LCD_WR_BIT_CLEARING_EDGE_REGISTER 0
#define LCD_WR_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LCD_WR_FREQ 50000000
#define ALT_MODULE_CLASS_lcd_wr altera_avalon_pio

/*
 * lcd32_data configuration
 *
 */

#define LCD32_DATA_NAME "/dev/lcd32_data"
#define LCD32_DATA_TYPE "altera_avalon_pio"
#define LCD32_DATA_BASE 0x00001880
#define LCD32_DATA_SPAN 16
#define LCD32_DATA_DO_TEST_BENCH_WIRING 0
#define LCD32_DATA_DRIVEN_SIM_VALUE 0
#define LCD32_DATA_HAS_TRI 1
#define LCD32_DATA_HAS_OUT 0
#define LCD32_DATA_HAS_IN 0
#define LCD32_DATA_CAPTURE 0
#define LCD32_DATA_DATA_WIDTH 16
#define LCD32_DATA_RESET_VALUE 0
#define LCD32_DATA_EDGE_TYPE "NONE"
#define LCD32_DATA_IRQ_TYPE "NONE"
#define LCD32_DATA_BIT_CLEARING_EDGE_REGISTER 0
#define LCD32_DATA_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LCD32_DATA_FREQ 50000000
#define ALT_MODULE_CLASS_lcd32_data altera_avalon_pio

/*
 * lcd_rd configuration
 *
 */

#define LCD_RD_NAME "/dev/lcd_rd"
#define LCD_RD_TYPE "altera_avalon_pio"
#define LCD_RD_BASE 0x00001890
#define LCD_RD_SPAN 16
#define LCD_RD_DO_TEST_BENCH_WIRING 0
#define LCD_RD_DRIVEN_SIM_VALUE 0
#define LCD_RD_HAS_TRI 0
#define LCD_RD_HAS_OUT 1
#define LCD_RD_HAS_IN 0
#define LCD_RD_CAPTURE 0
#define LCD_RD_DATA_WIDTH 1
#define LCD_RD_RESET_VALUE 0
#define LCD_RD_EDGE_TYPE "NONE"
#define LCD_RD_IRQ_TYPE "NONE"
#define LCD_RD_BIT_CLEARING_EDGE_REGISTER 0
#define LCD_RD_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LCD_RD_FREQ 50000000
#define ALT_MODULE_CLASS_lcd_rd altera_avalon_pio

/*
 * bl_p configuration
 *
 */

#define BL_P_NAME "/dev/bl_p"
#define BL_P_TYPE "altera_avalon_pio"
#define BL_P_BASE 0x000018a0
#define BL_P_SPAN 16
#define BL_P_DO_TEST_BENCH_WIRING 0
#define BL_P_DRIVEN_SIM_VALUE 0
#define BL_P_HAS_TRI 0
#define BL_P_HAS_OUT 1
#define BL_P_HAS_IN 0
#define BL_P_CAPTURE 0
#define BL_P_DATA_WIDTH 1
#define BL_P_RESET_VALUE 0
#define BL_P_EDGE_TYPE "NONE"
#define BL_P_IRQ_TYPE "NONE"
#define BL_P_BIT_CLEARING_EDGE_REGISTER 0
#define BL_P_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BL_P_FREQ 50000000
#define ALT_MODULE_CLASS_bl_p altera_avalon_pio

/*
 * bl_n configuration
 *
 */

#define BL_N_NAME "/dev/bl_n"
#define BL_N_TYPE "altera_avalon_pio"
#define BL_N_BASE 0x000018b0
#define BL_N_SPAN 16
#define BL_N_DO_TEST_BENCH_WIRING 0
#define BL_N_DRIVEN_SIM_VALUE 0
#define BL_N_HAS_TRI 0
#define BL_N_HAS_OUT 1
#define BL_N_HAS_IN 0
#define BL_N_CAPTURE 0
#define BL_N_DATA_WIDTH 1
#define BL_N_RESET_VALUE 0
#define BL_N_EDGE_TYPE "NONE"
#define BL_N_IRQ_TYPE "NONE"
#define BL_N_BIT_CLEARING_EDGE_REGISTER 0
#define BL_N_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BL_N_FREQ 50000000
#define ALT_MODULE_CLASS_bl_n altera_avalon_pio

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      EPCS


#endif /* __SYSTEM_H_ */
