Analysis & Synthesis report for LED_hello_world
Mon Feb 25 15:08:05 2013
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis DSP Block Usage Summary
 10. Analysis & Synthesis IP Cores Summary
 11. State Machine - |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_next
 12. State Machine - |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_state
 13. State Machine - |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|i_next
 14. State Machine - |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|i_state
 15. State Machine - |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize
 16. Registers Protected by Synthesis
 17. Registers Removed During Synthesis
 18. Removed Registers Triggering Further Register Optimizations
 19. General Register Statistics
 20. Inverted Register Statistics
 21. Multiplexer Restructuring Statistics (Restructuring Performed)
 22. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_udd1:auto_generated
 23. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_i2g1:auto_generated
 24. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_bpf1:auto_generated
 25. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b7f1:auto_generated
 26. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c7f1:auto_generated
 27. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result
 28. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result
 29. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_f572:auto_generated
 30. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated
 31. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
 32. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
 33. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
 34. Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
 35. Source assignments for CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom|altsyncram_sc31:auto_generated
 36. Source assignments for CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1
 37. Source assignments for CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1
 38. Source assignments for CORE_SOPC:inst|sdram:the_sdram
 39. Source assignments for CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch
 40. Parameter Settings for User Entity Instance: PLL:inst1|altpll:altpll_component
 41. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data
 42. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram
 43. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag
 44. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram
 45. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht
 46. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram
 47. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a
 48. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram
 49. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b
 50. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram
 51. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1
 52. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2
 53. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
 54. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 55. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component
 56. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 57. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
 58. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
 59. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
 60. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
 61. Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy
 62. Parameter Settings for User Entity Instance: CORE_SOPC:inst|epcs:the_epcs
 63. Parameter Settings for User Entity Instance: CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom
 64. Parameter Settings for User Entity Instance: CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
 65. Parameter Settings for User Entity Instance: CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
 66. Parameter Settings for User Entity Instance: CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
 67. Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub
 68. Parameter Settings for Inferred Entity Instance: CORE_SOPC:inst|cpu:the_cpu|lpm_add_sub:Add10
 69. altpll Parameter Settings by Entity Instance
 70. altsyncram Parameter Settings by Entity Instance
 71. altmult_add Parameter Settings by Entity Instance
 72. scfifo Parameter Settings by Entity Instance
 73. Port Connectivity Checks: "CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch"
 74. Port Connectivity Checks: "CORE_SOPC:inst|sysid:the_sysid"
 75. Port Connectivity Checks: "CORE_SOPC:inst|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port"
 76. Port Connectivity Checks: "CORE_SOPC:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module"
 77. Port Connectivity Checks: "CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1"
 78. Port Connectivity Checks: "CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1"
 79. Port Connectivity Checks: "CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"
 80. Port Connectivity Checks: "CORE_SOPC:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave"
 81. Port Connectivity Checks: "CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port"
 82. Elapsed Time Per Partition
 83. Analysis & Synthesis Messages
 84. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
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+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Mon Feb 25 15:08:05 2013     ;
; Quartus II Version                 ; 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name                      ; LED_hello_world                           ;
; Top-level Entity Name              ; LED_hello_world                           ;
; Family                             ; Cyclone IV E                              ;
; Total logic elements               ; 3,726                                     ;
;     Total combinational functions  ; 2,992                                     ;
;     Dedicated logic registers      ; 2,225                                     ;
; Total registers                    ; 2225                                      ;
; Total pins                         ; 74                                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 37,888                                    ;
; Embedded Multiplier 9-bit elements ; 4                                         ;
; Total PLLs                         ; 1                                         ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE10F17C8       ;                    ;
; Top-level entity name                                                      ; LED_hello_world    ; LED_hello_world    ;
; Family name                                                                ; Cyclone IV E       ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ; < 0.1%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                    ;
+-------------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path    ; Used in Netlist ; File Type                              ; File Name with Absolute Path                                             ;
+-------------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+
; LED_hello_world.bdf                 ; yes             ; User Block Diagram/Schematic File      ; E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf                        ;
; pll.v                               ; yes             ; Auto-Found Wizard-Generated File       ; E:/Program/EP4CE10/nios/LCD32/pll.v                                      ;
; altpll.tdf                          ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altpll.tdf                ;
; aglobal110.inc                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/aglobal110.inc            ;
; stratix_pll.inc                     ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_pll.inc           ;
; stratixii_pll.inc                   ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratixii_pll.inc         ;
; cycloneii_pll.inc                   ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/cycloneii_pll.inc         ;
; db/pll_altpll.v                     ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v                            ;
; core_sopc.v                         ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/core_sopc.v                                ;
; bl_n.v                              ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/bl_n.v                                     ;
; bl_p.v                              ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/bl_p.v                                     ;
; cpu.v                               ; yes             ; Encrypted Auto-Found Verilog HDL File  ; E:/Program/EP4CE10/nios/LCD32/cpu.v                                      ;
; cpu_test_bench.v                    ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/cpu_test_bench.v                           ;
; altsyncram.tdf                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf            ;
; stratix_ram_block.inc               ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_ram_block.inc     ;
; lpm_mux.inc                         ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_mux.inc               ;
; lpm_decode.inc                      ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_decode.inc            ;
; a_rdenreg.inc                       ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_rdenreg.inc             ;
; altrom.inc                          ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altrom.inc                ;
; altram.inc                          ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altram.inc                ;
; altdpram.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altdpram.inc              ;
; db/altsyncram_udd1.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_udd1.tdf                     ;
; db/altsyncram_i2g1.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_i2g1.tdf                     ;
; cpu_ic_tag_ram.mif                  ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP4CE10/nios/LCD32/cpu_ic_tag_ram.mif                         ;
; db/altsyncram_bpf1.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_bpf1.tdf                     ;
; cpu_bht_ram.mif                     ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP4CE10/nios/LCD32/cpu_bht_ram.mif                            ;
; db/altsyncram_b7f1.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_b7f1.tdf                     ;
; cpu_rf_ram_a.mif                    ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP4CE10/nios/LCD32/cpu_rf_ram_a.mif                           ;
; db/altsyncram_c7f1.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_c7f1.tdf                     ;
; cpu_rf_ram_b.mif                    ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP4CE10/nios/LCD32/cpu_rf_ram_b.mif                           ;
; cpu_mult_cell.v                     ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/cpu_mult_cell.v                            ;
; altmult_add.tdf                     ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altmult_add.tdf           ;
; stratix_mac_mult.inc                ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_mac_mult.inc      ;
; stratix_mac_out.inc                 ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/stratix_mac_out.inc       ;
; db/mult_add_mgr2.tdf                ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/mult_add_mgr2.tdf                       ;
; db/ded_mult_ks81.tdf                ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/ded_mult_ks81.tdf                       ;
; db/dffpipe_93c.tdf                  ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/dffpipe_93c.tdf                         ;
; db/mult_add_ogr2.tdf                ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/mult_add_ogr2.tdf                       ;
; db/altsyncram_f572.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_f572.tdf                     ;
; cpu_ociram_default_contents.mif     ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP4CE10/nios/LCD32/cpu_ociram_default_contents.mif            ;
; cpu_oci_test_bench.v                ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/cpu_oci_test_bench.v                       ;
; db/altsyncram_0a02.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf                     ;
; cpu_jtag_debug_module_wrapper.v     ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_wrapper.v            ;
; cpu_jtag_debug_module_tck.v         ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_tck.v                ;
; altera_std_synchronizer.v           ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altera_std_synchronizer.v ;
; cpu_jtag_debug_module_sysclk.v      ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_sysclk.v             ;
; sld_virtual_jtag_basic.v            ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v  ;
; epcs.v                              ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/epcs.v                                     ;
; db/altsyncram_sc31.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_sc31.tdf                     ;
; epcs_boot_rom_synth.hex             ; yes             ; Auto-Found Memory Initialization File  ; E:/Program/EP4CE10/nios/LCD32/epcs_boot_rom_synth.hex                    ;
; jtag_uart.v                         ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/jtag_uart.v                                ;
; scfifo.tdf                          ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/scfifo.tdf                ;
; a_regfifo.inc                       ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_regfifo.inc             ;
; a_dpfifo.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_dpfifo.inc              ;
; a_i2fifo.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_i2fifo.inc              ;
; a_fffifo.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_fffifo.inc              ;
; a_f2fifo.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/a_f2fifo.inc              ;
; db/scfifo_jr21.tdf                  ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/scfifo_jr21.tdf                         ;
; db/a_dpfifo_q131.tdf                ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/a_dpfifo_q131.tdf                       ;
; db/a_fefifo_7cf.tdf                 ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/a_fefifo_7cf.tdf                        ;
; db/cntr_do7.tdf                     ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/cntr_do7.tdf                            ;
; db/dpram_nl21.tdf                   ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/dpram_nl21.tdf                          ;
; db/altsyncram_r1m1.tdf              ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/altsyncram_r1m1.tdf                     ;
; db/cntr_1ob.tdf                     ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/cntr_1ob.tdf                            ;
; alt_jtag_atlantic.v                 ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/alt_jtag_atlantic.v       ;
; lcd32_data.v                        ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/lcd32_data.v                               ;
; lcd_cs.v                            ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/lcd_cs.v                                   ;
; lcd_rd.v                            ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/lcd_rd.v                                   ;
; lcd_rs.v                            ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/lcd_rs.v                                   ;
; lcd_wr.v                            ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/lcd_wr.v                                   ;
; reset.v                             ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/reset.v                                    ;
; sdram.v                             ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/sdram.v                                    ;
; spi_touch.v                         ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/spi_touch.v                                ;
; sysid.v                             ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/sysid.v                                    ;
; touch_cs.v                          ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/touch_cs.v                                 ;
; touch_irq.v                         ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/touch_irq.v                                ;
; sld_hub.vhd                         ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/sld_hub.vhd               ;
; sld_rom_sr.vhd                      ; yes             ; Encrypted Megafunction                 ; c:/altera/11.0/quartus/libraries/megafunctions/sld_rom_sr.vhd            ;
; lpm_add_sub.tdf                     ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/lpm_add_sub.tdf           ;
; addcore.inc                         ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/addcore.inc               ;
; look_add.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/look_add.inc              ;
; bypassff.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/bypassff.inc              ;
; altshift.inc                        ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/altshift.inc              ;
; alt_stratix_add_sub.inc             ; yes             ; Megafunction                           ; c:/altera/11.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc   ;
; db/add_sub_qvi.tdf                  ; yes             ; Auto-Generated Megafunction            ; E:/Program/EP4CE10/nios/LCD32/db/add_sub_qvi.tdf                         ;
; E:/Program/EP4CE10/nios/LCD32/led.v ; yes             ; Auto-Found Verilog HDL File            ; E:/Program/EP4CE10/nios/LCD32/led.v                                      ;
+-------------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                ;
+---------------------------------------------+------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                        ;
+---------------------------------------------+------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 3,726                                                                        ;
;                                             ;                                                                              ;
; Total combinational functions               ; 2992                                                                         ;
; Logic element usage by number of LUT inputs ;                                                                              ;
;     -- 4 input functions                    ; 1562                                                                         ;
;     -- 3 input functions                    ; 1016                                                                         ;
;     -- <=2 input functions                  ; 414                                                                          ;
;                                             ;                                                                              ;
; Logic elements by mode                      ;                                                                              ;
;     -- normal mode                          ; 2777                                                                         ;
;     -- arithmetic mode                      ; 215                                                                          ;
;                                             ;                                                                              ;
; Total registers                             ; 2225                                                                         ;
;     -- Dedicated logic registers            ; 2225                                                                         ;
;     -- I/O registers                        ; 0                                                                            ;
;                                             ;                                                                              ;
; I/O pins                                    ; 74                                                                           ;
; Total memory bits                           ; 37888                                                                        ;
; Embedded Multiplier 9-bit elements          ; 4                                                                            ;
; Total PLLs                                  ; 1                                                                            ;
;     -- PLLs                                 ; 1                                                                            ;
;                                             ;                                                                              ;
; Maximum fan-out node                        ; PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out                             ; 2272                                                                         ;
; Total fan-out                               ; 22009                                                                        ;
; Average fan-out                             ; 3.92                                                                         ;
+---------------------------------------------+------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                                        ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                            ; Library Name ;
+-------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |LED_hello_world                                                                                                  ; 2992 (2)          ; 2225 (0)     ; 37888       ; 4            ; 0       ; 2         ; 74   ; 0            ; |LED_hello_world                                                                                                                                                                                                                                               ;              ;
;    |CORE_SOPC:inst|                                                                                               ; 2868 (1)          ; 2149 (0)     ; 37888       ; 4            ; 0       ; 2         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst                                                                                                                                                                                                                                ;              ;
;       |CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch|                                  ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch                                                                                                                                                       ;              ;
;       |bl_n:the_bl_n|                                                                                             ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|bl_n:the_bl_n                                                                                                                                                                                                                  ;              ;
;       |bl_n_s1_arbitrator:the_bl_n_s1|                                                                            ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|bl_n_s1_arbitrator:the_bl_n_s1                                                                                                                                                                                                 ;              ;
;       |bl_p:the_bl_p|                                                                                             ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|bl_p:the_bl_p                                                                                                                                                                                                                  ;              ;
;       |bl_p_s1_arbitrator:the_bl_p_s1|                                                                            ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|bl_p_s1_arbitrator:the_bl_p_s1                                                                                                                                                                                                 ;              ;
;       |cpu:the_cpu|                                                                                               ; 1678 (1385)       ; 1384 (1199)  ; 28672       ; 4            ; 0       ; 2         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu                                                                                                                                                                                                                    ;              ;
;          |cpu_bht_module:cpu_bht|                                                                                 ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht                                                                                                                                                                                             ;              ;
;             |altsyncram:the_altsyncram|                                                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram                                                                                                                                                                   ;              ;
;                |altsyncram_bpf1:auto_generated|                                                                   ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_bpf1:auto_generated                                                                                                                                    ;              ;
;          |cpu_ic_data_module:cpu_ic_data|                                                                         ; 1 (0)             ; 1 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data                                                                                                                                                                                     ;              ;
;             |altsyncram:the_altsyncram|                                                                           ; 1 (0)             ; 1 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram                                                                                                                                                           ;              ;
;                |altsyncram_udd1:auto_generated|                                                                   ; 1 (1)             ; 1 (1)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_udd1:auto_generated                                                                                                                            ;              ;
;          |cpu_ic_tag_module:cpu_ic_tag|                                                                           ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag                                                                                                                                                                                       ;              ;
;             |altsyncram:the_altsyncram|                                                                           ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram                                                                                                                                                             ;              ;
;                |altsyncram_i2g1:auto_generated|                                                                   ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_i2g1:auto_generated                                                                                                                              ;              ;
;          |cpu_mult_cell:the_cpu_mult_cell|                                                                        ; 0 (0)             ; 0 (0)        ; 0           ; 4            ; 0       ; 2         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell                                                                                                                                                                                    ;              ;
;             |altmult_add:the_altmult_add_part_1|                                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1                                                                                                                                                 ;              ;
;                |mult_add_mgr2:auto_generated|                                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated                                                                                                                    ;              ;
;                   |ded_mult_ks81:ded_mult1|                                                                       ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1                                                                                            ;              ;
;             |altmult_add:the_altmult_add_part_2|                                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2                                                                                                                                                 ;              ;
;                |mult_add_ogr2:auto_generated|                                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated                                                                                                                    ;              ;
;                   |ded_mult_ks81:ded_mult1|                                                                       ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated|ded_mult_ks81:ded_mult1                                                                                            ;              ;
;          |cpu_nios2_oci:the_cpu_nios2_oci|                                                                        ; 216 (23)          ; 184 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci                                                                                                                                                                                    ;              ;
;             |cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|                                     ; 92 (0)            ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper                                                                                                                    ;              ;
;                |cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|                                    ; 6 (6)             ; 49 (45)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk                                                      ;              ;
;                   |altera_std_synchronizer:the_altera_std_synchronizer2|                                          ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;              ;
;                   |altera_std_synchronizer:the_altera_std_synchronizer3|                                          ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;              ;
;                |cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|                                          ; 82 (82)           ; 47 (43)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck                                                            ;              ;
;                   |altera_std_synchronizer:the_altera_std_synchronizer1|                                          ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1       ;              ;
;                   |altera_std_synchronizer:the_altera_std_synchronizer|                                           ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer        ;              ;
;                |sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|                                                 ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy                                                                   ;              ;
;             |cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|                                                       ; 10 (10)           ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg                                                                                                                                      ;              ;
;             |cpu_nios2_oci_break:the_cpu_nios2_oci_break|                                                         ; 32 (32)           ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break                                                                                                                                        ;              ;
;             |cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|                                                         ; 8 (8)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug                                                                                                                                        ;              ;
;             |cpu_nios2_ocimem:the_cpu_nios2_ocimem|                                                               ; 51 (51)           ; 44 (44)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem                                                                                                                                              ;              ;
;                |cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|                       ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component                                                                   ;              ;
;                   |altsyncram:the_altsyncram|                                                                     ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram                                         ;              ;
;                      |altsyncram_f572:auto_generated|                                                             ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_f572:auto_generated          ;              ;
;          |cpu_register_bank_a_module:cpu_register_bank_a|                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a                                                                                                                                                                     ;              ;
;             |altsyncram:the_altsyncram|                                                                           ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram                                                                                                                                           ;              ;
;                |altsyncram_b7f1:auto_generated|                                                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b7f1:auto_generated                                                                                                            ;              ;
;          |cpu_register_bank_b_module:cpu_register_bank_b|                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b                                                                                                                                                                     ;              ;
;             |altsyncram:the_altsyncram|                                                                           ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram                                                                                                                                           ;              ;
;                |altsyncram_c7f1:auto_generated|                                                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c7f1:auto_generated                                                                                                            ;              ;
;          |cpu_test_bench:the_cpu_test_bench|                                                                      ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench                                                                                                                                                                                  ;              ;
;          |lpm_add_sub:Add10|                                                                                      ; 66 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|lpm_add_sub:Add10                                                                                                                                                                                                  ;              ;
;             |add_sub_qvi:auto_generated|                                                                          ; 66 (66)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|lpm_add_sub:Add10|add_sub_qvi:auto_generated                                                                                                                                                                       ;              ;
;       |cpu_data_master_arbitrator:the_cpu_data_master|                                                            ; 223 (223)         ; 51 (51)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu_data_master_arbitrator:the_cpu_data_master                                                                                                                                                                                 ;              ;
;       |cpu_instruction_master_arbitrator:the_cpu_instruction_master|                                              ; 110 (110)         ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master                                                                                                                                                                   ;              ;
;       |cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|                                                ; 37 (37)           ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module                                                                                                                                                                     ;              ;
;       |epcs:the_epcs|                                                                                             ; 109 (2)           ; 115 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs                                                                                                                                                                                                                  ;              ;
;          |altsyncram:the_boot_copier_rom|                                                                         ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom                                                                                                                                                                                   ;              ;
;             |altsyncram_sc31:auto_generated|                                                                      ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom|altsyncram_sc31:auto_generated                                                                                                                                                    ;              ;
;          |epcs_sub:the_epcs_sub|                                                                                  ; 107 (107)         ; 115 (115)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub                                                                                                                                                                                            ;              ;
;       |epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|                                              ; 24 (24)           ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port                                                                                                                                                                   ;              ;
;       |jtag_uart:the_jtag_uart|                                                                                   ; 142 (40)          ; 107 (13)     ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart                                                                                                                                                                                                        ;              ;
;          |alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|                                                          ; 51 (51)           ; 54 (54)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic                                                                                                                                                          ;              ;
;          |jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|                                                              ; 26 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r                                                                                                                                                              ;              ;
;             |scfifo:rfifo|                                                                                        ; 26 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo                                                                                                                                                 ;              ;
;                |scfifo_jr21:auto_generated|                                                                       ; 26 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated                                                                                                                      ;              ;
;                   |a_dpfifo_q131:dpfifo|                                                                          ; 26 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo                                                                                                 ;              ;
;                      |a_fefifo_7cf:fifo_state|                                                                    ; 14 (8)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state                                                                         ;              ;
;                         |cntr_do7:count_usedw|                                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw                                                    ;              ;
;                      |cntr_1ob:rd_ptr_count|                                                                      ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count                                                                           ;              ;
;                      |cntr_1ob:wr_ptr|                                                                            ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr                                                                                 ;              ;
;                      |dpram_nl21:FIFOram|                                                                         ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram                                                                              ;              ;
;                         |altsyncram_r1m1:altsyncram1|                                                             ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1                                                  ;              ;
;          |jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|                                                              ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w                                                                                                                                                              ;              ;
;             |scfifo:wfifo|                                                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo                                                                                                                                                 ;              ;
;                |scfifo_jr21:auto_generated|                                                                       ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated                                                                                                                      ;              ;
;                   |a_dpfifo_q131:dpfifo|                                                                          ; 25 (0)            ; 20 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo                                                                                                 ;              ;
;                      |a_fefifo_7cf:fifo_state|                                                                    ; 13 (7)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state                                                                         ;              ;
;                         |cntr_do7:count_usedw|                                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw                                                    ;              ;
;                      |cntr_1ob:rd_ptr_count|                                                                      ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count                                                                           ;              ;
;                      |cntr_1ob:wr_ptr|                                                                            ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr                                                                                 ;              ;
;                      |dpram_nl21:FIFOram|                                                                         ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram                                                                              ;              ;
;                         |altsyncram_r1m1:altsyncram1|                                                             ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1                                                  ;              ;
;       |jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|                                    ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave                                                                                                                                                         ;              ;
;       |lcd32_data:the_lcd32_data|                                                                                 ; 18 (18)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd32_data:the_lcd32_data                                                                                                                                                                                                      ;              ;
;       |lcd32_data_s1_arbitrator:the_lcd32_data_s1|                                                                ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd32_data_s1_arbitrator:the_lcd32_data_s1                                                                                                                                                                                     ;              ;
;       |lcd_cs:the_lcd_cs|                                                                                         ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd_cs:the_lcd_cs                                                                                                                                                                                                              ;              ;
;       |lcd_cs_s1_arbitrator:the_lcd_cs_s1|                                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd_cs_s1_arbitrator:the_lcd_cs_s1                                                                                                                                                                                             ;              ;
;       |lcd_rd:the_lcd_rd|                                                                                         ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd_rd:the_lcd_rd                                                                                                                                                                                                              ;              ;
;       |lcd_rd_s1_arbitrator:the_lcd_rd_s1|                                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd_rd_s1_arbitrator:the_lcd_rd_s1                                                                                                                                                                                             ;              ;
;       |lcd_rs:the_lcd_rs|                                                                                         ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd_rs:the_lcd_rs                                                                                                                                                                                                              ;              ;
;       |lcd_rs_s1_arbitrator:the_lcd_rs_s1|                                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd_rs_s1_arbitrator:the_lcd_rs_s1                                                                                                                                                                                             ;              ;
;       |lcd_wr:the_lcd_wr|                                                                                         ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd_wr:the_lcd_wr                                                                                                                                                                                                              ;              ;
;       |lcd_wr_s1_arbitrator:the_lcd_wr_s1|                                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|lcd_wr_s1_arbitrator:the_lcd_wr_s1                                                                                                                                                                                             ;              ;
;       |reset:the_reset|                                                                                           ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|reset:the_reset                                                                                                                                                                                                                ;              ;
;       |reset_s1_arbitrator:the_reset_s1|                                                                          ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|reset_s1_arbitrator:the_reset_s1                                                                                                                                                                                               ;              ;
;       |sdram:the_sdram|                                                                                           ; 266 (213)         ; 245 (155)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram                                                                                                                                                                                                                ;              ;
;          |sdram_input_efifo_module:the_sdram_input_efifo_module|                                                  ; 53 (53)           ; 90 (90)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module                                                                                                                                                          ;              ;
;       |sdram_s1_arbitrator:the_sdram_s1|                                                                          ; 109 (59)          ; 42 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1                                                                                                                                                                                               ;              ;
;          |rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|               ; 25 (25)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1                                                                                                      ;              ;
;          |rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1| ; 25 (25)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1                                                                                        ;              ;
;       |spi_touch:the_spi_touch|                                                                                   ; 112 (112)         ; 119 (119)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|spi_touch:the_spi_touch                                                                                                                                                                                                        ;              ;
;       |spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port|                                      ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port                                                                                                                                                           ;              ;
;       |sysid_control_slave_arbitrator:the_sysid_control_slave|                                                    ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|sysid_control_slave_arbitrator:the_sysid_control_slave                                                                                                                                                                         ;              ;
;       |touch_cs:the_touch_cs|                                                                                     ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|touch_cs:the_touch_cs                                                                                                                                                                                                          ;              ;
;       |touch_cs_s1_arbitrator:the_touch_cs_s1|                                                                    ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|touch_cs_s1_arbitrator:the_touch_cs_s1                                                                                                                                                                                         ;              ;
;       |touch_irq:the_touch_irq|                                                                                   ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|touch_irq:the_touch_irq                                                                                                                                                                                                        ;              ;
;       |touch_irq_s1_arbitrator:the_touch_irq_s1|                                                                  ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|CORE_SOPC:inst|touch_irq_s1_arbitrator:the_touch_irq_s1                                                                                                                                                                                       ;              ;
;    |PLL:inst1|                                                                                                    ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|PLL:inst1                                                                                                                                                                                                                                     ;              ;
;       |altpll:altpll_component|                                                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|PLL:inst1|altpll:altpll_component                                                                                                                                                                                                             ;              ;
;          |PLL_altpll:auto_generated|                                                                              ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated                                                                                                                                                                                   ;              ;
;    |sld_hub:auto_hub|                                                                                             ; 122 (81)          ; 76 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|sld_hub:auto_hub                                                                                                                                                                                                                              ;              ;
;       |sld_rom_sr:hub_info_reg|                                                                                   ; 24 (24)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|sld_hub:auto_hub|sld_rom_sr:hub_info_reg                                                                                                                                                                                                      ;              ;
;       |sld_shadow_jsm:shadow_jsm|                                                                                 ; 17 (17)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |LED_hello_world|sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                                    ;              ;
+-------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                                                ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------+
; Name                                                                                                                                                                                                                                            ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                             ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------+
; CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_bpf1:auto_generated|ALTSYNCRAM                                                                                                                           ; AUTO ; Simple Dual Port ; 256          ; 2            ; 256          ; 2            ; 512   ; cpu_bht_ram.mif                 ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_udd1:auto_generated|ALTSYNCRAM                                                                                                                   ; AUTO ; Simple Dual Port ; 512          ; 32           ; 512          ; 32           ; 16384 ; None                            ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_i2g1:auto_generated|ALTSYNCRAM                                                                                                                     ; AUTO ; Simple Dual Port ; 64           ; 24           ; 64           ; 24           ; 1536  ; cpu_ic_tag_ram.mif              ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_f572:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port   ; 256          ; 32           ; 256          ; 32           ; 8192  ; cpu_ociram_default_contents.mif ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b7f1:auto_generated|ALTSYNCRAM                                                                                                   ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; cpu_rf_ram_a.mif                ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c7f1:auto_generated|ALTSYNCRAM                                                                                                   ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; cpu_rf_ram_b.mif                ;
; CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom|altsyncram_sc31:auto_generated|ALTSYNCRAM                                                                                                                                           ; AUTO ; ROM              ; 256          ; 32           ; --           ; --           ; 8192  ; epcs_boot_rom_synth.hex         ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM                                         ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512   ; None                            ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM                                         ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512   ; None                            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 2           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 4           ;
; Signed Embedded Multipliers           ; 0           ;
; Unsigned Embedded Multipliers         ; 2           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                              ;
+--------+-------------------------------+---------+--------------+--------------+---------------------------------------------+-------------------------------------+
; Vendor ; IP Core Name                  ; Version ; Release Date ; License Type ; Entity Instance                             ; IP Include File                     ;
+--------+-------------------------------+---------+--------------+--------------+---------------------------------------------+-------------------------------------+
; Altera ; Nios II Processor (6AF7_00A2) ; N/A     ; Apr 2004     ; Licensed     ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu ; E:/Program/EP4CE10/nios/LCD32/cpu.v ;
; Altera ; ALTPLL                        ; N/A     ; N/A          ; N/A          ; |LED_hello_world|PLL:inst1                  ; E:/Program/EP4CE10/nios/LCD32/pll.v ;
+--------+-------------------------------+---------+--------------+--------------+---------------------------------------------+-------------------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------+
; State Machine - |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_next                       ;
+------------------+------------------+------------------+------------------+------------------+
; Name             ; m_next.010000000 ; m_next.000010000 ; m_next.000001000 ; m_next.000000001 ;
+------------------+------------------+------------------+------------------+------------------+
; m_next.000000001 ; 0                ; 0                ; 0                ; 0                ;
; m_next.000001000 ; 0                ; 0                ; 1                ; 1                ;
; m_next.000010000 ; 0                ; 1                ; 0                ; 1                ;
; m_next.010000000 ; 1                ; 0                ; 0                ; 1                ;
+------------------+------------------+------------------+------------------+------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_state                                                                                                                               ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; m_state.100000000 ; m_state.010000000 ; m_state.001000000 ; m_state.000100000 ; m_state.000010000 ; m_state.000001000 ; m_state.000000100 ; m_state.000000010 ; m_state.000000001 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; m_state.000000001 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; m_state.000000010 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; m_state.000000100 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; m_state.000001000 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; m_state.000010000 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000100000 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.001000000 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.010000000 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.100000000 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------+
; State Machine - |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|i_next ;
+------------+------------+------------+------------+--------------------+
; Name       ; i_next.111 ; i_next.101 ; i_next.010 ; i_next.000         ;
+------------+------------+------------+------------+--------------------+
; i_next.000 ; 0          ; 0          ; 0          ; 0                  ;
; i_next.010 ; 0          ; 0          ; 1          ; 1                  ;
; i_next.101 ; 0          ; 1          ; 0          ; 1                  ;
; i_next.111 ; 1          ; 0          ; 0          ; 1                  ;
+------------+------------+------------+------------+--------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------+
; State Machine - |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|i_state                         ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; Name        ; i_state.111 ; i_state.101 ; i_state.011 ; i_state.010 ; i_state.001 ; i_state.000 ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; i_state.000 ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ;
; i_state.001 ; 0           ; 0           ; 0           ; 0           ; 1           ; 1           ;
; i_state.010 ; 0           ; 0           ; 0           ; 1           ; 0           ; 1           ;
; i_state.011 ; 0           ; 0           ; 1           ; 0           ; 0           ; 1           ;
; i_state.101 ; 0           ; 1           ; 0           ; 0           ; 0           ; 1           ;
; i_state.111 ; 1           ; 0           ; 0           ; 0           ; 0           ; 1           ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize ;
+------------+------------+------------+------------+------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Name       ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000                                                                                                                                   ;
+------------+------------+------------+------------+------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; DRsize.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0                                                                                                                                            ;
; DRsize.001 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1                                                                                                                                            ;
; DRsize.010 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1                                                                                                                                            ;
; DRsize.011 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1                                                                                                                                            ;
; DRsize.100 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1                                                                                                                                            ;
; DRsize.101 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1                                                                                                                                            ;
+------------+------------+------------+------------+------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                                                                                                      ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                                                                                                         ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[0]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch|data_out                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0]       ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]        ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[1]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid                                                                                                                                                           ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                  ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch|data_in_d1                                                                                                                                                    ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1        ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[2]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                    ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                     ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[7]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[3]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[0]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_req                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_valid                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[4]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[1]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write                                                                                                                                                       ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[5]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[2]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1  ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[6]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[3]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[2]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[3]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[7]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[6]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[5]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[4]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[4]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                          ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                      ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[5]                                                                                                                                                         ; yes                                                              ; yes                                        ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[6]                                                                                                                                                         ; yes                                                              ; yes                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                 ; Reason for Removal                                                                                                                                                                                        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[0..35]                                                                           ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|touch_irq:the_touch_irq|readdata[1..31]                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|sdram:the_sdram|i_addr[4,5]                                                                                                                                                    ; Stuck at VCC due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|lcd32_data:the_lcd32_data|readdata[16..31]                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[3..31]                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[3..31]                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|E_ctrl_br_always_pred_taken                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|M_ctrl_br_always_pred_taken                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_im_addr[0..6]                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_wrap                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto1                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break_pulse                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto0                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_break                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto0                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto1                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|M_xbrk_goto0                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|M_xbrk_goto1                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[0..16]                                                                         ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_latency_counter                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rst1                                                                                                     ; Merged with CORE_SOPC:inst|cpu:the_cpu|clr_break_line                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[5]                                                                       ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[6]                                                                       ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[6]                                                                       ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[7]                                                                       ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[7]                                                                       ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[8]                                                                       ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[8]                                                                       ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[9]                                                                       ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[9]                                                                       ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[10]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[10]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[11]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[11]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[12]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[12]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[13]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[13]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[14]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[14]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[15]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[15]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[16]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[16]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[17]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[17]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[18]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[18]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[19]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[19]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[20]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[20]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[21]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[21]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[22]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[22]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[23]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[23]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[24]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[24]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[25]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[25]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[26]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[26]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[27]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[27]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[28]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[28]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[29]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[29]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[30]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[30]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[31]                                                                      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[31]                                                                      ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[3]                                                                       ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[3]                                                                       ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[4]                                                                       ;
; CORE_SOPC:inst|sdram:the_sdram|i_addr[0..3,6..11]                                                                                                                                             ; Merged with CORE_SOPC:inst|sdram:the_sdram|i_addr[12]                                                                                                                                                     ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|d1_epcs_epcs_control_port_end_xfer                                                                                ; Merged with CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|d1_reasons_to_wait                                                                                                ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_cpu_jtag_debug_module_end_xfer                                                                                   ; Merged with CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait                                                                                                  ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_6                                 ; Merged with CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_6                                               ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_5                                 ; Merged with CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_5                                               ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_4                                 ; Merged with CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_4                                               ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_3                                 ; Merged with CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_3                                               ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_2                                 ; Merged with CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_2                                               ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_1                                 ; Merged with CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_1                                               ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_0                                 ; Merged with CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_0                                               ;
; CORE_SOPC:inst|cpu:the_cpu|D_ctrl_jmp_direct                                                                                                                                                  ; Merged with CORE_SOPC:inst|cpu:the_cpu|D_ctrl_a_not_src                                                                                                                                                   ;
; CORE_SOPC:inst|cpu:the_cpu|D_ctrl_b_not_src                                                                                                                                                   ; Merged with CORE_SOPC:inst|cpu:the_cpu|D_ctrl_b_is_dst                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigger_state                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[0]                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_address[0]                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_dbs_address[0]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigbrktype                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_arb_share_counter[1]                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter[1]                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_arb_share_counter[0]                                                                       ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_slavearbiterlockenable                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_slavearbiterlockenable                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port                                            ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port                                                   ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module                                                      ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module                                               ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_reg_firsttransfer                                                                          ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_saved_chosen_master_vector[1]                                                              ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter[0]                                                                          ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_reg_firsttransfer                                                                             ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[1]                                                                 ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|slowcount[1]                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|sdram:the_sdram|m_next~9                                                                                                                                                       ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|m_next~10                                                                                                                                                      ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|m_next~13                                                                                                                                                      ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|m_next~14                                                                                                                                                      ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|m_next~16                                                                                                                                                      ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|i_next~4                                                                                                                                                       ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|i_next~5                                                                                                                                                       ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|i_next~6                                                                                                                                                       ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|i_state~14                                                                                                                                                     ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|i_state~15                                                                                                                                                     ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|sdram:the_sdram|i_state~16                                                                                                                                                     ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize~3   ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize~4   ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize~5   ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize.101 ; Lost fanout                                                                                                                                                                                               ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize.011 ; Merged with CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize.001 ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize.001 ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; CORE_SOPC:inst|sdram:the_sdram|m_count[2]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                    ;
; Total Number of Removed Registers = 268                                                                                                                                                       ;                                                                                                                                                                                                           ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                 ;
+---------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                             ; Reason for Removal        ; Registers Removed due to This Register                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_slavearbiterlockenable    ; Stuck at GND              ; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module,           ;
;                                                                                                                           ; due to stuck port data_in ; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module,    ;
;                                                                                                                           ;                           ; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[1]                       ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_arb_share_counter[1]   ; Stuck at GND              ; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port, ;
;                                                                                                                           ; due to stuck port data_in ; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_reg_firsttransfer                                ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_slavearbiterlockenable ; Stuck at GND              ; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port,        ;
;                                                                                                                           ; due to stuck port data_in ; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_saved_chosen_master_vector[1]                    ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[28]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[28]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[27]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[27]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[26]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[26]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[25]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[25]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[24]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[24]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[23]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[23]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[22]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[22]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[21]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[21]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[20]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[20]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[19]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[19]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[18]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[18]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[17]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[17]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[16]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[16]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[15]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[15]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[31]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[31]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[13]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[13]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[12]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[12]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[11]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[11]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[10]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[10]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[9]                                                                        ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[9]                                                                                                  ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[8]                                                                        ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[8]                                                                                                  ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[7]                                                                        ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[7]                                                                                                  ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[6]                                                                        ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[6]                                                                                                  ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[5]                                                                        ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[5]                                                                                                  ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[4]                                                                        ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[4]                                                                                                  ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[3]                                                                        ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[3]                                                                                                  ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_ctrl_br_always_pred_taken                                                                    ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_ctrl_br_always_pred_taken                                                                                              ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[30]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[30]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter[1]      ; Stuck at GND              ; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_reg_firsttransfer                                   ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[29]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[29]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
; CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[14]                                                                       ; Stuck at GND              ; CORE_SOPC:inst|cpu:the_cpu|M_control_reg_rddata[14]                                                                                                 ;
;                                                                                                                           ; due to stuck port data_in ;                                                                                                                                                     ;
+---------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 2225  ;
; Number of registers using Synchronous Clear  ; 44    ;
; Number of registers using Synchronous Load   ; 237   ;
; Number of registers using Asynchronous Clear ; 1881  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1574  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                           ; Fan out ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|epcs_slave_select_reg[0]                                                                                                 ; 2       ;
; CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|stateZero                                                                                                                ; 1       ;
; CORE_SOPC:inst|sdram:the_sdram|m_cmd[1]                                                                                                                                     ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|m_cmd[3]                                                                                                                                     ; 1       ;
; CORE_SOPC:inst|sdram:the_sdram|m_cmd[2]                                                                                                                                     ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|m_cmd[0]                                                                                                                                     ; 2       ;
; CORE_SOPC:inst|spi_touch:the_spi_touch|spi_slave_select_reg[0]                                                                                                              ; 2       ;
; CORE_SOPC:inst|spi_touch:the_spi_touch|stateZero                                                                                                                            ; 1       ;
; CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|epcs_slave_select_holding_reg[0]                                                                                         ; 1       ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n ; 22      ;
; CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_arb_addend[0]                                                            ; 6       ;
; CORE_SOPC:inst|sdram:the_sdram|i_cmd[1]                                                                                                                                     ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|i_cmd[3]                                                                                                                                     ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|i_cmd[2]                                                                                                                                     ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|i_cmd[0]                                                                                                                                     ; 2       ;
; CORE_SOPC:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_waitrequest                                                                                   ; 14      ;
; CORE_SOPC:inst|spi_touch:the_spi_touch|spi_slave_select_holding_reg[0]                                                                                                      ; 1       ;
; CORE_SOPC:inst|sdram:the_sdram|i_addr[12]                                                                                                                                   ; 11      ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|t_dav                                                                                                                                ; 4       ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[9]                                                                               ; 11      ;
; CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]                                                               ; 5       ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n               ; 2       ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]                                                                                                      ; 6       ;
; CORE_SOPC:inst|cpu:the_cpu|M_pipe_flush                                                                                                                                     ; 52      ;
; CORE_SOPC:inst|sdram:the_sdram|refresh_counter[12]                                                                                                                          ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|refresh_counter[9]                                                                                                                           ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|refresh_counter[8]                                                                                                                           ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|refresh_counter[7]                                                                                                                           ; 2       ;
; CORE_SOPC:inst|sdram:the_sdram|refresh_counter[3]                                                                                                                           ; 2       ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|av_waitrequest                                                                                                                       ; 1       ;
; CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_reg_firsttransfer                                                                                                  ; 1       ;
; CORE_SOPC:inst|cpu:the_cpu|hbreak_enabled                                                                                                                                   ; 12      ;
; CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rst2                                                                                   ; 3       ;
; CORE_SOPC:inst|cpu:the_cpu|ic_tag_clr_valid_bits                                                                                                                            ; 1       ;
; CORE_SOPC:inst|cpu:the_cpu|clr_break_line                                                                                                                                   ; 5       ;
; CORE_SOPC:inst|cpu:the_cpu|A_wr_dst_reg_from_M                                                                                                                              ; 66      ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[2]                                                     ; 2       ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[1]                                                     ; 2       ;
; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|oci_ienable[0]                                                     ; 2       ;
; sld_hub:auto_hub|tdo                                                                                                                                                        ; 2       ;
; Total number of inverted registers = 40                                                                                                                                     ;         ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                                                                                                                                                                                                 ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[3]                                                                                             ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|M_mem_byte_en[1]                                                                                                                                               ;                            ;
; 3:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|D_iw[17]                                                                                                                                                       ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|A_slow_inst_result[11]                                                                                                                                         ;                            ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|A_slow_inst_result[18]                                                                                                                                         ;                            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|ic_fill_ap_cnt[0]                                                                                                                                              ;                            ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|ic_fill_ap_offset[2]                                                                                                                                           ;                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[0]                                                                                           ;                            ;
; 8:1                ; 5 bits    ; 25 LEs        ; 10 LEs               ; 15 LEs                 ; |LED_hello_world|CORE_SOPC:inst|spi_touch:the_spi_touch|data_to_cpu[15]                                                                                                                                    ;                            ;
; 8:1                ; 2 bits    ; 10 LEs        ; 8 LEs                ; 2 LEs                  ; |LED_hello_world|CORE_SOPC:inst|spi_touch:the_spi_touch|data_to_cpu[9]                                                                                                                                     ;                            ;
; 8:1                ; 3 bits    ; 15 LEs        ; 6 LEs                ; 9 LEs                  ; |LED_hello_world|CORE_SOPC:inst|spi_touch:the_spi_touch|data_to_cpu[2]                                                                                                                                     ;                            ;
; 8:1                ; 4 bits    ; 20 LEs        ; 12 LEs               ; 8 LEs                  ; |LED_hello_world|CORE_SOPC:inst|spi_touch:the_spi_touch|data_to_cpu[3]                                                                                                                                     ;                            ;
; 8:1                ; 5 bits    ; 25 LEs        ; 10 LEs               ; 15 LEs                 ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|data_to_cpu[14]                                                                                                                        ;                            ;
; 8:1                ; 2 bits    ; 10 LEs        ; 8 LEs                ; 2 LEs                  ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|data_to_cpu[8]                                                                                                                         ;                            ;
; 8:1                ; 3 bits    ; 15 LEs        ; 6 LEs                ; 9 LEs                  ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|data_to_cpu[2]                                                                                                                         ;                            ;
; 8:1                ; 4 bits    ; 20 LEs        ; 12 LEs               ; 8 LEs                  ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|data_to_cpu[7]                                                                                                                         ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; |LED_hello_world|CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub|shift_reg[5]                                                                                                                           ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; |LED_hello_world|CORE_SOPC:inst|spi_touch:the_spi_touch|shift_reg[7]                                                                                                                                       ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                          ;                            ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|ic_tag_wraddress[1]                                                                                                                                            ;                            ;
; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonDReg[6]                                                                               ;                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonDReg[5]                                                                               ;                            ;
; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|E_control_reg_rddata[1]                                                                                                                                        ;                            ;
; 4:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|E_src2[24]                                                                                                                                                     ;                            ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|A_slow_inst_result[6]                                                                                                                                          ;                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|M_st_data[30]                                                                                                                                                  ;                            ;
; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonDReg[1]                                                                               ;                            ;
; 6:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[37] ;                            ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[33] ;                            ;
; 6:1                ; 13 bits   ; 52 LEs        ; 26 LEs               ; 26 LEs                 ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[10] ;                            ;
; 6:1                ; 16 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|sr[28] ;                            ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|E_src1[17]                                                                                                                                                     ;                            ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[10]                                                                              ;                            ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_bank[0]                                                                                                                                                  ;                            ;
; 5:1                ; 32 bits   ; 96 LEs        ; 32 LEs               ; 64 LEs                 ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[3]                                                                   ;                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|M_mem_byte_en[3]                                                                                                                                               ;                            ;
; 6:1                ; 16 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|F_pc[24]                                                                                                                                                       ;                            ;
; 6:1                ; 25 bits   ; 100 LEs       ; 100 LEs              ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|M_pipe_flush_waddr[14]                                                                                                                                         ;                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|i_count[0]                                                                                                                                                 ;                            ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_addr[10]                                                                                                                                                 ;                            ;
; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_addr[4]                                                                                                                                                  ;                            ;
; 7:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_addr[1]                                                                                                                                                  ;                            ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[4]                                                                                          ;                            ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; |LED_hello_world|CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[5]                                                                                          ;                            ;
; 12:1               ; 43 bits   ; 344 LEs       ; 0 LEs                ; 344 LEs                ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|active_addr[13]                                                                                                                                            ;                            ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|m_data[3]                                                                                                                                                  ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|comb                                                                                                                                                       ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |LED_hello_world|CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_arb_share_counter_next_value[0]                                                        ;                            ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|E_logic_result[3]                                                                                                                                              ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter_next_value[1]                                                           ;                            ;
; 3:1                ; 12 bits   ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|F_iw[11]                                                                                                                                                       ;                            ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count                  ;                            ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |LED_hello_world|CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count                                ;                            ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|D_dst_regnum[0]                                                                                                                                                ;                            ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[1]                                                                                                                    ;                            ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|A_wr_data_unfiltered[27]                                                                                                                                       ;                            ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|D_src2_reg[18]                                                                                                                                                 ;                            ;
; 6:1                ; 9 bits    ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; |LED_hello_world|CORE_SOPC:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]                                                                                                                                       ;                            ;
; 11:1               ; 2 bits    ; 14 LEs        ; 4 LEs                ; 10 LEs                 ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|Selector34                                                                                                                                                 ;                            ;
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; |LED_hello_world|CORE_SOPC:inst|sdram:the_sdram|Selector28                                                                                                                                                 ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_udd1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                          ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                           ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_i2g1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                        ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                         ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_bpf1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                  ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                   ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b7f1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                          ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                           ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c7f1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                          ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                           ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_f572:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                            ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                             ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                              ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                         ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                         ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                         ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                          ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                          ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                          ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                               ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                          ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                          ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                          ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                           ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                     ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                 ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                 ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                 ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                     ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                 ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                 ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                 ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom|altsyncram_sc31:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                  ;
+---------------------------------+--------------------+------+-----------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                   ;
+---------------------------------+--------------------+------+-----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                    ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                     ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                    ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                     ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|sdram:the_sdram         ;
+-----------------------------+-------+------+------------------+
; Assignment                  ; Value ; From ; To               ;
+-----------------------------+-------+------+------------------+
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[3]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[2]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[0]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[12]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[0]         ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; oe               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]~reg0  ;
+-----------------------------+-------+------+------------------+


+----------------------------------------------------------------------------------------------------------------+
; Source assignments for CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch ;
+-------------------+-------+------+-----------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                          ;
+-------------------+-------+------+-----------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                    ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                  ;
+-------------------+-------+------+-----------------------------------------------------------------------------+


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: PLL:inst1|altpll:altpll_component ;
+-------------------------------+-----------------------+------------------------+
; Parameter Name                ; Value                 ; Type                   ;
+-------------------------------+-----------------------+------------------------+
; OPERATION_MODE                ; NORMAL                ; Untyped                ;
; PLL_TYPE                      ; AUTO                  ; Untyped                ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=PLL ; Untyped                ;
; QUALIFY_CONF_DONE             ; OFF                   ; Untyped                ;
; COMPENSATE_CLOCK              ; CLK0                  ; Untyped                ;
; SCAN_CHAIN                    ; LONG                  ; Untyped                ;
; PRIMARY_CLOCK                 ; INCLK0                ; Untyped                ;
; INCLK0_INPUT_FREQUENCY        ; 20000                 ; Signed Integer         ;
; INCLK1_INPUT_FREQUENCY        ; 0                     ; Untyped                ;
; GATE_LOCK_SIGNAL              ; NO                    ; Untyped                ;
; GATE_LOCK_COUNTER             ; 0                     ; Untyped                ;
; LOCK_HIGH                     ; 1                     ; Untyped                ;
; LOCK_LOW                      ; 1                     ; Untyped                ;
; VALID_LOCK_MULTIPLIER         ; 1                     ; Untyped                ;
; INVALID_LOCK_MULTIPLIER       ; 5                     ; Untyped                ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                   ; Untyped                ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                   ; Untyped                ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                   ; Untyped                ;
; SKIP_VCO                      ; OFF                   ; Untyped                ;
; SWITCH_OVER_COUNTER           ; 0                     ; Untyped                ;
; SWITCH_OVER_TYPE              ; AUTO                  ; Untyped                ;
; FEEDBACK_SOURCE               ; EXTCLK0               ; Untyped                ;
; BANDWIDTH                     ; 0                     ; Untyped                ;
; BANDWIDTH_TYPE                ; AUTO                  ; Untyped                ;
; SPREAD_FREQUENCY              ; 0                     ; Untyped                ;
; DOWN_SPREAD                   ; 0                     ; Untyped                ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                   ; Untyped                ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                   ; Untyped                ;
; CLK9_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK8_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK7_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK6_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK5_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK4_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK3_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK2_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK1_MULTIPLY_BY              ; 1                     ; Signed Integer         ;
; CLK0_MULTIPLY_BY              ; 1                     ; Signed Integer         ;
; CLK9_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK8_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK7_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK6_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK5_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK4_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK3_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK2_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK1_DIVIDE_BY                ; 1                     ; Signed Integer         ;
; CLK0_DIVIDE_BY                ; 1                     ; Signed Integer         ;
; CLK9_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK8_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK7_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK6_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK5_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK4_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK3_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK2_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK1_PHASE_SHIFT              ; -5556                 ; Untyped                ;
; CLK0_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK5_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK4_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK3_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK2_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK1_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK0_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK9_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK8_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK7_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK6_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK5_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK4_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK3_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK2_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK1_DUTY_CYCLE               ; 50                    ; Signed Integer         ;
; CLK0_DUTY_CYCLE               ; 50                    ; Signed Integer         ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; LOCK_WINDOW_UI                ;  0.05                 ; Untyped                ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                ; Untyped                ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                ; Untyped                ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                ; Untyped                ;
; DPA_MULTIPLY_BY               ; 0                     ; Untyped                ;
; DPA_DIVIDE_BY                 ; 1                     ; Untyped                ;
; DPA_DIVIDER                   ; 0                     ; Untyped                ;
; EXTCLK3_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK2_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK1_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK0_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK3_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK2_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK1_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK0_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK3_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK2_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK1_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK0_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK3_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK2_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK1_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK0_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK3_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK2_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK1_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK0_DUTY_CYCLE            ; 50                    ; Untyped                ;
; VCO_MULTIPLY_BY               ; 0                     ; Untyped                ;
; VCO_DIVIDE_BY                 ; 0                     ; Untyped                ;
; SCLKOUT0_PHASE_SHIFT          ; 0                     ; Untyped                ;
; SCLKOUT1_PHASE_SHIFT          ; 0                     ; Untyped                ;
; VCO_MIN                       ; 0                     ; Untyped                ;
; VCO_MAX                       ; 0                     ; Untyped                ;
; VCO_CENTER                    ; 0                     ; Untyped                ;
; PFD_MIN                       ; 0                     ; Untyped                ;
; PFD_MAX                       ; 0                     ; Untyped                ;
; M_INITIAL                     ; 0                     ; Untyped                ;
; M                             ; 0                     ; Untyped                ;
; N                             ; 1                     ; Untyped                ;
; M2                            ; 1                     ; Untyped                ;
; N2                            ; 1                     ; Untyped                ;
; SS                            ; 1                     ; Untyped                ;
; C0_HIGH                       ; 0                     ; Untyped                ;
; C1_HIGH                       ; 0                     ; Untyped                ;
; C2_HIGH                       ; 0                     ; Untyped                ;
; C3_HIGH                       ; 0                     ; Untyped                ;
; C4_HIGH                       ; 0                     ; Untyped                ;
; C5_HIGH                       ; 0                     ; Untyped                ;
; C6_HIGH                       ; 0                     ; Untyped                ;
; C7_HIGH                       ; 0                     ; Untyped                ;
; C8_HIGH                       ; 0                     ; Untyped                ;
; C9_HIGH                       ; 0                     ; Untyped                ;
; C0_LOW                        ; 0                     ; Untyped                ;
; C1_LOW                        ; 0                     ; Untyped                ;
; C2_LOW                        ; 0                     ; Untyped                ;
; C3_LOW                        ; 0                     ; Untyped                ;
; C4_LOW                        ; 0                     ; Untyped                ;
; C5_LOW                        ; 0                     ; Untyped                ;
; C6_LOW                        ; 0                     ; Untyped                ;
; C7_LOW                        ; 0                     ; Untyped                ;
; C8_LOW                        ; 0                     ; Untyped                ;
; C9_LOW                        ; 0                     ; Untyped                ;
; C0_INITIAL                    ; 0                     ; Untyped                ;
; C1_INITIAL                    ; 0                     ; Untyped                ;
; C2_INITIAL                    ; 0                     ; Untyped                ;
; C3_INITIAL                    ; 0                     ; Untyped                ;
; C4_INITIAL                    ; 0                     ; Untyped                ;
; C5_INITIAL                    ; 0                     ; Untyped                ;
; C6_INITIAL                    ; 0                     ; Untyped                ;
; C7_INITIAL                    ; 0                     ; Untyped                ;
; C8_INITIAL                    ; 0                     ; Untyped                ;
; C9_INITIAL                    ; 0                     ; Untyped                ;
; C0_MODE                       ; BYPASS                ; Untyped                ;
; C1_MODE                       ; BYPASS                ; Untyped                ;
; C2_MODE                       ; BYPASS                ; Untyped                ;
; C3_MODE                       ; BYPASS                ; Untyped                ;
; C4_MODE                       ; BYPASS                ; Untyped                ;
; C5_MODE                       ; BYPASS                ; Untyped                ;
; C6_MODE                       ; BYPASS                ; Untyped                ;
; C7_MODE                       ; BYPASS                ; Untyped                ;
; C8_MODE                       ; BYPASS                ; Untyped                ;
; C9_MODE                       ; BYPASS                ; Untyped                ;
; C0_PH                         ; 0                     ; Untyped                ;
; C1_PH                         ; 0                     ; Untyped                ;
; C2_PH                         ; 0                     ; Untyped                ;
; C3_PH                         ; 0                     ; Untyped                ;
; C4_PH                         ; 0                     ; Untyped                ;
; C5_PH                         ; 0                     ; Untyped                ;
; C6_PH                         ; 0                     ; Untyped                ;
; C7_PH                         ; 0                     ; Untyped                ;
; C8_PH                         ; 0                     ; Untyped                ;
; C9_PH                         ; 0                     ; Untyped                ;
; L0_HIGH                       ; 1                     ; Untyped                ;
; L1_HIGH                       ; 1                     ; Untyped                ;
; G0_HIGH                       ; 1                     ; Untyped                ;
; G1_HIGH                       ; 1                     ; Untyped                ;
; G2_HIGH                       ; 1                     ; Untyped                ;
; G3_HIGH                       ; 1                     ; Untyped                ;
; E0_HIGH                       ; 1                     ; Untyped                ;
; E1_HIGH                       ; 1                     ; Untyped                ;
; E2_HIGH                       ; 1                     ; Untyped                ;
; E3_HIGH                       ; 1                     ; Untyped                ;
; L0_LOW                        ; 1                     ; Untyped                ;
; L1_LOW                        ; 1                     ; Untyped                ;
; G0_LOW                        ; 1                     ; Untyped                ;
; G1_LOW                        ; 1                     ; Untyped                ;
; G2_LOW                        ; 1                     ; Untyped                ;
; G3_LOW                        ; 1                     ; Untyped                ;
; E0_LOW                        ; 1                     ; Untyped                ;
; E1_LOW                        ; 1                     ; Untyped                ;
; E2_LOW                        ; 1                     ; Untyped                ;
; E3_LOW                        ; 1                     ; Untyped                ;
; L0_INITIAL                    ; 1                     ; Untyped                ;
; L1_INITIAL                    ; 1                     ; Untyped                ;
; G0_INITIAL                    ; 1                     ; Untyped                ;
; G1_INITIAL                    ; 1                     ; Untyped                ;
; G2_INITIAL                    ; 1                     ; Untyped                ;
; G3_INITIAL                    ; 1                     ; Untyped                ;
; E0_INITIAL                    ; 1                     ; Untyped                ;
; E1_INITIAL                    ; 1                     ; Untyped                ;
; E2_INITIAL                    ; 1                     ; Untyped                ;
; E3_INITIAL                    ; 1                     ; Untyped                ;
; L0_MODE                       ; BYPASS                ; Untyped                ;
; L1_MODE                       ; BYPASS                ; Untyped                ;
; G0_MODE                       ; BYPASS                ; Untyped                ;
; G1_MODE                       ; BYPASS                ; Untyped                ;
; G2_MODE                       ; BYPASS                ; Untyped                ;
; G3_MODE                       ; BYPASS                ; Untyped                ;
; E0_MODE                       ; BYPASS                ; Untyped                ;
; E1_MODE                       ; BYPASS                ; Untyped                ;
; E2_MODE                       ; BYPASS                ; Untyped                ;
; E3_MODE                       ; BYPASS                ; Untyped                ;
; L0_PH                         ; 0                     ; Untyped                ;
; L1_PH                         ; 0                     ; Untyped                ;
; G0_PH                         ; 0                     ; Untyped                ;
; G1_PH                         ; 0                     ; Untyped                ;
; G2_PH                         ; 0                     ; Untyped                ;
; G3_PH                         ; 0                     ; Untyped                ;
; E0_PH                         ; 0                     ; Untyped                ;
; E1_PH                         ; 0                     ; Untyped                ;
; E2_PH                         ; 0                     ; Untyped                ;
; E3_PH                         ; 0                     ; Untyped                ;
; M_PH                          ; 0                     ; Untyped                ;
; C1_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C2_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C3_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C4_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C5_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C6_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C7_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C8_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C9_USE_CASC_IN                ; OFF                   ; Untyped                ;
; CLK0_COUNTER                  ; G0                    ; Untyped                ;
; CLK1_COUNTER                  ; G0                    ; Untyped                ;
; CLK2_COUNTER                  ; G0                    ; Untyped                ;
; CLK3_COUNTER                  ; G0                    ; Untyped                ;
; CLK4_COUNTER                  ; G0                    ; Untyped                ;
; CLK5_COUNTER                  ; G0                    ; Untyped                ;
; CLK6_COUNTER                  ; E0                    ; Untyped                ;
; CLK7_COUNTER                  ; E1                    ; Untyped                ;
; CLK8_COUNTER                  ; E2                    ; Untyped                ;
; CLK9_COUNTER                  ; E3                    ; Untyped                ;
; L0_TIME_DELAY                 ; 0                     ; Untyped                ;
; L1_TIME_DELAY                 ; 0                     ; Untyped                ;
; G0_TIME_DELAY                 ; 0                     ; Untyped                ;
; G1_TIME_DELAY                 ; 0                     ; Untyped                ;
; G2_TIME_DELAY                 ; 0                     ; Untyped                ;
; G3_TIME_DELAY                 ; 0                     ; Untyped                ;
; E0_TIME_DELAY                 ; 0                     ; Untyped                ;
; E1_TIME_DELAY                 ; 0                     ; Untyped                ;
; E2_TIME_DELAY                 ; 0                     ; Untyped                ;
; E3_TIME_DELAY                 ; 0                     ; Untyped                ;
; M_TIME_DELAY                  ; 0                     ; Untyped                ;
; N_TIME_DELAY                  ; 0                     ; Untyped                ;
; EXTCLK3_COUNTER               ; E3                    ; Untyped                ;
; EXTCLK2_COUNTER               ; E2                    ; Untyped                ;
; EXTCLK1_COUNTER               ; E1                    ; Untyped                ;
; EXTCLK0_COUNTER               ; E0                    ; Untyped                ;
; ENABLE0_COUNTER               ; L0                    ; Untyped                ;
; ENABLE1_COUNTER               ; L0                    ; Untyped                ;
; CHARGE_PUMP_CURRENT           ; 2                     ; Untyped                ;
; LOOP_FILTER_R                 ;  1.000000             ; Untyped                ;
; LOOP_FILTER_C                 ; 5                     ; Untyped                ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                  ; Untyped                ;
; LOOP_FILTER_R_BITS            ; 9999                  ; Untyped                ;
; LOOP_FILTER_C_BITS            ; 9999                  ; Untyped                ;
; VCO_POST_SCALE                ; 0                     ; Untyped                ;
; CLK2_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; CLK1_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; CLK0_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E          ; Untyped                ;
; PORT_CLKENA0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA2                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA3                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA4                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA5                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLK0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK2                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK3                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKBAD0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKBAD1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK0                     ; PORT_USED             ; Untyped                ;
; PORT_CLK1                     ; PORT_USED             ; Untyped                ;
; PORT_CLK2                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK3                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK4                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK5                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK6                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK7                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK8                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK9                     ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDATA                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDATAOUT              ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDONE                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKLOSS                  ; PORT_UNUSED           ; Untyped                ;
; PORT_INCLK1                   ; PORT_UNUSED           ; Untyped                ;
; PORT_INCLK0                   ; PORT_USED             ; Untyped                ;
; PORT_FBIN                     ; PORT_UNUSED           ; Untyped                ;
; PORT_PLLENA                   ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKSWITCH                ; PORT_UNUSED           ; Untyped                ;
; PORT_ARESET                   ; PORT_UNUSED           ; Untyped                ;
; PORT_PFDENA                   ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANCLK                  ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANACLR                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANREAD                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANWRITE                ; PORT_UNUSED           ; Untyped                ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_LOCKED                   ; PORT_UNUSED           ; Untyped                ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED           ; Untyped                ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_PHASEDONE                ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASESTEP                ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANCLKENA               ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED           ; Untyped                ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY     ; Untyped                ;
; M_TEST_SOURCE                 ; 5                     ; Untyped                ;
; C0_TEST_SOURCE                ; 5                     ; Untyped                ;
; C1_TEST_SOURCE                ; 5                     ; Untyped                ;
; C2_TEST_SOURCE                ; 5                     ; Untyped                ;
; C3_TEST_SOURCE                ; 5                     ; Untyped                ;
; C4_TEST_SOURCE                ; 5                     ; Untyped                ;
; C5_TEST_SOURCE                ; 5                     ; Untyped                ;
; C6_TEST_SOURCE                ; 5                     ; Untyped                ;
; C7_TEST_SOURCE                ; 5                     ; Untyped                ;
; C8_TEST_SOURCE                ; 5                     ; Untyped                ;
; C9_TEST_SOURCE                ; 5                     ; Untyped                ;
; CBXI_PARAMETER                ; PLL_altpll            ; Untyped                ;
; VCO_FREQUENCY_CONTROL         ; AUTO                  ; Untyped                ;
; VCO_PHASE_SHIFT_STEP          ; 0                     ; Untyped                ;
; WIDTH_CLOCK                   ; 5                     ; Signed Integer         ;
; WIDTH_PHASECOUNTERSELECT      ; 4                     ; Untyped                ;
; USING_FBMIMICBIDIR_PORT       ; OFF                   ; Untyped                ;
; DEVICE_FAMILY                 ; Cyclone IV E          ; Untyped                ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                ; Untyped                ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                   ; Untyped                ;
; AUTO_CARRY_CHAINS             ; ON                    ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS          ; OFF                   ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS           ; ON                    ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS        ; OFF                   ; IGNORE_CASCADE         ;
+-------------------------------+-----------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data ;
+----------------+--------+------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                         ;
+----------------+--------+------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                       ;
+----------------+--------+------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+----------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                 ;
+------------------------------------+----------------------+----------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                              ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                       ;
; WIDTHAD_A                          ; 9                    ; Signed Integer                                                       ;
; NUMWORDS_A                         ; 512                  ; Signed Integer                                                       ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                              ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                       ;
; WIDTHAD_B                          ; 9                    ; Signed Integer                                                       ;
; NUMWORDS_B                         ; 512                  ; Signed Integer                                                       ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                              ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                              ;
; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                                                              ;
; CBXI_PARAMETER                     ; altsyncram_udd1      ; Untyped                                                              ;
+------------------------------------+----------------------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag ;
+----------------+--------------------+----------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                           ;
+----------------+--------------------+----------------------------------------------------------------+
; lpm_file       ; cpu_ic_tag_ram.mif ; String                                                         ;
+----------------+--------------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+--------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                               ;
+------------------------------------+----------------------+--------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                            ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                       ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                     ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                            ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                            ;
; WIDTH_A                            ; 24                   ; Signed Integer                                                     ;
; WIDTHAD_A                          ; 6                    ; Signed Integer                                                     ;
; NUMWORDS_A                         ; 64                   ; Signed Integer                                                     ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                            ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                            ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                            ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                            ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                            ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                            ;
; WIDTH_B                            ; 24                   ; Signed Integer                                                     ;
; WIDTHAD_B                          ; 6                    ; Signed Integer                                                     ;
; NUMWORDS_B                         ; 64                   ; Signed Integer                                                     ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                            ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                            ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                            ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                            ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                            ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                            ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                            ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                            ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                            ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                            ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                            ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                            ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                            ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                            ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                            ;
; INIT_FILE                          ; cpu_ic_tag_ram.mif   ; Untyped                                                            ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                            ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                     ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                            ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                            ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                            ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                            ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                            ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                            ;
; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                                                            ;
; CBXI_PARAMETER                     ; altsyncram_i2g1      ; Untyped                                                            ;
+------------------------------------+----------------------+--------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht ;
+----------------+-----------------+-------------------------------------------------------------+
; Parameter Name ; Value           ; Type                                                        ;
+----------------+-----------------+-------------------------------------------------------------+
; lpm_file       ; cpu_bht_ram.mif ; String                                                      ;
+----------------+-----------------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+--------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                         ;
+------------------------------------+----------------------+--------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                      ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                   ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                 ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                               ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                      ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                      ;
; WIDTH_A                            ; 2                    ; Signed Integer                                               ;
; WIDTHAD_A                          ; 8                    ; Signed Integer                                               ;
; NUMWORDS_A                         ; 256                  ; Signed Integer                                               ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                      ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                      ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                      ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                      ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                      ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                      ;
; WIDTH_B                            ; 2                    ; Signed Integer                                               ;
; WIDTHAD_B                          ; 8                    ; Signed Integer                                               ;
; NUMWORDS_B                         ; 256                  ; Signed Integer                                               ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                      ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                      ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                      ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                      ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                      ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                      ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                      ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                      ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                      ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                      ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                      ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                      ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                      ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                      ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                      ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                      ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                      ;
; INIT_FILE                          ; cpu_bht_ram.mif      ; Untyped                                                      ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                      ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                               ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                      ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                      ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                      ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                      ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                      ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                      ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                      ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                      ;
; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                                                      ;
; CBXI_PARAMETER                     ; altsyncram_bpf1      ; Untyped                                                      ;
+------------------------------------+----------------------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a ;
+----------------+------------------+------------------------------------------------------------------------------------+
; Parameter Name ; Value            ; Type                                                                               ;
+----------------+------------------+------------------------------------------------------------------------------------+
; lpm_file       ; cpu_rf_ram_a.mif ; String                                                                             ;
+----------------+------------------+------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                 ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                              ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                       ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                       ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                       ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                              ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                       ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                       ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                       ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                              ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                              ;
; INIT_FILE                          ; cpu_rf_ram_a.mif     ; Untyped                                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                              ;
; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                                                                              ;
; CBXI_PARAMETER                     ; altsyncram_b7f1      ; Untyped                                                                              ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b ;
+----------------+------------------+------------------------------------------------------------------------------------+
; Parameter Name ; Value            ; Type                                                                               ;
+----------------+------------------+------------------------------------------------------------------------------------+
; lpm_file       ; cpu_rf_ram_b.mif ; String                                                                             ;
+----------------+------------------+------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                 ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                              ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                       ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                       ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                       ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                              ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                       ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                       ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                       ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                              ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                              ;
; INIT_FILE                          ; cpu_rf_ram_b.mif     ; Untyped                                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                              ;
; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                                                                              ;
; CBXI_PARAMETER                     ; altsyncram_c7f1      ; Untyped                                                                              ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1 ;
+---------------------------------------+-------------------+--------------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                           ;
+---------------------------------------+-------------------+--------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                                     ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                                   ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                                   ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                                 ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                        ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                        ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                        ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                        ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                        ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                        ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                        ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                        ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0             ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED      ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                        ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                        ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                        ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES               ; Untyped                                                                        ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                        ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                        ;
; INPUT_ACLR_A0                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_B0                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_REGISTER_A0                     ; UNREGISTERED      ; Untyped                                                                        ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_B0                     ; UNREGISTERED      ; Untyped                                                                        ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                        ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                        ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                        ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                        ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                        ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                        ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                        ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                        ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                        ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                        ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                        ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                        ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                        ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                        ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                        ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                        ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                        ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                        ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                        ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                        ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                        ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                        ;
; MULTIPLIER_ACLR0                      ; ACLR0             ; Untyped                                                                        ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                        ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                        ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                        ;
; MULTIPLIER_REGISTER0                  ; CLOCK0            ; Untyped                                                                        ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                        ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                        ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                        ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                                 ;
; OUTPUT_ACLR                           ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_REGISTER                       ; UNREGISTERED      ; Untyped                                                                        ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                        ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                        ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                        ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                        ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                        ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                        ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                        ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                        ;
; port_addnsub1                         ; PORT_UNUSED       ; Untyped                                                                        ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                        ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                        ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                        ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                        ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                        ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                        ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                        ;
; port_signa                            ; PORT_UNUSED       ; Untyped                                                                        ;
; port_signb                            ; PORT_UNUSED       ; Untyped                                                                        ;
; REPRESENTATION_A                      ; UNSIGNED          ; Untyped                                                                        ;
; REPRESENTATION_B                      ; UNSIGNED          ; Untyped                                                                        ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                        ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                        ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                        ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                        ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                        ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                        ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                        ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                        ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                        ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                        ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                        ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                        ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                        ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                        ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                        ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                        ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                        ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                        ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                        ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0             ; Untyped                                                                        ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0             ; Untyped                                                                        ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                        ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                        ;
; SIGNED_REGISTER_A                     ; UNREGISTERED      ; Untyped                                                                        ;
; SIGNED_REGISTER_B                     ; UNREGISTERED      ; Untyped                                                                        ;
; WIDTH_A                               ; 16                ; Signed Integer                                                                 ;
; WIDTH_B                               ; 16                ; Signed Integer                                                                 ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                        ;
; WIDTH_RESULT                          ; 32                ; Signed Integer                                                                 ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                        ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                        ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                        ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                        ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                        ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                        ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                        ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                        ;
; CBXI_PARAMETER                        ; mult_add_mgr2     ; Untyped                                                                        ;
; DEVICE_FAMILY                         ; Cyclone IV E      ; Untyped                                                                        ;
; WIDTH_C                               ; 22                ; Untyped                                                                        ;
; LOADCONST_VALUE                       ; 64                ; Untyped                                                                        ;
; PREADDER_MODE                         ; SIMPLE            ; Untyped                                                                        ;
; PREADDER_DIRECTION_0                  ; ADD               ; Untyped                                                                        ;
; PREADDER_DIRECTION_1                  ; ADD               ; Untyped                                                                        ;
; PREADDER_DIRECTION_2                  ; ADD               ; Untyped                                                                        ;
; PREADDER_DIRECTION_3                  ; ADD               ; Untyped                                                                        ;
; INPUT_REGISTER_C0                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_ACLR_C0                         ; ACLR0             ; Untyped                                                                        ;
; COEFSEL0_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; COEFSEL1_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; COEFSEL2_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; COEFSEL3_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; COEFSEL0_ACLR                         ; ACLR0             ; Untyped                                                                        ;
; COEFSEL1_ACLR                         ; ACLR0             ; Untyped                                                                        ;
; COEFSEL2_ACLR                         ; ACLR0             ; Untyped                                                                        ;
; COEFSEL3_ACLR                         ; ACLR0             ; Untyped                                                                        ;
; SYSTOLIC_DELAY1                       ; CLOCK0            ; Untyped                                                                        ;
; SYSTOLIC_DELAY3                       ; CLOCK0            ; Untyped                                                                        ;
; SYSTOLIC_ACLR1                        ; ACLR0             ; Untyped                                                                        ;
; SYSTOLIC_ACLR3                        ; ACLR0             ; Untyped                                                                        ;
; COEF0_0                               ; 0                 ; Untyped                                                                        ;
; COEF0_1                               ; 0                 ; Untyped                                                                        ;
; COEF0_2                               ; 0                 ; Untyped                                                                        ;
; COEF0_3                               ; 0                 ; Untyped                                                                        ;
; COEF0_4                               ; 0                 ; Untyped                                                                        ;
; COEF0_5                               ; 0                 ; Untyped                                                                        ;
; COEF0_6                               ; 0                 ; Untyped                                                                        ;
; COEF0_7                               ; 0                 ; Untyped                                                                        ;
; COEF1_0                               ; 0                 ; Untyped                                                                        ;
; COEF1_1                               ; 0                 ; Untyped                                                                        ;
; COEF1_2                               ; 0                 ; Untyped                                                                        ;
; COEF1_3                               ; 0                 ; Untyped                                                                        ;
; COEF1_4                               ; 0                 ; Untyped                                                                        ;
; COEF1_5                               ; 0                 ; Untyped                                                                        ;
; COEF1_6                               ; 0                 ; Untyped                                                                        ;
; COEF1_7                               ; 0                 ; Untyped                                                                        ;
; COEF2_0                               ; 0                 ; Untyped                                                                        ;
; COEF2_1                               ; 0                 ; Untyped                                                                        ;
; COEF2_2                               ; 0                 ; Untyped                                                                        ;
; COEF2_3                               ; 0                 ; Untyped                                                                        ;
; COEF2_4                               ; 0                 ; Untyped                                                                        ;
; COEF2_5                               ; 0                 ; Untyped                                                                        ;
; COEF2_6                               ; 0                 ; Untyped                                                                        ;
; COEF2_7                               ; 0                 ; Untyped                                                                        ;
; COEF3_0                               ; 0                 ; Untyped                                                                        ;
; COEF3_1                               ; 0                 ; Untyped                                                                        ;
; COEF3_2                               ; 0                 ; Untyped                                                                        ;
; COEF3_3                               ; 0                 ; Untyped                                                                        ;
; COEF3_4                               ; 0                 ; Untyped                                                                        ;
; COEF3_5                               ; 0                 ; Untyped                                                                        ;
; COEF3_6                               ; 0                 ; Untyped                                                                        ;
; COEF3_7                               ; 0                 ; Untyped                                                                        ;
; WIDTH_COEF                            ; 18                ; Untyped                                                                        ;
+---------------------------------------+-------------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2 ;
+---------------------------------------+-------------------+--------------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                           ;
+---------------------------------------+-------------------+--------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                                     ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                                   ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                                   ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                                 ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                        ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                        ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                        ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                        ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                        ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                        ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                        ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                        ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0             ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED      ; Untyped                                                                        ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                        ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                        ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                        ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                        ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                        ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES               ; Untyped                                                                        ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                        ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                        ;
; INPUT_ACLR_A0                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_B0                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                        ;
; INPUT_REGISTER_A0                     ; UNREGISTERED      ; Untyped                                                                        ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_B0                     ; UNREGISTERED      ; Untyped                                                                        ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                        ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                        ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                        ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                        ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                        ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                        ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                        ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                        ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                        ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                        ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                        ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                        ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                        ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                        ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                        ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                        ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                        ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                        ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                        ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                        ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                        ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                        ;
; MULTIPLIER_ACLR0                      ; ACLR0             ; Untyped                                                                        ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                        ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                        ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                        ;
; MULTIPLIER_REGISTER0                  ; CLOCK0            ; Untyped                                                                        ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                        ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                        ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                        ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                                 ;
; OUTPUT_ACLR                           ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_REGISTER                       ; UNREGISTERED      ; Untyped                                                                        ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                        ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                        ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                        ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                        ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                        ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                        ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                        ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                        ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                        ;
; port_addnsub1                         ; PORT_UNUSED       ; Untyped                                                                        ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                        ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                        ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                        ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                        ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                        ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                        ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                        ;
; port_signa                            ; PORT_UNUSED       ; Untyped                                                                        ;
; port_signb                            ; PORT_UNUSED       ; Untyped                                                                        ;
; REPRESENTATION_A                      ; UNSIGNED          ; Untyped                                                                        ;
; REPRESENTATION_B                      ; UNSIGNED          ; Untyped                                                                        ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                        ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                        ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                        ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                        ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                        ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                        ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                        ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                        ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                        ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                        ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                        ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                        ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                        ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                        ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                        ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                        ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                        ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                        ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                        ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0             ; Untyped                                                                        ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0             ; Untyped                                                                        ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                        ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                        ;
; SIGNED_REGISTER_A                     ; UNREGISTERED      ; Untyped                                                                        ;
; SIGNED_REGISTER_B                     ; UNREGISTERED      ; Untyped                                                                        ;
; WIDTH_A                               ; 16                ; Signed Integer                                                                 ;
; WIDTH_B                               ; 16                ; Signed Integer                                                                 ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                        ;
; WIDTH_RESULT                          ; 16                ; Signed Integer                                                                 ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                        ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                        ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                        ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                        ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                        ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                        ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                        ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                        ;
; CBXI_PARAMETER                        ; mult_add_ogr2     ; Untyped                                                                        ;
; DEVICE_FAMILY                         ; Cyclone IV E      ; Untyped                                                                        ;
; WIDTH_C                               ; 22                ; Untyped                                                                        ;
; LOADCONST_VALUE                       ; 64                ; Untyped                                                                        ;
; PREADDER_MODE                         ; SIMPLE            ; Untyped                                                                        ;
; PREADDER_DIRECTION_0                  ; ADD               ; Untyped                                                                        ;
; PREADDER_DIRECTION_1                  ; ADD               ; Untyped                                                                        ;
; PREADDER_DIRECTION_2                  ; ADD               ; Untyped                                                                        ;
; PREADDER_DIRECTION_3                  ; ADD               ; Untyped                                                                        ;
; INPUT_REGISTER_C0                     ; CLOCK0            ; Untyped                                                                        ;
; INPUT_ACLR_C0                         ; ACLR0             ; Untyped                                                                        ;
; COEFSEL0_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; COEFSEL1_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; COEFSEL2_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; COEFSEL3_REGISTER                     ; CLOCK0            ; Untyped                                                                        ;
; COEFSEL0_ACLR                         ; ACLR0             ; Untyped                                                                        ;
; COEFSEL1_ACLR                         ; ACLR0             ; Untyped                                                                        ;
; COEFSEL2_ACLR                         ; ACLR0             ; Untyped                                                                        ;
; COEFSEL3_ACLR                         ; ACLR0             ; Untyped                                                                        ;
; SYSTOLIC_DELAY1                       ; CLOCK0            ; Untyped                                                                        ;
; SYSTOLIC_DELAY3                       ; CLOCK0            ; Untyped                                                                        ;
; SYSTOLIC_ACLR1                        ; ACLR0             ; Untyped                                                                        ;
; SYSTOLIC_ACLR3                        ; ACLR0             ; Untyped                                                                        ;
; COEF0_0                               ; 0                 ; Untyped                                                                        ;
; COEF0_1                               ; 0                 ; Untyped                                                                        ;
; COEF0_2                               ; 0                 ; Untyped                                                                        ;
; COEF0_3                               ; 0                 ; Untyped                                                                        ;
; COEF0_4                               ; 0                 ; Untyped                                                                        ;
; COEF0_5                               ; 0                 ; Untyped                                                                        ;
; COEF0_6                               ; 0                 ; Untyped                                                                        ;
; COEF0_7                               ; 0                 ; Untyped                                                                        ;
; COEF1_0                               ; 0                 ; Untyped                                                                        ;
; COEF1_1                               ; 0                 ; Untyped                                                                        ;
; COEF1_2                               ; 0                 ; Untyped                                                                        ;
; COEF1_3                               ; 0                 ; Untyped                                                                        ;
; COEF1_4                               ; 0                 ; Untyped                                                                        ;
; COEF1_5                               ; 0                 ; Untyped                                                                        ;
; COEF1_6                               ; 0                 ; Untyped                                                                        ;
; COEF1_7                               ; 0                 ; Untyped                                                                        ;
; COEF2_0                               ; 0                 ; Untyped                                                                        ;
; COEF2_1                               ; 0                 ; Untyped                                                                        ;
; COEF2_2                               ; 0                 ; Untyped                                                                        ;
; COEF2_3                               ; 0                 ; Untyped                                                                        ;
; COEF2_4                               ; 0                 ; Untyped                                                                        ;
; COEF2_5                               ; 0                 ; Untyped                                                                        ;
; COEF2_6                               ; 0                 ; Untyped                                                                        ;
; COEF2_7                               ; 0                 ; Untyped                                                                        ;
; COEF3_0                               ; 0                 ; Untyped                                                                        ;
; COEF3_1                               ; 0                 ; Untyped                                                                        ;
; COEF3_2                               ; 0                 ; Untyped                                                                        ;
; COEF3_3                               ; 0                 ; Untyped                                                                        ;
; COEF3_4                               ; 0                 ; Untyped                                                                        ;
; COEF3_5                               ; 0                 ; Untyped                                                                        ;
; COEF3_6                               ; 0                 ; Untyped                                                                        ;
; COEF3_7                               ; 0                 ; Untyped                                                                        ;
; WIDTH_COEF                            ; 18                ; Untyped                                                                        ;
+---------------------------------------+-------------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component ;
+----------------+---------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value                           ; Type                                                                                                                                                                  ;
+----------------+---------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; cpu_ociram_default_contents.mif ; String                                                                                                                                                                ;
+----------------+---------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+---------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                           ; Type                                                                                                                                                                        ;
+------------------------------------+---------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                               ; Untyped                                                                                                                                                                     ;
; AUTO_CARRY_CHAINS                  ; ON                              ; AUTO_CARRY                                                                                                                                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF                             ; IGNORE_CARRY                                                                                                                                                                ;
; AUTO_CASCADE_CHAINS                ; ON                              ; AUTO_CASCADE                                                                                                                                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF                             ; IGNORE_CASCADE                                                                                                                                                              ;
; WIDTH_BYTEENA                      ; 1                               ; Untyped                                                                                                                                                                     ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT                 ; Untyped                                                                                                                                                                     ;
; WIDTH_A                            ; 32                              ; Signed Integer                                                                                                                                                              ;
; WIDTHAD_A                          ; 8                               ; Signed Integer                                                                                                                                                              ;
; NUMWORDS_A                         ; 256                             ; Signed Integer                                                                                                                                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED                    ; Untyped                                                                                                                                                                     ;
; ADDRESS_ACLR_A                     ; NONE                            ; Untyped                                                                                                                                                                     ;
; OUTDATA_ACLR_A                     ; NONE                            ; Untyped                                                                                                                                                                     ;
; WRCONTROL_ACLR_A                   ; NONE                            ; Untyped                                                                                                                                                                     ;
; INDATA_ACLR_A                      ; NONE                            ; Untyped                                                                                                                                                                     ;
; BYTEENA_ACLR_A                     ; NONE                            ; Untyped                                                                                                                                                                     ;
; WIDTH_B                            ; 32                              ; Signed Integer                                                                                                                                                              ;
; WIDTHAD_B                          ; 8                               ; Signed Integer                                                                                                                                                              ;
; NUMWORDS_B                         ; 256                             ; Signed Integer                                                                                                                                                              ;
; INDATA_REG_B                       ; CLOCK1                          ; Untyped                                                                                                                                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                          ; Untyped                                                                                                                                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1                          ; Untyped                                                                                                                                                                     ;
; ADDRESS_REG_B                      ; CLOCK1                          ; Untyped                                                                                                                                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED                    ; Untyped                                                                                                                                                                     ;
; BYTEENA_REG_B                      ; CLOCK1                          ; Untyped                                                                                                                                                                     ;
; INDATA_ACLR_B                      ; NONE                            ; Untyped                                                                                                                                                                     ;
; WRCONTROL_ACLR_B                   ; NONE                            ; Untyped                                                                                                                                                                     ;
; ADDRESS_ACLR_B                     ; NONE                            ; Untyped                                                                                                                                                                     ;
; OUTDATA_ACLR_B                     ; NONE                            ; Untyped                                                                                                                                                                     ;
; RDCONTROL_ACLR_B                   ; NONE                            ; Untyped                                                                                                                                                                     ;
; BYTEENA_ACLR_B                     ; NONE                            ; Untyped                                                                                                                                                                     ;
; WIDTH_BYTEENA_A                    ; 4                               ; Signed Integer                                                                                                                                                              ;
; WIDTH_BYTEENA_B                    ; 1                               ; Untyped                                                                                                                                                                     ;
; RAM_BLOCK_TYPE                     ; AUTO                            ; Untyped                                                                                                                                                                     ;
; BYTE_SIZE                          ; 8                               ; Untyped                                                                                                                                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                        ; Untyped                                                                                                                                                                     ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ            ; Untyped                                                                                                                                                                     ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ            ; Untyped                                                                                                                                                                     ;
; INIT_FILE                          ; cpu_ociram_default_contents.mif ; Untyped                                                                                                                                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A                          ; Untyped                                                                                                                                                                     ;
; MAXIMUM_DEPTH                      ; 0                               ; Untyped                                                                                                                                                                     ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                          ; Untyped                                                                                                                                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                          ; Untyped                                                                                                                                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                          ; Untyped                                                                                                                                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                          ; Untyped                                                                                                                                                                     ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                 ; Untyped                                                                                                                                                                     ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                 ; Untyped                                                                                                                                                                     ;
; ENABLE_ECC                         ; FALSE                           ; Untyped                                                                                                                                                                     ;
; WIDTH_ECCSTATUS                    ; 3                               ; Untyped                                                                                                                                                                     ;
; DEVICE_FAMILY                      ; Cyclone IV E                    ; Untyped                                                                                                                                                                     ;
; CBXI_PARAMETER                     ; altsyncram_f572                 ; Untyped                                                                                                                                                                     ;
+------------------------------------+---------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                               ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                             ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                       ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                    ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                 ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                               ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                               ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                             ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                    ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                                                                                                                                    ;
; WIDTH_A                            ; 36                   ; Signed Integer                                                                                                                                                                             ;
; WIDTHAD_A                          ; 7                    ; Signed Integer                                                                                                                                                                             ;
; NUMWORDS_A                         ; 128                  ; Signed Integer                                                                                                                                                                             ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                    ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                    ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                    ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                    ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                    ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                    ;
; WIDTH_B                            ; 36                   ; Signed Integer                                                                                                                                                                             ;
; WIDTHAD_B                          ; 7                    ; Signed Integer                                                                                                                                                                             ;
; NUMWORDS_B                         ; 128                  ; Signed Integer                                                                                                                                                                             ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                    ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                    ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                    ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                    ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                    ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                    ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                    ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                    ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                    ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                    ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                    ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                    ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                                                                                                                    ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                    ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                    ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                                                                                                                    ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                                                                                                                                    ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                    ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                    ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                    ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                    ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                    ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                    ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                    ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                    ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                    ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                    ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                    ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                    ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                    ;
; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                                                                                                                                                                                    ;
; CBXI_PARAMETER                     ; altsyncram_0a02      ; Untyped                                                                                                                                                                                    ;
+------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                       ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                             ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                              ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                              ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                    ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                              ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                    ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy ;
+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value                  ; Type                                                                                                                                                                  ;
+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sld_mfg_id              ; 70                     ; Signed Integer                                                                                                                                                        ;
; sld_type_id             ; 34                     ; Signed Integer                                                                                                                                                        ;
; sld_version             ; 3                      ; Signed Integer                                                                                                                                                        ;
; sld_instance_index      ; 0                      ; Signed Integer                                                                                                                                                        ;
; sld_auto_instance_index ; YES                    ; String                                                                                                                                                                ;
; sld_ir_width            ; 2                      ; Signed Integer                                                                                                                                                        ;
; sld_sim_n_scan          ; 0                      ; Signed Integer                                                                                                                                                        ;
; sld_sim_action          ;                        ; String                                                                                                                                                                ;
; sld_sim_total_length    ; 0                      ; Signed Integer                                                                                                                                                        ;
; lpm_type                ; sld_virtual_jtag_basic ; String                                                                                                                                                                ;
; lpm_hint                ; UNUSED                 ; String                                                                                                                                                                ;
+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|epcs:the_epcs ;
+----------------+-------------------+--------------------------------------+
; Parameter Name ; Value             ; Type                                 ;
+----------------+-------------------+--------------------------------------+
; INIT_FILE      ; epcs_boot_rom.hex ; String                               ;
+----------------+-------------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom ;
+------------------------------------+-------------------------+-------------------------------------------+
; Parameter Name                     ; Value                   ; Type                                      ;
+------------------------------------+-------------------------+-------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                       ; Untyped                                   ;
; AUTO_CARRY_CHAINS                  ; ON                      ; AUTO_CARRY                                ;
; IGNORE_CARRY_BUFFERS               ; OFF                     ; IGNORE_CARRY                              ;
; AUTO_CASCADE_CHAINS                ; ON                      ; AUTO_CASCADE                              ;
; IGNORE_CASCADE_BUFFERS             ; OFF                     ; IGNORE_CASCADE                            ;
; WIDTH_BYTEENA                      ; 1                       ; Untyped                                   ;
; OPERATION_MODE                     ; ROM                     ; Untyped                                   ;
; WIDTH_A                            ; 32                      ; Signed Integer                            ;
; WIDTHAD_A                          ; 8                       ; Signed Integer                            ;
; NUMWORDS_A                         ; 256                     ; Signed Integer                            ;
; OUTDATA_REG_A                      ; UNREGISTERED            ; Untyped                                   ;
; ADDRESS_ACLR_A                     ; NONE                    ; Untyped                                   ;
; OUTDATA_ACLR_A                     ; NONE                    ; Untyped                                   ;
; WRCONTROL_ACLR_A                   ; NONE                    ; Untyped                                   ;
; INDATA_ACLR_A                      ; NONE                    ; Untyped                                   ;
; BYTEENA_ACLR_A                     ; NONE                    ; Untyped                                   ;
; WIDTH_B                            ; 1                       ; Untyped                                   ;
; WIDTHAD_B                          ; 1                       ; Untyped                                   ;
; NUMWORDS_B                         ; 1                       ; Untyped                                   ;
; INDATA_REG_B                       ; CLOCK1                  ; Untyped                                   ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                  ; Untyped                                   ;
; RDCONTROL_REG_B                    ; CLOCK1                  ; Untyped                                   ;
; ADDRESS_REG_B                      ; CLOCK1                  ; Untyped                                   ;
; OUTDATA_REG_B                      ; UNREGISTERED            ; Untyped                                   ;
; BYTEENA_REG_B                      ; CLOCK1                  ; Untyped                                   ;
; INDATA_ACLR_B                      ; NONE                    ; Untyped                                   ;
; WRCONTROL_ACLR_B                   ; NONE                    ; Untyped                                   ;
; ADDRESS_ACLR_B                     ; NONE                    ; Untyped                                   ;
; OUTDATA_ACLR_B                     ; NONE                    ; Untyped                                   ;
; RDCONTROL_ACLR_B                   ; NONE                    ; Untyped                                   ;
; BYTEENA_ACLR_B                     ; NONE                    ; Untyped                                   ;
; WIDTH_BYTEENA_A                    ; 1                       ; Untyped                                   ;
; WIDTH_BYTEENA_B                    ; 1                       ; Untyped                                   ;
; RAM_BLOCK_TYPE                     ; AUTO                    ; Untyped                                   ;
; BYTE_SIZE                          ; 8                       ; Signed Integer                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE               ; Untyped                                   ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ    ; Untyped                                   ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ    ; Untyped                                   ;
; INIT_FILE                          ; epcs_boot_rom_synth.hex ; Untyped                                   ;
; INIT_FILE_LAYOUT                   ; PORT_A                  ; Untyped                                   ;
; MAXIMUM_DEPTH                      ; 0                       ; Untyped                                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                  ; Untyped                                   ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                  ; Untyped                                   ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                  ; Untyped                                   ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                  ; Untyped                                   ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN         ; Untyped                                   ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN         ; Untyped                                   ;
; ENABLE_ECC                         ; FALSE                   ; Untyped                                   ;
; WIDTH_ECCSTATUS                    ; 3                       ; Untyped                                   ;
; DEVICE_FAMILY                      ; Cyclone IV E            ; Untyped                                   ;
; CBXI_PARAMETER                     ; altsyncram_sc31         ; Untyped                                   ;
+------------------------------------+-------------------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo ;
+-------------------------+--------------+---------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value        ; Type                                                                                              ;
+-------------------------+--------------+---------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON           ; AUTO_CARRY                                                                                        ;
; IGNORE_CARRY_BUFFERS    ; OFF          ; IGNORE_CARRY                                                                                      ;
; AUTO_CASCADE_CHAINS     ; ON           ; AUTO_CASCADE                                                                                      ;
; IGNORE_CASCADE_BUFFERS  ; OFF          ; IGNORE_CASCADE                                                                                    ;
; lpm_width               ; 8            ; Signed Integer                                                                                    ;
; LPM_NUMWORDS            ; 64           ; Signed Integer                                                                                    ;
; LPM_WIDTHU              ; 6            ; Signed Integer                                                                                    ;
; LPM_SHOWAHEAD           ; OFF          ; Untyped                                                                                           ;
; UNDERFLOW_CHECKING      ; OFF          ; Untyped                                                                                           ;
; OVERFLOW_CHECKING       ; OFF          ; Untyped                                                                                           ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF          ; Untyped                                                                                           ;
; ADD_RAM_OUTPUT_REGISTER ; OFF          ; Untyped                                                                                           ;
; ALMOST_FULL_VALUE       ; 0            ; Untyped                                                                                           ;
; ALMOST_EMPTY_VALUE      ; 0            ; Untyped                                                                                           ;
; USE_EAB                 ; ON           ; Untyped                                                                                           ;
; MAXIMIZE_SPEED          ; 5            ; Untyped                                                                                           ;
; DEVICE_FAMILY           ; Cyclone IV E ; Untyped                                                                                           ;
; OPTIMIZE_FOR_SPEED      ; 5            ; Untyped                                                                                           ;
; CBXI_PARAMETER          ; scfifo_jr21  ; Untyped                                                                                           ;
+-------------------------+--------------+---------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo ;
+-------------------------+--------------+---------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value        ; Type                                                                                              ;
+-------------------------+--------------+---------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON           ; AUTO_CARRY                                                                                        ;
; IGNORE_CARRY_BUFFERS    ; OFF          ; IGNORE_CARRY                                                                                      ;
; AUTO_CASCADE_CHAINS     ; ON           ; AUTO_CASCADE                                                                                      ;
; IGNORE_CASCADE_BUFFERS  ; OFF          ; IGNORE_CASCADE                                                                                    ;
; lpm_width               ; 8            ; Signed Integer                                                                                    ;
; LPM_NUMWORDS            ; 64           ; Signed Integer                                                                                    ;
; LPM_WIDTHU              ; 6            ; Signed Integer                                                                                    ;
; LPM_SHOWAHEAD           ; OFF          ; Untyped                                                                                           ;
; UNDERFLOW_CHECKING      ; OFF          ; Untyped                                                                                           ;
; OVERFLOW_CHECKING       ; OFF          ; Untyped                                                                                           ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF          ; Untyped                                                                                           ;
; ADD_RAM_OUTPUT_REGISTER ; OFF          ; Untyped                                                                                           ;
; ALMOST_FULL_VALUE       ; 0            ; Untyped                                                                                           ;
; ALMOST_EMPTY_VALUE      ; 0            ; Untyped                                                                                           ;
; USE_EAB                 ; ON           ; Untyped                                                                                           ;
; MAXIMIZE_SPEED          ; 5            ; Untyped                                                                                           ;
; DEVICE_FAMILY           ; Cyclone IV E ; Untyped                                                                                           ;
; OPTIMIZE_FOR_SPEED      ; 5            ; Untyped                                                                                           ;
; CBXI_PARAMETER          ; scfifo_jr21  ; Untyped                                                                                           ;
+-------------------------+--------------+---------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic ;
+-------------------------+----------------------------------+----------------------------------------------------------------------+
; Parameter Name          ; Value                            ; Type                                                                 ;
+-------------------------+----------------------------------+----------------------------------------------------------------------+
; INSTANCE_ID             ; 0                                ; Signed Integer                                                       ;
; SLD_NODE_INFO           ; 00001100000000000110111000000000 ; Unsigned Binary                                                      ;
; SLD_AUTO_INSTANCE_INDEX ; YES                              ; String                                                               ;
; LOG2_TXFIFO_DEPTH       ; 6                                ; Signed Integer                                                       ;
; LOG2_RXFIFO_DEPTH       ; 6                                ; Signed Integer                                                       ;
; RESERVED                ; 0                                ; Signed Integer                                                       ;
; DATA_WIDTH              ; 8                                ; Signed Integer                                                       ;
; NODE_IR_WIDTH           ; 1                                ; Signed Integer                                                       ;
; SCAN_LENGTH             ; 11                               ; Signed Integer                                                       ;
+-------------------------+----------------------------------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub                                             ;
+--------------------------+------------------------------------------------------------------+-----------------+
; Parameter Name           ; Value                                                            ; Type            ;
+--------------------------+------------------------------------------------------------------+-----------------+
; sld_hub_ip_version       ; 1                                                                ; Untyped         ;
; sld_hub_ip_minor_version ; 4                                                                ; Untyped         ;
; sld_common_ip_version    ; 0                                                                ; Untyped         ;
; device_family            ; Cyclone IV E                                                     ; Untyped         ;
; n_nodes                  ; 2                                                                ; Untyped         ;
; n_sel_bits               ; 2                                                                ; Untyped         ;
; n_node_ir_bits           ; 5                                                                ; Untyped         ;
; node_info                ; 0000110000000000011011100000000000011001000100000100011000000000 ; Unsigned Binary ;
; compilation_mode         ; 1                                                                ; Untyped         ;
; BROADCAST_FEATURE        ; 1                                                                ; Signed Integer  ;
; FORCE_IR_CAPTURE_FEATURE ; 1                                                                ; Signed Integer  ;
+--------------------------+------------------------------------------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CORE_SOPC:inst|cpu:the_cpu|lpm_add_sub:Add10 ;
+------------------------+--------------+-------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                  ;
+------------------------+--------------+-------------------------------------------------------+
; LPM_WIDTH              ; 33           ; Untyped                                               ;
; LPM_REPRESENTATION     ; UNSIGNED     ; Untyped                                               ;
; LPM_DIRECTION          ; DEFAULT      ; Untyped                                               ;
; ONE_INPUT_IS_CONSTANT  ; NO           ; Untyped                                               ;
; LPM_PIPELINE           ; 0            ; Untyped                                               ;
; MAXIMIZE_SPEED         ; 5            ; Untyped                                               ;
; REGISTERED_AT_END      ; 0            ; Untyped                                               ;
; OPTIMIZE_FOR_SPEED     ; 5            ; Untyped                                               ;
; USE_CS_BUFFERS         ; 1            ; Untyped                                               ;
; CARRY_CHAIN            ; MANUAL       ; Untyped                                               ;
; CARRY_CHAIN_LENGTH     ; 48           ; CARRY_CHAIN_LENGTH                                    ;
; DEVICE_FAMILY          ; Cyclone IV E ; Untyped                                               ;
; USE_WYS                ; OFF          ; Untyped                                               ;
; STYLE                  ; FAST         ; Untyped                                               ;
; CBXI_PARAMETER         ; add_sub_qvi  ; Untyped                                               ;
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                            ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                          ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                          ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                        ;
+------------------------+--------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                      ;
+-------------------------------+-----------------------------------+
; Name                          ; Value                             ;
+-------------------------------+-----------------------------------+
; Number of entity instances    ; 1                                 ;
; Entity Instance               ; PLL:inst1|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                            ;
;     -- PLL_TYPE               ; AUTO                              ;
;     -- PRIMARY_CLOCK          ; INCLK0                            ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                             ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                 ;
;     -- VCO_MULTIPLY_BY        ; 0                                 ;
;     -- VCO_DIVIDE_BY          ; 0                                 ;
+-------------------------------+-----------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                                                                                                                                                                      ;
+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                                      ; Value                                                                                                                                                                                                     ;
+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances                ; 8                                                                                                                                                                                                         ;
; Entity Instance                           ; CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram                                                                                                                       ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                 ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_A                         ; 512                                                                                                                                                                                                       ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_B                         ; 512                                                                                                                                                                                                       ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                 ;
; Entity Instance                           ; CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram                                                                                                                         ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                 ;
;     -- WIDTH_A                            ; 24                                                                                                                                                                                                        ;
;     -- NUMWORDS_A                         ; 64                                                                                                                                                                                                        ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- WIDTH_B                            ; 24                                                                                                                                                                                                        ;
;     -- NUMWORDS_B                         ; 64                                                                                                                                                                                                        ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                  ;
; Entity Instance                           ; CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram                                                                                                                               ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                 ;
;     -- WIDTH_A                            ; 2                                                                                                                                                                                                         ;
;     -- NUMWORDS_A                         ; 256                                                                                                                                                                                                       ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- WIDTH_B                            ; 2                                                                                                                                                                                                         ;
;     -- NUMWORDS_B                         ; 256                                                                                                                                                                                                       ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                  ;
; Entity Instance                           ; CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram                                                                                                       ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                 ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_A                         ; 32                                                                                                                                                                                                        ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_B                         ; 32                                                                                                                                                                                                        ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                  ;
; Entity Instance                           ; CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram                                                                                                       ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                 ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_A                         ; 32                                                                                                                                                                                                        ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_B                         ; 32                                                                                                                                                                                                        ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                  ;
; Entity Instance                           ; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram     ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                           ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_A                         ; 256                                                                                                                                                                                                       ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_B                         ; 256                                                                                                                                                                                                       ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                  ;
; Entity Instance                           ; CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                           ;
;     -- WIDTH_A                            ; 36                                                                                                                                                                                                        ;
;     -- NUMWORDS_A                         ; 128                                                                                                                                                                                                       ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- WIDTH_B                            ; 36                                                                                                                                                                                                        ;
;     -- NUMWORDS_B                         ; 128                                                                                                                                                                                                       ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                  ;
; Entity Instance                           ; CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom                                                                                                                                               ;
;     -- OPERATION_MODE                     ; ROM                                                                                                                                                                                                       ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                        ;
;     -- NUMWORDS_A                         ; 256                                                                                                                                                                                                       ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- WIDTH_B                            ; 1                                                                                                                                                                                                         ;
;     -- NUMWORDS_B                         ; 1                                                                                                                                                                                                         ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                 ;
+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; altmult_add Parameter Settings by Entity Instance                                                                                     ;
+---------------------------------------+-----------------------------------------------------------------------------------------------+
; Name                                  ; Value                                                                                         ;
+---------------------------------------+-----------------------------------------------------------------------------------------------+
; Number of entity instances            ; 2                                                                                             ;
; Entity Instance                       ; CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                           ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                             ;
;     -- port_signa                     ; PORT_UNUSED                                                                                   ;
;     -- port_signb                     ; PORT_UNUSED                                                                                   ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                                      ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                                      ;
;     -- WIDTH_A                        ; 16                                                                                            ;
;     -- WIDTH_B                        ; 16                                                                                            ;
;     -- WIDTH_RESULT                   ; 32                                                                                            ;
; Entity Instance                       ; CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                           ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                             ;
;     -- port_signa                     ; PORT_UNUSED                                                                                   ;
;     -- port_signb                     ; PORT_UNUSED                                                                                   ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                                      ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                                      ;
;     -- WIDTH_A                        ; 16                                                                                            ;
;     -- WIDTH_B                        ; 16                                                                                            ;
;     -- WIDTH_RESULT                   ; 16                                                                                            ;
+---------------------------------------+-----------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                               ;
+----------------------------+-----------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                         ;
+----------------------------+-----------------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                             ;
; Entity Instance            ; CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo ;
;     -- FIFO Type           ; Single Clock                                                                                  ;
;     -- lpm_width           ; 8                                                                                             ;
;     -- LPM_NUMWORDS        ; 64                                                                                            ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                           ;
;     -- USE_EAB             ; ON                                                                                            ;
; Entity Instance            ; CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo ;
;     -- FIFO Type           ; Single Clock                                                                                  ;
;     -- lpm_width           ; 8                                                                                             ;
;     -- LPM_NUMWORDS        ; 64                                                                                            ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                           ;
;     -- USE_EAB             ; ON                                                                                            ;
+----------------------------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch" ;
+---------+-------+----------+----------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                ;
+---------+-------+----------+----------------------------------------------------------------------------------------+
; data_in ; Input ; Info     ; Stuck at VCC                                                                           ;
+---------+-------+----------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|sysid:the_sysid" ;
+-------+-------+----------+---------------------------------+
; Port  ; Type  ; Severity ; Details                         ;
+-------+-------+----------+---------------------------------+
; clock ; Input ; Info     ; Stuck at GND                    ;
+-------+-------+----------+---------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port"                                            ;
+--------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                             ; Type   ; Severity ; Details                                                                             ;
+--------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; spi_touch_spi_control_port_dataavailable_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; spi_touch_spi_control_port_endofpacket_from_sa   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; spi_touch_spi_control_port_readyfordata_from_sa  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module"       ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                             ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; almost_empty ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; almost_full  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1" ;
+------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                                                                                           ;
+------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; clear_fifo ; Input  ; Info     ; Stuck at GND                                                                                                                                      ;
; empty      ; Output ; Info     ; Explicitly unconnected                                                                                                                            ;
; full       ; Output ; Info     ; Explicitly unconnected                                                                                                                            ;
; sync_reset ; Input  ; Info     ; Stuck at GND                                                                                                                                      ;
+------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1" ;
+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                                                                             ;
+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------+
; clear_fifo ; Input  ; Info     ; Stuck at GND                                                                                                                        ;
; empty      ; Output ; Info     ; Explicitly unconnected                                                                                                              ;
; full       ; Output ; Info     ; Explicitly unconnected                                                                                                              ;
; sync_reset ; Input  ; Info     ; Stuck at GND                                                                                                                        ;
+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"                                                                  ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                                                                                                                      ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; raw_tck        ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tck            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tdi            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; rti            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; shift          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; update         ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; usr1           ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; clr            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; ena            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; ir_in          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; tdo            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; irq            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; ir_out         ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; jtag_state_cdr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; jtag_state_sdr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; jtag_state_udr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave"                                           ;
+---------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                              ; Type   ; Severity ; Details                                                                             ;
+---------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; jtag_uart_avalon_jtag_slave_dataavailable_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; jtag_uart_avalon_jtag_slave_readyfordata_from_sa  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port"                                                ;
+----------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                                         ; Type   ; Severity ; Details                                                                             ;
+----------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; epcs_epcs_control_port_dataavailable_from_sa ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; epcs_epcs_control_port_endofpacket_from_sa   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; epcs_epcs_control_port_readyfordata_from_sa  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------------------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:16     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
    Info: Processing started: Mon Feb 25 15:07:43 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LED_hello_world -c LED_hello_world
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file /program/ep4ce10/verilog/led/led_4.v
    Info: Found entity 1: LED_4
Info: Found 1 design units, including 1 entities, in source file led_hello_world.bdf
    Info: Found entity 1: LED_hello_world
Info: Elaborating entity "LED_hello_world" for the top level hierarchy
Warning: Using design file pll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: PLL
Info: Elaborating entity "PLL" for hierarchy "PLL:inst1"
Info: Elaborating entity "altpll" for hierarchy "PLL:inst1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "PLL:inst1|altpll:altpll_component"
Info: Instantiated megafunction "PLL:inst1|altpll:altpll_component" with the following parameter:
    Info: Parameter "bandwidth_type" = "AUTO"
    Info: Parameter "clk0_divide_by" = "1"
    Info: Parameter "clk0_duty_cycle" = "50"
    Info: Parameter "clk0_multiply_by" = "1"
    Info: Parameter "clk0_phase_shift" = "0"
    Info: Parameter "clk1_divide_by" = "1"
    Info: Parameter "clk1_duty_cycle" = "50"
    Info: Parameter "clk1_multiply_by" = "1"
    Info: Parameter "clk1_phase_shift" = "-5556"
    Info: Parameter "compensate_clock" = "CLK0"
    Info: Parameter "inclk0_input_frequency" = "20000"
    Info: Parameter "intended_device_family" = "Cyclone IV E"
    Info: Parameter "lpm_hint" = "CBX_MODULE_PREFIX=PLL"
    Info: Parameter "lpm_type" = "altpll"
    Info: Parameter "operation_mode" = "NORMAL"
    Info: Parameter "pll_type" = "AUTO"
    Info: Parameter "port_activeclock" = "PORT_UNUSED"
    Info: Parameter "port_areset" = "PORT_UNUSED"
    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
    Info: Parameter "port_clkloss" = "PORT_UNUSED"
    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
    Info: Parameter "port_configupdate" = "PORT_UNUSED"
    Info: Parameter "port_fbin" = "PORT_UNUSED"
    Info: Parameter "port_inclk0" = "PORT_USED"
    Info: Parameter "port_inclk1" = "PORT_UNUSED"
    Info: Parameter "port_locked" = "PORT_UNUSED"
    Info: Parameter "port_pfdena" = "PORT_UNUSED"
    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info: Parameter "port_phasedone" = "PORT_UNUSED"
    Info: Parameter "port_phasestep" = "PORT_UNUSED"
    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info: Parameter "port_pllena" = "PORT_UNUSED"
    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
    Info: Parameter "port_scanclk" = "PORT_UNUSED"
    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
    Info: Parameter "port_scandata" = "PORT_UNUSED"
    Info: Parameter "port_scandataout" = "PORT_UNUSED"
    Info: Parameter "port_scandone" = "PORT_UNUSED"
    Info: Parameter "port_scanread" = "PORT_UNUSED"
    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
    Info: Parameter "port_clk0" = "PORT_USED"
    Info: Parameter "port_clk1" = "PORT_USED"
    Info: Parameter "port_clk2" = "PORT_UNUSED"
    Info: Parameter "port_clk3" = "PORT_UNUSED"
    Info: Parameter "port_clk4" = "PORT_UNUSED"
    Info: Parameter "port_clk5" = "PORT_UNUSED"
    Info: Parameter "port_clkena0" = "PORT_UNUSED"
    Info: Parameter "port_clkena1" = "PORT_UNUSED"
    Info: Parameter "port_clkena2" = "PORT_UNUSED"
    Info: Parameter "port_clkena3" = "PORT_UNUSED"
    Info: Parameter "port_clkena4" = "PORT_UNUSED"
    Info: Parameter "port_clkena5" = "PORT_UNUSED"
    Info: Parameter "port_extclk0" = "PORT_UNUSED"
    Info: Parameter "port_extclk1" = "PORT_UNUSED"
    Info: Parameter "port_extclk2" = "PORT_UNUSED"
    Info: Parameter "port_extclk3" = "PORT_UNUSED"
    Info: Parameter "width_clock" = "5"
Info: Found 1 design units, including 1 entities, in source file db/pll_altpll.v
    Info: Found entity 1: PLL_altpll
Info: Elaborating entity "PLL_altpll" for hierarchy "PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated"
Warning: Using design file core_sopc.v, which is not specified as a design file for the current project, but contains definitions for 22 design units and 22 entities in project
    Info: Found entity 1: bl_n_s1_arbitrator
    Info: Found entity 2: bl_p_s1_arbitrator
    Info: Found entity 3: cpu_jtag_debug_module_arbitrator
    Info: Found entity 4: cpu_data_master_arbitrator
    Info: Found entity 5: cpu_instruction_master_arbitrator
    Info: Found entity 6: epcs_epcs_control_port_arbitrator
    Info: Found entity 7: jtag_uart_avalon_jtag_slave_arbitrator
    Info: Found entity 8: lcd32_data_s1_arbitrator
    Info: Found entity 9: lcd_cs_s1_arbitrator
    Info: Found entity 10: lcd_rd_s1_arbitrator
    Info: Found entity 11: lcd_rs_s1_arbitrator
    Info: Found entity 12: lcd_wr_s1_arbitrator
    Info: Found entity 13: reset_s1_arbitrator
    Info: Found entity 14: rdv_fifo_for_cpu_data_master_to_sdram_s1_module
    Info: Found entity 15: rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module
    Info: Found entity 16: sdram_s1_arbitrator
    Info: Found entity 17: spi_touch_spi_control_port_arbitrator
    Info: Found entity 18: sysid_control_slave_arbitrator
    Info: Found entity 19: touch_cs_s1_arbitrator
    Info: Found entity 20: touch_irq_s1_arbitrator
    Info: Found entity 21: CORE_SOPC_reset_clk_domain_synch_module
    Info: Found entity 22: CORE_SOPC
Info: Elaborating entity "CORE_SOPC" for hierarchy "CORE_SOPC:inst"
Info: Elaborating entity "bl_n_s1_arbitrator" for hierarchy "CORE_SOPC:inst|bl_n_s1_arbitrator:the_bl_n_s1"
Warning: Using design file bl_n.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: bl_n
Info: Elaborating entity "bl_n" for hierarchy "CORE_SOPC:inst|bl_n:the_bl_n"
Info: Elaborating entity "bl_p_s1_arbitrator" for hierarchy "CORE_SOPC:inst|bl_p_s1_arbitrator:the_bl_p_s1"
Warning: Using design file bl_p.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: bl_p
Info: Elaborating entity "bl_p" for hierarchy "CORE_SOPC:inst|bl_p:the_bl_p"
Info: Elaborating entity "cpu_jtag_debug_module_arbitrator" for hierarchy "CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module"
Info: Elaborating entity "cpu_data_master_arbitrator" for hierarchy "CORE_SOPC:inst|cpu_data_master_arbitrator:the_cpu_data_master"
Info: Elaborating entity "cpu_instruction_master_arbitrator" for hierarchy "CORE_SOPC:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master"
Info: Found 25 design units, including 25 entities, in source file cpu.v
    Info: Found entity 1: cpu_ic_data_module
    Info: Found entity 2: cpu_ic_tag_module
    Info: Found entity 3: cpu_bht_module
    Info: Found entity 4: cpu_register_bank_a_module
    Info: Found entity 5: cpu_register_bank_b_module
    Info: Found entity 6: cpu_nios2_oci_debug
    Info: Found entity 7: cpu_ociram_lpm_dram_bdp_component_module
    Info: Found entity 8: cpu_nios2_ocimem
    Info: Found entity 9: cpu_nios2_avalon_reg
    Info: Found entity 10: cpu_nios2_oci_break
    Info: Found entity 11: cpu_nios2_oci_xbrk
    Info: Found entity 12: cpu_nios2_oci_dbrk
    Info: Found entity 13: cpu_nios2_oci_itrace
    Info: Found entity 14: cpu_nios2_oci_td_mode
    Info: Found entity 15: cpu_nios2_oci_dtrace
    Info: Found entity 16: cpu_nios2_oci_compute_tm_count
    Info: Found entity 17: cpu_nios2_oci_fifowp_inc
    Info: Found entity 18: cpu_nios2_oci_fifocount_inc
    Info: Found entity 19: cpu_nios2_oci_fifo
    Info: Found entity 20: cpu_nios2_oci_pib
    Info: Found entity 21: cpu_traceram_lpm_dram_bdp_component_module
    Info: Found entity 22: cpu_nios2_oci_im
    Info: Found entity 23: cpu_nios2_performance_monitors
    Info: Found entity 24: cpu_nios2_oci
    Info: Found entity 25: cpu
Info: Elaborating entity "cpu" for hierarchy "CORE_SOPC:inst|cpu:the_cpu"
Warning: Using design file cpu_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_test_bench
Info: Elaborating entity "cpu_test_bench" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench"
Info: Elaborating entity "cpu_ic_data_module" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data"
Info: Elaborating entity "altsyncram" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "512"
    Info: Parameter "numwords_b" = "512"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "widthad_a" = "9"
    Info: Parameter "widthad_b" = "9"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_udd1.tdf
    Info: Found entity 1: altsyncram_udd1
Info: Elaborating entity "altsyncram_udd1" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_udd1:auto_generated"
Info: Elaborating entity "cpu_ic_tag_module" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag"
Info: Elaborating entity "altsyncram" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_ic_tag_ram.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "64"
    Info: Parameter "numwords_b" = "64"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "24"
    Info: Parameter "width_b" = "24"
    Info: Parameter "widthad_a" = "6"
    Info: Parameter "widthad_b" = "6"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_i2g1.tdf
    Info: Found entity 1: altsyncram_i2g1
Info: Elaborating entity "altsyncram_i2g1" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_i2g1:auto_generated"
Info: Elaborating entity "cpu_bht_module" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht"
Info: Elaborating entity "altsyncram" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_bht_ram.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "256"
    Info: Parameter "numwords_b" = "256"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "2"
    Info: Parameter "width_b" = "2"
    Info: Parameter "widthad_a" = "8"
    Info: Parameter "widthad_b" = "8"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bpf1.tdf
    Info: Found entity 1: altsyncram_bpf1
Info: Elaborating entity "altsyncram_bpf1" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_bpf1:auto_generated"
Info: Elaborating entity "cpu_register_bank_a_module" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a"
Info: Elaborating entity "altsyncram" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_rf_ram_a.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "32"
    Info: Parameter "numwords_b" = "32"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "widthad_a" = "5"
    Info: Parameter "widthad_b" = "5"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_b7f1.tdf
    Info: Found entity 1: altsyncram_b7f1
Info: Elaborating entity "altsyncram_b7f1" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b7f1:auto_generated"
Info: Elaborating entity "cpu_register_bank_b_module" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b"
Info: Elaborating entity "altsyncram" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_reg_b" = "CLOCK0"
    Info: Parameter "init_file" = "cpu_rf_ram_b.mif"
    Info: Parameter "maximum_depth" = "0"
    Info: Parameter "numwords_a" = "32"
    Info: Parameter "numwords_b" = "32"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "widthad_a" = "5"
    Info: Parameter "widthad_b" = "5"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_c7f1.tdf
    Info: Found entity 1: altsyncram_c7f1
Info: Elaborating entity "altsyncram_c7f1" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c7f1:auto_generated"
Warning: Using design file cpu_mult_cell.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_mult_cell
Info: Elaborating entity "cpu_mult_cell" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell"
Info: Elaborating entity "altmult_add" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1" with the following parameter:
    Info: Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0"
    Info: Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0"
    Info: Parameter "addnsub_multiplier_register1" = "UNREGISTERED"
    Info: Parameter "dedicated_multiplier_circuitry" = "YES"
    Info: Parameter "input_register_a0" = "UNREGISTERED"
    Info: Parameter "input_register_b0" = "UNREGISTERED"
    Info: Parameter "input_source_a0" = "DATAA"
    Info: Parameter "input_source_b0" = "DATAB"
    Info: Parameter "intended_device_family" = "CYCLONEIVE"
    Info: Parameter "lpm_type" = "altmult_add"
    Info: Parameter "multiplier1_direction" = "ADD"
    Info: Parameter "multiplier_aclr0" = "ACLR0"
    Info: Parameter "multiplier_register0" = "CLOCK0"
    Info: Parameter "number_of_multipliers" = "1"
    Info: Parameter "output_register" = "UNREGISTERED"
    Info: Parameter "port_addnsub1" = "PORT_UNUSED"
    Info: Parameter "port_signa" = "PORT_UNUSED"
    Info: Parameter "port_signb" = "PORT_UNUSED"
    Info: Parameter "representation_a" = "UNSIGNED"
    Info: Parameter "representation_b" = "UNSIGNED"
    Info: Parameter "signed_pipeline_aclr_a" = "ACLR0"
    Info: Parameter "signed_pipeline_aclr_b" = "ACLR0"
    Info: Parameter "signed_pipeline_register_a" = "CLOCK0"
    Info: Parameter "signed_pipeline_register_b" = "CLOCK0"
    Info: Parameter "signed_register_a" = "UNREGISTERED"
    Info: Parameter "signed_register_b" = "UNREGISTERED"
    Info: Parameter "width_a" = "16"
    Info: Parameter "width_b" = "16"
    Info: Parameter "width_result" = "32"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_mgr2.tdf
    Info: Found entity 1: mult_add_mgr2
Info: Elaborating entity "mult_add_mgr2" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf
    Info: Found entity 1: ded_mult_ks81
Info: Elaborating entity "ded_mult_ks81" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf
    Info: Found entity 1: dffpipe_93c
Info: Elaborating entity "dffpipe_93c" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result"
Info: Elaborating entity "altmult_add" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2" with the following parameter:
    Info: Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0"
    Info: Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0"
    Info: Parameter "addnsub_multiplier_register1" = "UNREGISTERED"
    Info: Parameter "dedicated_multiplier_circuitry" = "YES"
    Info: Parameter "input_register_a0" = "UNREGISTERED"
    Info: Parameter "input_register_b0" = "UNREGISTERED"
    Info: Parameter "input_source_a0" = "DATAA"
    Info: Parameter "input_source_b0" = "DATAB"
    Info: Parameter "intended_device_family" = "CYCLONEIVE"
    Info: Parameter "lpm_type" = "altmult_add"
    Info: Parameter "multiplier1_direction" = "ADD"
    Info: Parameter "multiplier_aclr0" = "ACLR0"
    Info: Parameter "multiplier_register0" = "CLOCK0"
    Info: Parameter "number_of_multipliers" = "1"
    Info: Parameter "output_register" = "UNREGISTERED"
    Info: Parameter "port_addnsub1" = "PORT_UNUSED"
    Info: Parameter "port_signa" = "PORT_UNUSED"
    Info: Parameter "port_signb" = "PORT_UNUSED"
    Info: Parameter "representation_a" = "UNSIGNED"
    Info: Parameter "representation_b" = "UNSIGNED"
    Info: Parameter "signed_pipeline_aclr_a" = "ACLR0"
    Info: Parameter "signed_pipeline_aclr_b" = "ACLR0"
    Info: Parameter "signed_pipeline_register_a" = "CLOCK0"
    Info: Parameter "signed_pipeline_register_b" = "CLOCK0"
    Info: Parameter "signed_register_a" = "UNREGISTERED"
    Info: Parameter "signed_register_b" = "UNREGISTERED"
    Info: Parameter "width_a" = "16"
    Info: Parameter "width_b" = "16"
    Info: Parameter "width_result" = "16"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_ogr2.tdf
    Info: Found entity 1: mult_add_ogr2
Info: Elaborating entity "mult_add_ogr2" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated"
Info: Elaborating entity "cpu_nios2_oci" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci"
Info: Elaborating entity "cpu_nios2_oci_debug" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug"
Info: Elaborating entity "cpu_nios2_ocimem" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem"
Info: Elaborating entity "cpu_ociram_lpm_dram_bdp_component_module" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_aclr_a" = "NONE"
    Info: Parameter "address_aclr_b" = "NONE"
    Info: Parameter "address_reg_b" = "CLOCK1"
    Info: Parameter "indata_aclr_a" = "NONE"
    Info: Parameter "indata_aclr_b" = "NONE"
    Info: Parameter "init_file" = "cpu_ociram_default_contents.mif"
    Info: Parameter "intended_device_family" = "CYCLONEIVE"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "256"
    Info: Parameter "numwords_b" = "256"
    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    Info: Parameter "outdata_aclr_a" = "NONE"
    Info: Parameter "outdata_aclr_b" = "NONE"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "32"
    Info: Parameter "width_b" = "32"
    Info: Parameter "width_byteena_a" = "4"
    Info: Parameter "widthad_a" = "8"
    Info: Parameter "widthad_b" = "8"
    Info: Parameter "wrcontrol_aclr_a" = "NONE"
    Info: Parameter "wrcontrol_aclr_b" = "NONE"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f572.tdf
    Info: Found entity 1: altsyncram_f572
Info: Elaborating entity "altsyncram_f572" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_f572:auto_generated"
Info: Elaborating entity "cpu_nios2_avalon_reg" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg"
Info: Elaborating entity "cpu_nios2_oci_break" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break"
Info: Elaborating entity "cpu_nios2_oci_xbrk" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk"
Info: Elaborating entity "cpu_nios2_oci_dbrk" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk"
Info: Elaborating entity "cpu_nios2_oci_itrace" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace"
Info: Elaborating entity "cpu_nios2_oci_dtrace" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace"
Info: Elaborating entity "cpu_nios2_oci_td_mode" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode"
Info: Elaborating entity "cpu_nios2_oci_fifo" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo"
Info: Elaborating entity "cpu_nios2_oci_compute_tm_count" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count"
Info: Elaborating entity "cpu_nios2_oci_fifowp_inc" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp"
Info: Elaborating entity "cpu_nios2_oci_fifocount_inc" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount"
Warning: Using design file cpu_oci_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_oci_test_bench
Info: Elaborating entity "cpu_oci_test_bench" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_oci_test_bench:the_cpu_oci_test_bench"
Info: Elaborating entity "cpu_nios2_oci_pib" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib"
Info: Elaborating entity "cpu_nios2_oci_im" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im"
Info: Elaborating entity "cpu_traceram_lpm_dram_bdp_component_module" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" with the following parameter:
    Info: Parameter "address_aclr_a" = "NONE"
    Info: Parameter "address_aclr_b" = "NONE"
    Info: Parameter "address_reg_b" = "CLOCK1"
    Info: Parameter "indata_aclr_a" = "NONE"
    Info: Parameter "indata_aclr_b" = "NONE"
    Info: Parameter "init_file" = "UNUSED"
    Info: Parameter "intended_device_family" = "CYCLONEIVE"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "128"
    Info: Parameter "numwords_b" = "128"
    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    Info: Parameter "outdata_aclr_a" = "NONE"
    Info: Parameter "outdata_aclr_b" = "NONE"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "outdata_reg_b" = "UNREGISTERED"
    Info: Parameter "ram_block_type" = "AUTO"
    Info: Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA"
    Info: Parameter "width_a" = "36"
    Info: Parameter "width_b" = "36"
    Info: Parameter "widthad_a" = "7"
    Info: Parameter "widthad_b" = "7"
    Info: Parameter "wrcontrol_aclr_a" = "NONE"
    Info: Parameter "wrcontrol_aclr_b" = "NONE"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf
    Info: Found entity 1: altsyncram_0a02
Info: Elaborating entity "altsyncram_0a02" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated"
Warning: Using design file cpu_jtag_debug_module_wrapper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_jtag_debug_module_wrapper
Info: Elaborating entity "cpu_jtag_debug_module_wrapper" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper"
Warning: Using design file cpu_jtag_debug_module_tck.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_jtag_debug_module_tck
Info: Elaborating entity "cpu_jtag_debug_module_tck" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck"
Info: Elaborating entity "altera_std_synchronizer" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter:
    Info: Parameter "depth" = "2"
Warning: Using design file cpu_jtag_debug_module_sysclk.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_jtag_debug_module_sysclk
Info: Elaborating entity "cpu_jtag_debug_module_sysclk" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk"
Info: Elaborating entity "sld_virtual_jtag_basic" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy" with the following parameter:
    Info: Parameter "sld_auto_instance_index" = "YES"
    Info: Parameter "sld_instance_index" = "0"
    Info: Parameter "sld_ir_width" = "2"
    Info: Parameter "sld_mfg_id" = "70"
    Info: Parameter "sld_sim_action" = ""
    Info: Parameter "sld_sim_n_scan" = "0"
    Info: Parameter "sld_sim_total_length" = "0"
    Info: Parameter "sld_type_id" = "34"
    Info: Parameter "sld_version" = "3"
Info: Elaborating entity "sld_virtual_jtag_impl" for hierarchy "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy"
Info: Elaborating entity "epcs_epcs_control_port_arbitrator" for hierarchy "CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port"
Warning: Using design file epcs.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: epcs_sub
    Info: Found entity 2: epcs
Info: Elaborating entity "epcs" for hierarchy "CORE_SOPC:inst|epcs:the_epcs"
Info: Elaborating entity "epcs_sub" for hierarchy "CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub"
Info: Elaborating entity "altsyncram" for hierarchy "CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom"
Info: Instantiated megafunction "CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom" with the following parameter:
    Info: Parameter "byte_size" = "8"
    Info: Parameter "init_file" = "epcs_boot_rom_synth.hex"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "256"
    Info: Parameter "operation_mode" = "ROM"
    Info: Parameter "outdata_reg_a" = "UNREGISTERED"
    Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info: Parameter "width_a" = "32"
    Info: Parameter "widthad_a" = "8"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sc31.tdf
    Info: Found entity 1: altsyncram_sc31
Info: Elaborating entity "altsyncram_sc31" for hierarchy "CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom|altsyncram_sc31:auto_generated"
Info: Elaborating entity "jtag_uart_avalon_jtag_slave_arbitrator" for hierarchy "CORE_SOPC:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave"
Warning: Using design file jtag_uart.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project
    Info: Found entity 1: jtag_uart_log_module
    Info: Found entity 2: jtag_uart_sim_scfifo_w
    Info: Found entity 3: jtag_uart_scfifo_w
    Info: Found entity 4: jtag_uart_drom_module
    Info: Found entity 5: jtag_uart_sim_scfifo_r
    Info: Found entity 6: jtag_uart_scfifo_r
    Info: Found entity 7: jtag_uart
Info: Elaborating entity "jtag_uart" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart"
Info: Elaborating entity "jtag_uart_scfifo_w" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w"
Info: Elaborating entity "scfifo" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo"
Info: Instantiated megafunction "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo" with the following parameter:
    Info: Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO"
    Info: Parameter "lpm_numwords" = "64"
    Info: Parameter "lpm_showahead" = "OFF"
    Info: Parameter "lpm_type" = "scfifo"
    Info: Parameter "lpm_width" = "8"
    Info: Parameter "lpm_widthu" = "6"
    Info: Parameter "overflow_checking" = "OFF"
    Info: Parameter "underflow_checking" = "OFF"
    Info: Parameter "use_eab" = "ON"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf
    Info: Found entity 1: scfifo_jr21
Info: Elaborating entity "scfifo_jr21" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf
    Info: Found entity 1: a_dpfifo_q131
Info: Elaborating entity "a_dpfifo_q131" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf
    Info: Found entity 1: a_fefifo_7cf
Info: Elaborating entity "a_fefifo_7cf" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf
    Info: Found entity 1: cntr_do7
Info: Elaborating entity "cntr_do7" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf
    Info: Found entity 1: dpram_nl21
Info: Elaborating entity "dpram_nl21" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf
    Info: Found entity 1: altsyncram_r1m1
Info: Elaborating entity "altsyncram_r1m1" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1"
Info: Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf
    Info: Found entity 1: cntr_1ob
Info: Elaborating entity "cntr_1ob" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count"
Info: Elaborating entity "jtag_uart_scfifo_r" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r"
Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic"
Info: Instantiated megafunction "CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic" with the following parameter:
    Info: Parameter "INSTANCE_ID" = "0"
    Info: Parameter "LOG2_RXFIFO_DEPTH" = "6"
    Info: Parameter "LOG2_TXFIFO_DEPTH" = "6"
    Info: Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES"
Info: Elaborating entity "lcd32_data_s1_arbitrator" for hierarchy "CORE_SOPC:inst|lcd32_data_s1_arbitrator:the_lcd32_data_s1"
Warning: Using design file lcd32_data.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lcd32_data
Info: Elaborating entity "lcd32_data" for hierarchy "CORE_SOPC:inst|lcd32_data:the_lcd32_data"
Info: Elaborating entity "lcd_cs_s1_arbitrator" for hierarchy "CORE_SOPC:inst|lcd_cs_s1_arbitrator:the_lcd_cs_s1"
Warning: Using design file lcd_cs.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lcd_cs
Info: Elaborating entity "lcd_cs" for hierarchy "CORE_SOPC:inst|lcd_cs:the_lcd_cs"
Info: Elaborating entity "lcd_rd_s1_arbitrator" for hierarchy "CORE_SOPC:inst|lcd_rd_s1_arbitrator:the_lcd_rd_s1"
Warning: Using design file lcd_rd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lcd_rd
Info: Elaborating entity "lcd_rd" for hierarchy "CORE_SOPC:inst|lcd_rd:the_lcd_rd"
Info: Elaborating entity "lcd_rs_s1_arbitrator" for hierarchy "CORE_SOPC:inst|lcd_rs_s1_arbitrator:the_lcd_rs_s1"
Warning: Using design file lcd_rs.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lcd_rs
Info: Elaborating entity "lcd_rs" for hierarchy "CORE_SOPC:inst|lcd_rs:the_lcd_rs"
Info: Elaborating entity "lcd_wr_s1_arbitrator" for hierarchy "CORE_SOPC:inst|lcd_wr_s1_arbitrator:the_lcd_wr_s1"
Warning: Using design file lcd_wr.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lcd_wr
Info: Elaborating entity "lcd_wr" for hierarchy "CORE_SOPC:inst|lcd_wr:the_lcd_wr"
Info: Elaborating entity "reset_s1_arbitrator" for hierarchy "CORE_SOPC:inst|reset_s1_arbitrator:the_reset_s1"
Warning: Using design file reset.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: reset
Info: Elaborating entity "reset" for hierarchy "CORE_SOPC:inst|reset:the_reset"
Info: Elaborating entity "sdram_s1_arbitrator" for hierarchy "CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1"
Info: Elaborating entity "rdv_fifo_for_cpu_data_master_to_sdram_s1_module" for hierarchy "CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1"
Info: Elaborating entity "rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module" for hierarchy "CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1"
Warning: Using design file sdram.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: sdram_input_efifo_module
    Info: Found entity 2: sdram
Info: Elaborating entity "sdram" for hierarchy "CORE_SOPC:inst|sdram:the_sdram"
Info: Elaborating entity "sdram_input_efifo_module" for hierarchy "CORE_SOPC:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module"
Info: Elaborating entity "spi_touch_spi_control_port_arbitrator" for hierarchy "CORE_SOPC:inst|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port"
Warning: Using design file spi_touch.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: spi_touch
Info: Elaborating entity "spi_touch" for hierarchy "CORE_SOPC:inst|spi_touch:the_spi_touch"
Info: Elaborating entity "sysid_control_slave_arbitrator" for hierarchy "CORE_SOPC:inst|sysid_control_slave_arbitrator:the_sysid_control_slave"
Warning: Using design file sysid.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sysid
Info: Elaborating entity "sysid" for hierarchy "CORE_SOPC:inst|sysid:the_sysid"
Info: Elaborating entity "touch_cs_s1_arbitrator" for hierarchy "CORE_SOPC:inst|touch_cs_s1_arbitrator:the_touch_cs_s1"
Warning: Using design file touch_cs.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: touch_cs
Info: Elaborating entity "touch_cs" for hierarchy "CORE_SOPC:inst|touch_cs:the_touch_cs"
Info: Elaborating entity "touch_irq_s1_arbitrator" for hierarchy "CORE_SOPC:inst|touch_irq_s1_arbitrator:the_touch_irq_s1"
Warning: Using design file touch_irq.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: touch_irq
Info: Elaborating entity "touch_irq" for hierarchy "CORE_SOPC:inst|touch_irq:the_touch_irq"
Info: Elaborating entity "CORE_SOPC_reset_clk_domain_synch_module" for hierarchy "CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch"
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[0]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[1]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[2]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[3]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[4]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[5]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[6]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[7]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[8]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[9]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[10]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[11]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[12]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[13]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[14]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[15]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[16]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[17]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[18]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[19]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[20]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[21]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[22]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[23]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[24]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[25]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[26]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[27]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[28]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[29]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[30]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[31]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[32]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[33]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[34]"
        Warning (14320): Synthesized away node "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[35]"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "CORE_SOPC:inst|cpu:the_cpu|Add10"
Info: Elaborated megafunction instantiation "CORE_SOPC:inst|cpu:the_cpu|lpm_add_sub:Add10"
Info: Instantiated megafunction "CORE_SOPC:inst|cpu:the_cpu|lpm_add_sub:Add10" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "33"
    Info: Parameter "LPM_DIRECTION" = "DEFAULT"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf
    Info: Found entity 1: add_sub_qvi
Warning: 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "CKE" is stuck at VCC
Info: Timing-Driven Synthesis is running on partition "Top"
Info: 78 registers lost all their fanouts during netlist optimizations. The first 78 are displayed below.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[0]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[1]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[2]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[3]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[4]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[5]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[6]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[7]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[8]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[9]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[10]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[11]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[12]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[13]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[14]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[15]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[16]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[17]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[18]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[19]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[20]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[21]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[22]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[23]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[24]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[25]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[26]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[27]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[28]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[29]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[30]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[31]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[34]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[33]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[32]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace|itm[35]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[0]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[16]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[15]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[14]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[13]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[12]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[11]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[10]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[9]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[8]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[7]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[6]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[5]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[4]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[3]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[2]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|trc_jtag_addr[1]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_arb_share_counter[0]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_reg_firsttransfer" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port|epcs_epcs_control_port_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter[0]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_reg_firsttransfer" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|m_next~9" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|m_next~10" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|m_next~13" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|m_next~14" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|m_next~16" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|i_next~4" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|i_next~5" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|i_next~6" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|i_state~14" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|i_state~15" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|sdram:the_sdram|i_state~16" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize~3" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize~4" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize~5" lost all its fanouts during netlist optimizations.
    Info: Register "CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|DRsize.101" lost all its fanouts during netlist optimizations.
Info: Generated suppressed messages file E:/Program/EP4CE10/nios/LCD32/LED_hello_world.map.smsg
Info: Generating hard_block partition "hard_block:auto_generated_inst"
    Info: Adding node "PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated|pll1"
Info: Implemented 4421 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 38 output pins
    Info: Implemented 32 bidirectional pins
    Info: Implemented 4135 logic cells
    Info: Implemented 202 RAM segments
    Info: Implemented 1 PLLs
    Info: Implemented 4 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 64 warnings
    Info: Peak virtual memory: 310 megabytes
    Info: Processing ended: Mon Feb 25 15:08:05 2013
    Info: Elapsed time: 00:00:22
    Info: Total CPU time (on all processors): 00:00:22


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/Program/EP4CE10/nios/LCD32/LED_hello_world.map.smsg.


