Quartus II
Version 11.0 Build 157 04/27/2011 SJ Full Version
15
1153
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
LED_hello_world
# storage
db|LED_hello_world.(0).cnf
db|LED_hello_world.(0).cnf
# case_insensitive
# source_file
led_hello_world.bdf
4eac2aeb98a8601e36d5b4895e6c97c9
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
PLL
# storage
db|LED_hello_world.(1).cnf
db|LED_hello_world.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pll.v
7756ff4231afdf233a9dcabaa9cb1d
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
PLL:inst1
}
# macro_sequence

# end
# entity
altpll
# storage
db|LED_hello_world.(2).cnf
db|LED_hello_world.(2).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altpll.tdf
452f627ba8b04372419df6af11f0325f
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
LPM_HINT
CBX_MODULE_PREFIX=PLL
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
USR
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
-5556
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
PLL_altpll
PARAMETER_UNKNOWN
USR
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
5
PARAMETER_SIGNED_DEC
USR
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
configupdate
-1
1
clkswitch
-1
1
areset
-1
1
scanclkena
-1
2
pllena
-1
2
phaseupdown
-1
2
phasestep
-1
2
phasecounterselect
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# include_file {
altpll.tdf
452f627ba8b04372419df6af11f0325f
stratix_pll.inc
a9a94c5be18105f7ae8c218a67ec9f7
cycloneii_pll.inc
c2ee779f89b3bc181df753ea85b3ef
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
stratixii_pll.inc
6797ab505ed70f1a221e4a213e16a6
}
# macro_sequence

# end
# entity
PLL_altpll
# storage
db|LED_hello_world.(3).cnf
db|LED_hello_world.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
db|pll_altpll.v
1a42cb638f71438401e19595a7e7416
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated
}
# macro_sequence
ALTERA_RESERVED_QISALTERA_RESERVED_QIS
# end
# entity
CORE_SOPC
# storage
db|LED_hello_world.(4).cnf
db|LED_hello_world.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst
}
# macro_sequence

# end
# entity
bl_n_s1_arbitrator
# storage
db|LED_hello_world.(5).cnf
db|LED_hello_world.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|bl_n_s1_arbitrator:the_bl_n_s1
}
# macro_sequence

# end
# entity
bl_n
# storage
db|LED_hello_world.(6).cnf
db|LED_hello_world.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
bl_n.v
a7debca3ff7354f11e2af118437a16d
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|bl_n:the_bl_n
}
# macro_sequence

# end
# entity
bl_p_s1_arbitrator
# storage
db|LED_hello_world.(7).cnf
db|LED_hello_world.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|bl_p_s1_arbitrator:the_bl_p_s1
}
# macro_sequence

# end
# entity
bl_p
# storage
db|LED_hello_world.(8).cnf
db|LED_hello_world.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
bl_p.v
568df6c260e08bea3dfb5328b5b53a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|bl_p:the_bl_p
}
# macro_sequence

# end
# entity
cpu_jtag_debug_module_arbitrator
# storage
db|LED_hello_world.(9).cnf
db|LED_hello_world.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module
}
# macro_sequence

# end
# entity
cpu_data_master_arbitrator
# storage
db|LED_hello_world.(10).cnf
db|LED_hello_world.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu_data_master_arbitrator:the_cpu_data_master
}
# macro_sequence

# end
# entity
cpu_instruction_master_arbitrator
# storage
db|LED_hello_world.(11).cnf
db|LED_hello_world.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master
}
# macro_sequence

# end
# entity
cpu
# storage
db|LED_hello_world.(12).cnf
db|LED_hello_world.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu
}
# macro_sequence

# end
# entity
cpu_test_bench
# storage
db|LED_hello_world.(13).cnf
db|LED_hello_world.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_test_bench.v
f0378e6bc22d1ce47fdadee88f7b5c9
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench
}
# macro_sequence

# end
# entity
cpu_ic_data_module
# storage
db|LED_hello_world.(14).cnf
db|LED_hello_world.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(15).cnf
db|LED_hello_world.(15).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
512
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
512
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_udd1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
altrom.inc
192b74eafa8debf2248ea73881e77f91
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# macro_sequence

# end
# entity
altsyncram_udd1
# storage
db|LED_hello_world.(16).cnf
db|LED_hello_world.(16).cnf
# case_insensitive
# source_file
db|altsyncram_udd1.tdf
ca4e6cedc5f0db183e71b679dd2f5039
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_udd1:auto_generated
}
# macro_sequence

# end
# entity
cpu_ic_tag_module
# storage
db|LED_hello_world.(17).cnf
db|LED_hello_world.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_ic_tag_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(18).cnf
db|LED_hello_world.(18).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
24
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
64
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
24
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
64
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_ic_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_i2g1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
altrom.inc
192b74eafa8debf2248ea73881e77f91
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# macro_sequence

# end
# entity
altsyncram_i2g1
# storage
db|LED_hello_world.(19).cnf
db|LED_hello_world.(19).cnf
# case_insensitive
# source_file
db|altsyncram_i2g1.tdf
e512963a694fea97cbca3fef6ceb257f
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_ic_tag_ram.mif
3d49d78e15516478379622d23bc6f70
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_i2g1:auto_generated
}
# macro_sequence

# end
# entity
cpu_bht_module
# storage
db|LED_hello_world.(20).cnf
db|LED_hello_world.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_bht_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(21).cnf
db|LED_hello_world.(21).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
2
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
2
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_bht_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_bpf1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
altrom.inc
192b74eafa8debf2248ea73881e77f91
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# macro_sequence

# end
# entity
altsyncram_bpf1
# storage
db|LED_hello_world.(22).cnf
db|LED_hello_world.(22).cnf
# case_insensitive
# source_file
db|altsyncram_bpf1.tdf
6d96b9232818654c34358f2a6b793c
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b1
-1
3
q_b0
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_bht_ram.mif
e8b47733fe3ed86551be0239a29e3ae
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_bpf1:auto_generated
}
# macro_sequence

# end
# entity
cpu_register_bank_a_module
# storage
db|LED_hello_world.(23).cnf
db|LED_hello_world.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_rf_ram_a.mif
PARAMETER_STRING
USR
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(24).cnf
db|LED_hello_world.(24).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_rf_ram_a.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_b7f1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
altrom.inc
192b74eafa8debf2248ea73881e77f91
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# macro_sequence

# end
# entity
altsyncram_b7f1
# storage
db|LED_hello_world.(25).cnf
db|LED_hello_world.(25).cnf
# case_insensitive
# source_file
db|altsyncram_b7f1.tdf
a25b24a28067d0a85a9dbc101339c947
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_rf_ram_a.mif
37e6bb46f593b58f68ad218371e525
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b7f1:auto_generated
}
# macro_sequence

# end
# entity
cpu_register_bank_b_module
# storage
db|LED_hello_world.(26).cnf
db|LED_hello_world.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_rf_ram_b.mif
PARAMETER_STRING
USR
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(27).cnf
db|LED_hello_world.(27).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_rf_ram_b.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_c7f1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
altrom.inc
192b74eafa8debf2248ea73881e77f91
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# macro_sequence

# end
# entity
altsyncram_c7f1
# storage
db|LED_hello_world.(28).cnf
db|LED_hello_world.(28).cnf
# case_insensitive
# source_file
db|altsyncram_c7f1.tdf
7140902c788a604a7d64c0231dedc63
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_rf_ram_b.mif
37e6bb46f593b58f68ad218371e525
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c7f1:auto_generated
}
# macro_sequence

# end
# entity
cpu_mult_cell
# storage
db|LED_hello_world.(29).cnf
db|LED_hello_world.(29).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_mult_cell.v
52a14683fe5769402cef8063bafedd40
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell
}
# macro_sequence

# end
# entity
altmult_add
# storage
db|LED_hello_world.(30).cnf
db|LED_hello_world.(30).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altmult_add.tdf
61a6fe8a40fd8b58b1825bd77b5dfb
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
ACCUM_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUMULATOR
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER1
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ADDER
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR2
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
NUMBER_OF_MULTIPLIERS
1
PARAMETER_SIGNED_DEC
USR
OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_TYPE
NEAREST_INTEGER
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_TYPE
ASYMMETRIC
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
port_addnsub1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_addnsub3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CHAINOUT_SAT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_OUTPUT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
port_signa
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_signb
PORT_UNUSED
PARAMETER_UNKNOWN
USR
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
REPRESENTATION_B
UNSIGNED
PARAMETER_UNKNOWN
USR
ROTATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
WIDTH_MSB
17
PARAMETER_UNKNOWN
DEF
WIDTH_SATURATE_SIGN
1
PARAMETER_UNKNOWN
DEF
SCANOUTA_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SCANOUTA_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
DEF
SHIFT_MODE
NO
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTH_CHAININ
1
PARAMETER_UNKNOWN
DEF
WIDTH_RESULT
32
PARAMETER_SIGNED_DEC
USR
ZERO_CHAINOUT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_CHAINOUT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_add_mgr2
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
WIDTH_C
22
PARAMETER_UNKNOWN
DEF
LOADCONST_VALUE
64
PARAMETER_UNKNOWN
DEF
PREADDER_MODE
SIMPLE
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_0
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_1
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_2
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_3
ADD
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_C0
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_C0
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL0_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL1_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL2_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL3_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL0_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL1_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL2_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL3_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY1
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY3
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR1
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR3
ACLR0
PARAMETER_UNKNOWN
DEF
COEF0_0
0
PARAMETER_UNKNOWN
DEF
COEF0_1
0
PARAMETER_UNKNOWN
DEF
COEF0_2
0
PARAMETER_UNKNOWN
DEF
COEF0_3
0
PARAMETER_UNKNOWN
DEF
COEF0_4
0
PARAMETER_UNKNOWN
DEF
COEF0_5
0
PARAMETER_UNKNOWN
DEF
COEF0_6
0
PARAMETER_UNKNOWN
DEF
COEF0_7
0
PARAMETER_UNKNOWN
DEF
COEF1_0
0
PARAMETER_UNKNOWN
DEF
COEF1_1
0
PARAMETER_UNKNOWN
DEF
COEF1_2
0
PARAMETER_UNKNOWN
DEF
COEF1_3
0
PARAMETER_UNKNOWN
DEF
COEF1_4
0
PARAMETER_UNKNOWN
DEF
COEF1_5
0
PARAMETER_UNKNOWN
DEF
COEF1_6
0
PARAMETER_UNKNOWN
DEF
COEF1_7
0
PARAMETER_UNKNOWN
DEF
COEF2_0
0
PARAMETER_UNKNOWN
DEF
COEF2_1
0
PARAMETER_UNKNOWN
DEF
COEF2_2
0
PARAMETER_UNKNOWN
DEF
COEF2_3
0
PARAMETER_UNKNOWN
DEF
COEF2_4
0
PARAMETER_UNKNOWN
DEF
COEF2_5
0
PARAMETER_UNKNOWN
DEF
COEF2_6
0
PARAMETER_UNKNOWN
DEF
COEF2_7
0
PARAMETER_UNKNOWN
DEF
COEF3_0
0
PARAMETER_UNKNOWN
DEF
COEF3_1
0
PARAMETER_UNKNOWN
DEF
COEF3_2
0
PARAMETER_UNKNOWN
DEF
COEF3_3
0
PARAMETER_UNKNOWN
DEF
COEF3_4
0
PARAMETER_UNKNOWN
DEF
COEF3_5
0
PARAMETER_UNKNOWN
DEF
COEF3_6
0
PARAMETER_UNKNOWN
DEF
COEF3_7
0
PARAMETER_UNKNOWN
DEF
WIDTH_COEF
18
PARAMETER_UNKNOWN
DEF
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
ena0
-1
2
}
# include_file {
stratix_mac_out.inc
9ac89b9d6c98d3e379f29a56f74933
stratix_mac_mult.inc
39994655f1ee0a1246f2c1a60bc98e4
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altmult_add.tdf
61a6fe8a40fd8b58b1825bd77b5dfb
}
# macro_sequence

# end
# entity
mult_add_mgr2
# storage
db|LED_hello_world.(31).cnf
db|LED_hello_world.(31).cnf
# case_insensitive
# source_file
db|mult_add_mgr2.tdf
52ebe17a60aaa4a777b8fc57f5d95b7
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated
}
# macro_sequence

# end
# entity
ded_mult_ks81
# storage
db|LED_hello_world.(32).cnf
db|LED_hello_world.(32).cnf
# case_insensitive
# source_file
db|ded_mult_ks81.tdf
d926dccb411e6b7355a627ad0ced2f9
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
ena0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
aclr3
-1
1
aclr2
-1
1
aclr1
-1
1
ena3
-1
2
ena2
-1
2
ena1
-1
2
clock3
-1
2
clock2
-1
2
clock1
-1
2
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated|ded_mult_ks81:ded_mult1
}
# macro_sequence

# end
# entity
dffpipe_93c
# storage
db|LED_hello_world.(33).cnf
db|LED_hello_world.(33).cnf
# case_insensitive
# source_file
db|dffpipe_93c.tdf
51f820326468d6a7f57452a5874ade14
7
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d31
-1
3
d30
-1
3
d3
-1
3
d29
-1
3
d28
-1
3
d27
-1
3
d26
-1
3
d25
-1
3
d24
-1
3
d23
-1
3
d22
-1
3
d21
-1
3
d20
-1
3
d2
-1
3
d19
-1
3
d18
-1
3
d17
-1
3
d16
-1
3
d15
-1
3
d14
-1
3
d13
-1
3
d12
-1
3
d11
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_mgr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result
}
# macro_sequence

# end
# entity
altmult_add
# storage
db|LED_hello_world.(34).cnf
db|LED_hello_world.(34).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altmult_add.tdf
61a6fe8a40fd8b58b1825bd77b5dfb
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
ACCUM_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUMULATOR
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER1
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ADDER
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR2
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
NUMBER_OF_MULTIPLIERS
1
PARAMETER_SIGNED_DEC
USR
OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_TYPE
NEAREST_INTEGER
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_TYPE
ASYMMETRIC
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
port_addnsub1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_addnsub3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CHAINOUT_SAT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_OUTPUT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
port_signa
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_signb
PORT_UNUSED
PARAMETER_UNKNOWN
USR
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
REPRESENTATION_B
UNSIGNED
PARAMETER_UNKNOWN
USR
ROTATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
WIDTH_MSB
17
PARAMETER_UNKNOWN
DEF
WIDTH_SATURATE_SIGN
1
PARAMETER_UNKNOWN
DEF
SCANOUTA_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SCANOUTA_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
DEF
SHIFT_MODE
NO
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTH_CHAININ
1
PARAMETER_UNKNOWN
DEF
WIDTH_RESULT
16
PARAMETER_SIGNED_DEC
USR
ZERO_CHAINOUT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_CHAINOUT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_add_ogr2
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
WIDTH_C
22
PARAMETER_UNKNOWN
DEF
LOADCONST_VALUE
64
PARAMETER_UNKNOWN
DEF
PREADDER_MODE
SIMPLE
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_0
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_1
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_2
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_3
ADD
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_C0
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_C0
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL0_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL1_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL2_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL3_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL0_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL1_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL2_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL3_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY1
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY3
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR1
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR3
ACLR0
PARAMETER_UNKNOWN
DEF
COEF0_0
0
PARAMETER_UNKNOWN
DEF
COEF0_1
0
PARAMETER_UNKNOWN
DEF
COEF0_2
0
PARAMETER_UNKNOWN
DEF
COEF0_3
0
PARAMETER_UNKNOWN
DEF
COEF0_4
0
PARAMETER_UNKNOWN
DEF
COEF0_5
0
PARAMETER_UNKNOWN
DEF
COEF0_6
0
PARAMETER_UNKNOWN
DEF
COEF0_7
0
PARAMETER_UNKNOWN
DEF
COEF1_0
0
PARAMETER_UNKNOWN
DEF
COEF1_1
0
PARAMETER_UNKNOWN
DEF
COEF1_2
0
PARAMETER_UNKNOWN
DEF
COEF1_3
0
PARAMETER_UNKNOWN
DEF
COEF1_4
0
PARAMETER_UNKNOWN
DEF
COEF1_5
0
PARAMETER_UNKNOWN
DEF
COEF1_6
0
PARAMETER_UNKNOWN
DEF
COEF1_7
0
PARAMETER_UNKNOWN
DEF
COEF2_0
0
PARAMETER_UNKNOWN
DEF
COEF2_1
0
PARAMETER_UNKNOWN
DEF
COEF2_2
0
PARAMETER_UNKNOWN
DEF
COEF2_3
0
PARAMETER_UNKNOWN
DEF
COEF2_4
0
PARAMETER_UNKNOWN
DEF
COEF2_5
0
PARAMETER_UNKNOWN
DEF
COEF2_6
0
PARAMETER_UNKNOWN
DEF
COEF2_7
0
PARAMETER_UNKNOWN
DEF
COEF3_0
0
PARAMETER_UNKNOWN
DEF
COEF3_1
0
PARAMETER_UNKNOWN
DEF
COEF3_2
0
PARAMETER_UNKNOWN
DEF
COEF3_3
0
PARAMETER_UNKNOWN
DEF
COEF3_4
0
PARAMETER_UNKNOWN
DEF
COEF3_5
0
PARAMETER_UNKNOWN
DEF
COEF3_6
0
PARAMETER_UNKNOWN
DEF
COEF3_7
0
PARAMETER_UNKNOWN
DEF
WIDTH_COEF
18
PARAMETER_UNKNOWN
DEF
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
ena0
-1
2
}
# include_file {
stratix_mac_out.inc
9ac89b9d6c98d3e379f29a56f74933
stratix_mac_mult.inc
39994655f1ee0a1246f2c1a60bc98e4
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altmult_add.tdf
61a6fe8a40fd8b58b1825bd77b5dfb
}
# macro_sequence

# end
# entity
mult_add_ogr2
# storage
db|LED_hello_world.(35).cnf
db|LED_hello_world.(35).cnf
# case_insensitive
# source_file
db|mult_add_ogr2.tdf
b9ade75e77d238219478c21fab3c84b8
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_ogr2:auto_generated
}
# macro_sequence

# end
# entity
cpu_nios2_oci
# storage
db|LED_hello_world.(36).cnf
db|LED_hello_world.(36).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci
}
# macro_sequence

# end
# entity
cpu_nios2_oci_debug
# storage
db|LED_hello_world.(37).cnf
db|LED_hello_world.(37).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug
}
# macro_sequence

# end
# entity
cpu_nios2_ocimem
# storage
db|LED_hello_world.(38).cnf
db|LED_hello_world.(38).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem
}
# macro_sequence

# end
# entity
cpu_ociram_lpm_dram_bdp_component_module
# storage
db|LED_hello_world.(39).cnf
db|LED_hello_world.(39).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
cpu_ociram_default_contents.mif
PARAMETER_STRING
USR
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(40).cnf
db|LED_hello_world.(40).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_ociram_default_contents.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_f572
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
altrom.inc
192b74eafa8debf2248ea73881e77f91
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# macro_sequence

# end
# entity
altsyncram_f572
# storage
db|LED_hello_world.(41).cnf
db|LED_hello_world.(41).cnf
# case_insensitive
# source_file
db|altsyncram_f572.tdf
581b19d750745b4cd5bb56ac79355233
7
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a3
-1
3
byteena_a2
-1
3
byteena_a1
-1
3
byteena_a0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_ociram_default_contents.mif
4cbfd3ea3dccf9487ae93f24486ccfe4
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_f572:auto_generated
}
# macro_sequence

# end
# entity
cpu_nios2_avalon_reg
# storage
db|LED_hello_world.(42).cnf
db|LED_hello_world.(42).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg
}
# macro_sequence

# end
# entity
cpu_nios2_oci_break
# storage
db|LED_hello_world.(43).cnf
db|LED_hello_world.(43).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break
}
# macro_sequence

# end
# entity
cpu_nios2_oci_xbrk
# storage
db|LED_hello_world.(44).cnf
db|LED_hello_world.(44).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk
}
# macro_sequence

# end
# entity
cpu_nios2_oci_dbrk
# storage
db|LED_hello_world.(45).cnf
db|LED_hello_world.(45).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk
}
# macro_sequence

# end
# entity
cpu_nios2_oci_itrace
# storage
db|LED_hello_world.(46).cnf
db|LED_hello_world.(46).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace
}
# macro_sequence

# end
# entity
cpu_nios2_oci_dtrace
# storage
db|LED_hello_world.(47).cnf
db|LED_hello_world.(47).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace
}
# macro_sequence

# end
# entity
cpu_nios2_oci_td_mode
# storage
db|LED_hello_world.(48).cnf
db|LED_hello_world.(48).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode
}
# macro_sequence

# end
# entity
cpu_nios2_oci_fifo
# storage
db|LED_hello_world.(49).cnf
db|LED_hello_world.(49).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo
}
# macro_sequence

# end
# entity
cpu_nios2_oci_compute_tm_count
# storage
db|LED_hello_world.(50).cnf
db|LED_hello_world.(50).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count
}
# macro_sequence

# end
# entity
cpu_nios2_oci_fifowp_inc
# storage
db|LED_hello_world.(51).cnf
db|LED_hello_world.(51).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp
}
# macro_sequence

# end
# entity
cpu_nios2_oci_fifocount_inc
# storage
db|LED_hello_world.(52).cnf
db|LED_hello_world.(52).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount
}
# macro_sequence

# end
# entity
cpu_oci_test_bench
# storage
db|LED_hello_world.(53).cnf
db|LED_hello_world.(53).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_oci_test_bench.v
59b4a1b159b86910d0b65e50dbd3a55e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_oci_test_bench:the_cpu_oci_test_bench
}
# macro_sequence

# end
# entity
cpu_nios2_oci_pib
# storage
db|LED_hello_world.(54).cnf
db|LED_hello_world.(54).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib
}
# macro_sequence

# end
# entity
cpu_nios2_oci_im
# storage
db|LED_hello_world.(55).cnf
db|LED_hello_world.(55).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im
}
# macro_sequence

# end
# entity
cpu_traceram_lpm_dram_bdp_component_module
# storage
db|LED_hello_world.(56).cnf
db|LED_hello_world.(56).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
4db35e312a8784d53468c99ce5b55d3e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(57).cnf
db|LED_hello_world.(57).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
36
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
128
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
36
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
128
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_0a02
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
altrom.inc
192b74eafa8debf2248ea73881e77f91
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# macro_sequence

# end
# entity
altsyncram_0a02
# storage
db|LED_hello_world.(58).cnf
db|LED_hello_world.(58).cnf
# case_insensitive
# source_file
db|altsyncram_0a02.tdf
b815c6bc2c9f79a13485bdf3971b1bfe
7
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a35
-1
3
q_a34
-1
3
q_a33
-1
3
q_a32
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b35
-1
3
data_b34
-1
3
data_b33
-1
3
data_b32
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated
}
# macro_sequence

# end
# entity
cpu_jtag_debug_module_wrapper
# storage
db|LED_hello_world.(59).cnf
db|LED_hello_world.(59).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_jtag_debug_module_wrapper.v
f95ebb190854182b85befdb427aa867
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper
}
# macro_sequence

# end
# entity
cpu_jtag_debug_module_tck
# storage
db|LED_hello_world.(60).cnf
db|LED_hello_world.(60).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_jtag_debug_module_tck.v
2e319a607581691da66069f5a8f061d1
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck
}
# macro_sequence

# end
# entity
altera_std_synchronizer
# storage
db|LED_hello_world.(61).cnf
db|LED_hello_world.(61).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altera_std_synchronizer.v
3953f4d05760cbbea8ee11c946b3e47
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
depth
2
PARAMETER_SIGNED_DEC
USR
}
# include_file {
altera_std_synchronizer.v
3953f4d05760cbbea8ee11c946b3e47
}
# macro_sequence

# end
# entity
cpu_jtag_debug_module_sysclk
# storage
db|LED_hello_world.(62).cnf
db|LED_hello_world.(62).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_jtag_debug_module_sysclk.v
be465919a217c5b5ff81914b2298f21
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk
}
# macro_sequence

# end
# entity
sld_virtual_jtag_basic
# storage
db|LED_hello_world.(63).cnf
db|LED_hello_world.(63).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_virtual_jtag_basic.v
47cfae98cb3c8897dd15a8785bfc75
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
sld_mfg_id
70
PARAMETER_SIGNED_DEC
USR
sld_type_id
34
PARAMETER_SIGNED_DEC
USR
sld_version
3
PARAMETER_SIGNED_DEC
USR
sld_instance_index
0
PARAMETER_SIGNED_DEC
USR
sld_auto_instance_index
YES
PARAMETER_STRING
USR
sld_ir_width
2
PARAMETER_SIGNED_DEC
USR
sld_sim_n_scan
0
PARAMETER_SIGNED_DEC
USR
sld_sim_action

PARAMETER_STRING
USR
sld_sim_total_length
0
PARAMETER_SIGNED_DEC
USR
lpm_type
sld_virtual_jtag_basic
PARAMETER_STRING
DEF
lpm_hint
UNUSED
PARAMETER_STRING
DEF
}
# include_file {
sld_virtual_jtag_basic.v
47cfae98cb3c8897dd15a8785bfc75
}
# macro_sequence

# end
# entity
sld_virtual_jtag_impl
# storage
db|LED_hello_world.(64).cnf
db|LED_hello_world.(64).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_virtual_jtag_basic.v
47cfae98cb3c8897dd15a8785bfc75
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
sld_mfg_id
70
PARAMETER_SIGNED_DEC
USR
sld_type_id
34
PARAMETER_SIGNED_DEC
USR
sld_version
3
PARAMETER_SIGNED_DEC
USR
sld_instance_index
0
PARAMETER_SIGNED_DEC
USR
sld_auto_instance_index
YES
PARAMETER_STRING
USR
sld_ir_width
2
PARAMETER_SIGNED_DEC
USR
SLD_NODE_INFO
420496896
PARAMETER_SIGNED_DEC
DEF
}
# include_file {
sld_virtual_jtag_basic.v
47cfae98cb3c8897dd15a8785bfc75
}
# macro_sequence
MASK_8_BITS255INST_BIT_INDEX0MASK_11_BITS2047MFG_BIT_INDEX8MASK_8_BITS255TYPE_BIT_INDEX19MASK_5_BITS31VERION_BIT_INDEX27
# end
# entity
epcs_epcs_control_port_arbitrator
# storage
db|LED_hello_world.(65).cnf
db|LED_hello_world.(65).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port
}
# macro_sequence

# end
# entity
epcs
# storage
db|LED_hello_world.(66).cnf
db|LED_hello_world.(66).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
epcs.v
6022974b1456e38b51e86c4abbdc6
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
INIT_FILE
epcs_boot_rom.hex
PARAMETER_STRING
DEF
}
# hierarchies {
CORE_SOPC:inst|epcs:the_epcs
}
# macro_sequence

# end
# entity
epcs_sub
# storage
db|LED_hello_world.(67).cnf
db|LED_hello_world.(67).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
epcs.v
6022974b1456e38b51e86c4abbdc6
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|epcs:the_epcs|epcs_sub:the_epcs_sub
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(68).cnf
db|LED_hello_world.(68).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
epcs_boot_rom_synth.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_sc31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
}
# include_file {
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
altrom.inc
192b74eafa8debf2248ea73881e77f91
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# macro_sequence

# end
# entity
altsyncram_sc31
# storage
db|LED_hello_world.(69).cnf
db|LED_hello_world.(69).cnf
# case_insensitive
# source_file
db|altsyncram_sc31.tdf
ee1a368c4c2419b77151d893a1476
7
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
epcs_boot_rom_synth.hex
9ddddf27915afe3e6ed7d66b922b93d
}
# hierarchies {
CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom|altsyncram_sc31:auto_generated
}
# macro_sequence

# end
# entity
jtag_uart_avalon_jtag_slave_arbitrator
# storage
db|LED_hello_world.(70).cnf
db|LED_hello_world.(70).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave
}
# macro_sequence

# end
# entity
jtag_uart
# storage
db|LED_hello_world.(71).cnf
db|LED_hello_world.(71).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart.v
57918f201b8a1b81edbe4dc61b68e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart
}
# macro_sequence

# end
# entity
jtag_uart_scfifo_w
# storage
db|LED_hello_world.(72).cnf
db|LED_hello_world.(72).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart.v
57918f201b8a1b81edbe4dc61b68e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w
}
# macro_sequence

# end
# entity
scfifo
# storage
db|LED_hello_world.(73).cnf
db|LED_hello_world.(73).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|scfifo.tdf
892513e141f296ca2a061c832e0b073
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
64
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
6
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_jr21
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
a_fffifo.inc
aa34dd3c645beefc31a3e4ef186db4
a_i2fifo.inc
bfe272f05af0cf849bd8b4748efceffe
a_f2fifo.inc
cebe3836bad826c95e765f77477e8a8b
a_regfifo.inc
8b2977668c8752c10a1f1977c9b9ee6
a_dpfifo.inc
37c2d0bb70d5a3f83a4aa09e62c75080
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
scfifo.tdf
892513e141f296ca2a061c832e0b073
}
# macro_sequence

# end
# entity
scfifo_jr21
# storage
db|LED_hello_world.(74).cnf
db|LED_hello_world.(74).cnf
# case_insensitive
# source_file
db|scfifo_jr21.tdf
71b8f5d91e95ad7b2dbdfdb1716723f
7
# used_port {
wrreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated
}
# macro_sequence

# end
# entity
a_dpfifo_q131
# storage
db|LED_hello_world.(75).cnf
db|LED_hello_world.(75).cnf
# case_insensitive
# source_file
db|a_dpfifo_q131.tdf
235cd29d50597733e234dbf3eb64d8e
7
# used_port {
wreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo
}
# macro_sequence

# end
# entity
a_fefifo_7cf
# storage
db|LED_hello_world.(76).cnf
db|LED_hello_world.(76).cnf
# case_insensitive
# source_file
db|a_fefifo_7cf.tdf
2629c9c9779dcf8bb2ece8d44ed5e67
7
# used_port {
wreq
-1
3
usedw_out5
-1
3
usedw_out4
-1
3
usedw_out3
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state
}
# macro_sequence

# end
# entity
cntr_do7
# storage
db|LED_hello_world.(77).cnf
db|LED_hello_world.(77).cnf
# case_insensitive
# source_file
db|cntr_do7.tdf
5ddeaad1f5e5d5cc53f02a3e844c561f
7
# used_port {
updown
-1
3
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw
}
# macro_sequence

# end
# entity
dpram_nl21
# storage
db|LED_hello_world.(78).cnf
db|LED_hello_world.(78).cnf
# case_insensitive
# source_file
db|dpram_nl21.tdf
943453c23677dd2bcdfb08276445fe5
7
# used_port {
wren
-1
3
wraddress5
-1
3
wraddress4
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress5
-1
3
rdaddress4
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram
}
# macro_sequence

# end
# entity
altsyncram_r1m1
# storage
db|LED_hello_world.(79).cnf
db|LED_hello_world.(79).cnf
# case_insensitive
# source_file
db|altsyncram_r1m1.tdf
1276b73b9eb447e6416249de46e3ac
7
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1
}
# macro_sequence

# end
# entity
cntr_1ob
# storage
db|LED_hello_world.(80).cnf
db|LED_hello_world.(80).cnf
# case_insensitive
# source_file
db|cntr_1ob.tdf
b4f8eac5a8cb15567c1b962aaf4268d
7
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr
}
# macro_sequence

# end
# entity
jtag_uart_scfifo_r
# storage
db|LED_hello_world.(81).cnf
db|LED_hello_world.(81).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart.v
57918f201b8a1b81edbe4dc61b68e8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r
}
# macro_sequence

# end
# entity
alt_jtag_atlantic
# storage
db|LED_hello_world.(82).cnf
db|LED_hello_world.(82).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|alt_jtag_atlantic.v
d86551e05817d27f31e31fe2c53f393e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
INSTANCE_ID
0
PARAMETER_SIGNED_DEC
USR
SLD_NODE_INFO
00001100000000000110111000000000
PARAMETER_UNSIGNED_BIN
DEF
SLD_AUTO_INSTANCE_INDEX
YES
PARAMETER_STRING
USR
LOG2_TXFIFO_DEPTH
6
PARAMETER_SIGNED_DEC
USR
LOG2_RXFIFO_DEPTH
6
PARAMETER_SIGNED_DEC
USR
RESERVED
0
PARAMETER_SIGNED_DEC
DEF
DATA_WIDTH
8
PARAMETER_SIGNED_DEC
DEF
NODE_IR_WIDTH
1
PARAMETER_SIGNED_DEC
DEF
SCAN_LENGTH
11
PARAMETER_SIGNED_DEC
DEF
}
# include_file {
alt_jtag_atlantic.v
d86551e05817d27f31e31fe2c53f393e
}
# macro_sequence

# end
# entity
lcd32_data_s1_arbitrator
# storage
db|LED_hello_world.(83).cnf
db|LED_hello_world.(83).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd32_data_s1_arbitrator:the_lcd32_data_s1
}
# macro_sequence

# end
# entity
lcd32_data
# storage
db|LED_hello_world.(84).cnf
db|LED_hello_world.(84).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd32_data.v
3f706b60c090aac134e61574446f639
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd32_data:the_lcd32_data
}
# macro_sequence

# end
# entity
lcd_cs_s1_arbitrator
# storage
db|LED_hello_world.(85).cnf
db|LED_hello_world.(85).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd_cs_s1_arbitrator:the_lcd_cs_s1
}
# macro_sequence

# end
# entity
lcd_cs
# storage
db|LED_hello_world.(86).cnf
db|LED_hello_world.(86).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd_cs.v
20a0ad5e2b6093da62754e9f71839094
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd_cs:the_lcd_cs
}
# macro_sequence

# end
# entity
lcd_rd_s1_arbitrator
# storage
db|LED_hello_world.(87).cnf
db|LED_hello_world.(87).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd_rd_s1_arbitrator:the_lcd_rd_s1
}
# macro_sequence

# end
# entity
lcd_rd
# storage
db|LED_hello_world.(88).cnf
db|LED_hello_world.(88).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd_rd.v
58311e6d0a350104798deb2bb8d4216
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd_rd:the_lcd_rd
}
# macro_sequence

# end
# entity
lcd_rs_s1_arbitrator
# storage
db|LED_hello_world.(89).cnf
db|LED_hello_world.(89).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd_rs_s1_arbitrator:the_lcd_rs_s1
}
# macro_sequence

# end
# entity
lcd_rs
# storage
db|LED_hello_world.(90).cnf
db|LED_hello_world.(90).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd_rs.v
5cada7889a2e350e7dae7bc2812bac1
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd_rs:the_lcd_rs
}
# macro_sequence

# end
# entity
lcd_wr_s1_arbitrator
# storage
db|LED_hello_world.(91).cnf
db|LED_hello_world.(91).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd_wr_s1_arbitrator:the_lcd_wr_s1
}
# macro_sequence

# end
# entity
lcd_wr
# storage
db|LED_hello_world.(92).cnf
db|LED_hello_world.(92).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd_wr.v
1855c4eefa41c97b14646fe74fc79526
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|lcd_wr:the_lcd_wr
}
# macro_sequence

# end
# entity
reset_s1_arbitrator
# storage
db|LED_hello_world.(93).cnf
db|LED_hello_world.(93).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|reset_s1_arbitrator:the_reset_s1
}
# macro_sequence

# end
# entity
reset
# storage
db|LED_hello_world.(94).cnf
db|LED_hello_world.(94).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
reset.v
39a36bc7aa8b5269fc6c4e8c3676c15
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|reset:the_reset
}
# macro_sequence

# end
# entity
sdram_s1_arbitrator
# storage
db|LED_hello_world.(95).cnf
db|LED_hello_world.(95).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_data_master_to_sdram_s1_module
# storage
db|LED_hello_world.(96).cnf
db|LED_hello_world.(96).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1
}
# macro_sequence

# end
# entity
rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module
# storage
db|LED_hello_world.(97).cnf
db|LED_hello_world.(97).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1
}
# macro_sequence

# end
# entity
sdram
# storage
db|LED_hello_world.(98).cnf
db|LED_hello_world.(98).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram.v
f140abcd10c6c2dc4032e06753b15cb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|sdram:the_sdram
}
# macro_sequence

# end
# entity
sdram_input_efifo_module
# storage
db|LED_hello_world.(99).cnf
db|LED_hello_world.(99).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram.v
f140abcd10c6c2dc4032e06753b15cb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module
}
# macro_sequence

# end
# entity
spi_touch_spi_control_port_arbitrator
# storage
db|LED_hello_world.(100).cnf
db|LED_hello_world.(100).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port
}
# macro_sequence

# end
# entity
spi_touch
# storage
db|LED_hello_world.(101).cnf
db|LED_hello_world.(101).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
spi_touch.v
212e61aa307de88877998c77aa36ce7
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|spi_touch:the_spi_touch
}
# macro_sequence

# end
# entity
sysid_control_slave_arbitrator
# storage
db|LED_hello_world.(102).cnf
db|LED_hello_world.(102).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|sysid_control_slave_arbitrator:the_sysid_control_slave
}
# macro_sequence

# end
# entity
sysid
# storage
db|LED_hello_world.(103).cnf
db|LED_hello_world.(103).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sysid.v
5f2e1db2626428f41861508c73938f2
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|sysid:the_sysid
}
# macro_sequence

# end
# entity
touch_cs_s1_arbitrator
# storage
db|LED_hello_world.(104).cnf
db|LED_hello_world.(104).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|touch_cs_s1_arbitrator:the_touch_cs_s1
}
# macro_sequence

# end
# entity
touch_cs
# storage
db|LED_hello_world.(105).cnf
db|LED_hello_world.(105).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
touch_cs.v
ff452693db1a3a32b55db41f98616d99
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|touch_cs:the_touch_cs
}
# macro_sequence

# end
# entity
touch_irq_s1_arbitrator
# storage
db|LED_hello_world.(106).cnf
db|LED_hello_world.(106).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|touch_irq_s1_arbitrator:the_touch_irq_s1
}
# macro_sequence

# end
# entity
touch_irq
# storage
db|LED_hello_world.(107).cnf
db|LED_hello_world.(107).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
touch_irq.v
2c4cc5a8683b7736eb3177cc5cf93c1c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|touch_irq:the_touch_irq
}
# macro_sequence

# end
# entity
CORE_SOPC_reset_clk_domain_synch_module
# storage
db|LED_hello_world.(108).cnf
db|LED_hello_world.(108).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core_sopc.v
f4f71081367e4d9274f5df3a7a87266
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch
}
# macro_sequence

# end
# entity
sld_hub
# storage
db|LED_hello_world.(109).cnf
db|LED_hello_world.(109).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_hub.vhd
c788d113824f94d85789fc98ccb05494
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
4
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone IV E
PARAMETER_UNKNOWN
USR
n_nodes
2
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
5
PARAMETER_UNKNOWN
USR
node_info
0000110000000000011011100000000000011001000100000100011000000000
PARAMETER_UNSIGNED_BIN
USR
compilation_mode
1
PARAMETER_UNKNOWN
USR
BROADCAST_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
FORCE_IR_CAPTURE_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
}
# include_file {
sld_hub.vhd
c788d113824f94d85789fc98ccb05494
}
# macro_sequence

# end
# entity
sld_shadow_jsm
# storage
db|LED_hello_world.(110).cnf
db|LED_hello_world.(110).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_hub.vhd
c788d113824f94d85789fc98ccb05494
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
1
PARAMETER_SIGNED_DEC
USR
ip_minor_version
4
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
 constraint(jtag_state)
15 downto 0
PARAMETER_STRING
USR
}
# include_file {
sld_hub.vhd
c788d113824f94d85789fc98ccb05494
}
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|LED_hello_world.(111).cnf
db|LED_hello_world.(111).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_rom_sr.vhd
fdb1f8013679df812f23bf0ce3476a1
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
96
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
95 downto 0
PARAMETER_STRING
USR
}
# include_file {
sld_rom_sr.vhd
fdb1f8013679df812f23bf0ce3476a1
}
# macro_sequence

# end
# entity
lpm_add_sub
# storage
db|LED_hello_world.(112).cnf
db|LED_hello_world.(112).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|lpm_add_sub.tdf
21fac4014af92a431e599d80e9741
7
# user_parameter {
LPM_WIDTH
33
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_qvi
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result32
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab31
-1
3
datab30
-1
3
datab3
-1
3
datab29
-1
3
datab28
-1
3
datab27
-1
3
datab26
-1
3
datab25
-1
3
datab24
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa31
-1
3
dataa30
-1
3
dataa3
-1
3
dataa29
-1
3
dataa28
-1
3
dataa27
-1
3
dataa26
-1
3
dataa25
-1
3
dataa24
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
add_sub
-1
3
datab32
-1
1
dataa32
-1
1
}
# include_file {
altshift.inc
5c767a29f11db3f131fc886ea42a52bd
alt_stratix_add_sub.inc
16df31198e4f1dce2b8df944fbafaefe
lpm_add_sub.tdf
21fac4014af92a431e599d80e9741
look_add.inc
9091c394592369a07bdf7fbf1ce9ced6
bypassff.inc
42d08f243d3471f724fd61ea21a0eb9f
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
addcore.inc
e15993f131a5367862d6283fbb5a133
}
# macro_sequence

# end
# entity
add_sub_qvi
# storage
db|LED_hello_world.(113).cnf
db|LED_hello_world.(113).cnf
# case_insensitive
# source_file
db|add_sub_qvi.tdf
697a6064198c4a66eb20e3df43a0ede4
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result32
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab32
-1
3
datab31
-1
3
datab30
-1
3
datab3
-1
3
datab29
-1
3
datab28
-1
3
datab27
-1
3
datab26
-1
3
datab25
-1
3
datab24
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa32
-1
3
dataa31
-1
3
dataa30
-1
3
dataa3
-1
3
dataa29
-1
3
dataa28
-1
3
dataa27
-1
3
dataa26
-1
3
dataa25
-1
3
dataa24
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
add_sub
-1
3
}
# macro_sequence

# end
# entity
altpll
# storage
db|LED_hello_world.(114).cnf
db|LED_hello_world.(114).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altpll.tdf
452f627ba8b04372419df6af11f0325f
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
LPM_HINT
CBX_MODULE_PREFIX=PLL
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
USR
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
-5556
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
PLL_altpll
PARAMETER_UNKNOWN
USR
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
5
PARAMETER_SIGNED_DEC
USR
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
configupdate
-1
1
clkswitch
-1
1
areset
-1
1
scanclkena
-1
2
pllena
-1
2
phaseupdown
-1
2
phasestep
-1
2
phasecounterselect
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
stratixii_pll.inc
6797ab505ed70f1a221e4a213e16a6
stratix_pll.inc
a9a94c5be18105f7ae8c218a67ec9f7
cycloneii_pll.inc
c2ee779f89b3bc181df753ea85b3ef
altpll.tdf
452f627ba8b04372419df6af11f0325f
}
# hierarchies {
PLL:inst1|altpll:altpll_component
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(115).cnf
db|LED_hello_world.(115).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
512
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
512
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_udd1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altrom.inc
192b74eafa8debf2248ea73881e77f91
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(116).cnf
db|LED_hello_world.(116).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
24
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
64
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
24
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
64
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_ic_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_i2g1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altrom.inc
192b74eafa8debf2248ea73881e77f91
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(117).cnf
db|LED_hello_world.(117).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
2
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
2
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_bht_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_bpf1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altrom.inc
192b74eafa8debf2248ea73881e77f91
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(118).cnf
db|LED_hello_world.(118).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_rf_ram_a.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_b7f1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altrom.inc
192b74eafa8debf2248ea73881e77f91
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(119).cnf
db|LED_hello_world.(119).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_rf_ram_b.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_c7f1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altrom.inc
192b74eafa8debf2248ea73881e77f91
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altmult_add
# storage
db|LED_hello_world.(120).cnf
db|LED_hello_world.(120).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altmult_add.tdf
61a6fe8a40fd8b58b1825bd77b5dfb
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
ACCUM_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUMULATOR
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER1
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ADDER
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR2
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
NUMBER_OF_MULTIPLIERS
1
PARAMETER_SIGNED_DEC
USR
OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_TYPE
NEAREST_INTEGER
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_TYPE
ASYMMETRIC
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
port_addnsub1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_addnsub3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CHAINOUT_SAT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_OUTPUT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
port_signa
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_signb
PORT_UNUSED
PARAMETER_UNKNOWN
USR
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
REPRESENTATION_B
UNSIGNED
PARAMETER_UNKNOWN
USR
ROTATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
WIDTH_MSB
17
PARAMETER_UNKNOWN
DEF
WIDTH_SATURATE_SIGN
1
PARAMETER_UNKNOWN
DEF
SCANOUTA_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SCANOUTA_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
DEF
SHIFT_MODE
NO
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTH_CHAININ
1
PARAMETER_UNKNOWN
DEF
WIDTH_RESULT
32
PARAMETER_SIGNED_DEC
USR
ZERO_CHAINOUT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_CHAINOUT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_add_mgr2
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
WIDTH_C
22
PARAMETER_UNKNOWN
DEF
LOADCONST_VALUE
64
PARAMETER_UNKNOWN
DEF
PREADDER_MODE
SIMPLE
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_0
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_1
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_2
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_3
ADD
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_C0
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_C0
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL0_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL1_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL2_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL3_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL0_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL1_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL2_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL3_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY1
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY3
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR1
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR3
ACLR0
PARAMETER_UNKNOWN
DEF
COEF0_0
0
PARAMETER_UNKNOWN
DEF
COEF0_1
0
PARAMETER_UNKNOWN
DEF
COEF0_2
0
PARAMETER_UNKNOWN
DEF
COEF0_3
0
PARAMETER_UNKNOWN
DEF
COEF0_4
0
PARAMETER_UNKNOWN
DEF
COEF0_5
0
PARAMETER_UNKNOWN
DEF
COEF0_6
0
PARAMETER_UNKNOWN
DEF
COEF0_7
0
PARAMETER_UNKNOWN
DEF
COEF1_0
0
PARAMETER_UNKNOWN
DEF
COEF1_1
0
PARAMETER_UNKNOWN
DEF
COEF1_2
0
PARAMETER_UNKNOWN
DEF
COEF1_3
0
PARAMETER_UNKNOWN
DEF
COEF1_4
0
PARAMETER_UNKNOWN
DEF
COEF1_5
0
PARAMETER_UNKNOWN
DEF
COEF1_6
0
PARAMETER_UNKNOWN
DEF
COEF1_7
0
PARAMETER_UNKNOWN
DEF
COEF2_0
0
PARAMETER_UNKNOWN
DEF
COEF2_1
0
PARAMETER_UNKNOWN
DEF
COEF2_2
0
PARAMETER_UNKNOWN
DEF
COEF2_3
0
PARAMETER_UNKNOWN
DEF
COEF2_4
0
PARAMETER_UNKNOWN
DEF
COEF2_5
0
PARAMETER_UNKNOWN
DEF
COEF2_6
0
PARAMETER_UNKNOWN
DEF
COEF2_7
0
PARAMETER_UNKNOWN
DEF
COEF3_0
0
PARAMETER_UNKNOWN
DEF
COEF3_1
0
PARAMETER_UNKNOWN
DEF
COEF3_2
0
PARAMETER_UNKNOWN
DEF
COEF3_3
0
PARAMETER_UNKNOWN
DEF
COEF3_4
0
PARAMETER_UNKNOWN
DEF
COEF3_5
0
PARAMETER_UNKNOWN
DEF
COEF3_6
0
PARAMETER_UNKNOWN
DEF
COEF3_7
0
PARAMETER_UNKNOWN
DEF
WIDTH_COEF
18
PARAMETER_UNKNOWN
DEF
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
ena0
-1
2
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
stratix_mac_out.inc
9ac89b9d6c98d3e379f29a56f74933
altmult_add.tdf
61a6fe8a40fd8b58b1825bd77b5dfb
stratix_mac_mult.inc
39994655f1ee0a1246f2c1a60bc98e4
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1
}
# macro_sequence

# end
# entity
altmult_add
# storage
db|LED_hello_world.(121).cnf
db|LED_hello_world.(121).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altmult_add.tdf
61a6fe8a40fd8b58b1825bd77b5dfb
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
ACCUM_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUM_SLOAD_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ACCUMULATOR
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER1
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ADDER
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CHAINOUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR2
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
ADD
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
NUMBER_OF_MULTIPLIERS
1
PARAMETER_SIGNED_DEC
USR
OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUND_TYPE
NEAREST_INTEGER
PARAMETER_UNKNOWN
DEF
OUTPUT_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATE_TYPE
ASYMMETRIC
PARAMETER_UNKNOWN
DEF
OUTPUT_SATURATION
NO
PARAMETER_UNKNOWN
DEF
port_addnsub1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_addnsub3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CHAINOUT_SAT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_OUTPUT_IS_OVERFLOW
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
port_signa
PORT_UNUSED
PARAMETER_UNKNOWN
USR
port_signb
PORT_UNUSED
PARAMETER_UNKNOWN
USR
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
REPRESENTATION_B
UNSIGNED
PARAMETER_UNKNOWN
USR
ROTATE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ROTATE_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ROTATE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
WIDTH_MSB
17
PARAMETER_UNKNOWN
DEF
WIDTH_SATURATE_SIGN
1
PARAMETER_UNKNOWN
DEF
SCANOUTA_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SCANOUTA_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
DEF
SHIFT_MODE
NO
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SHIFT_RIGHT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTH_CHAININ
1
PARAMETER_UNKNOWN
DEF
WIDTH_RESULT
16
PARAMETER_SIGNED_DEC
USR
ZERO_CHAINOUT_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_CHAINOUT_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_OUTPUT_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ZERO_LOOPBACK_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_add_ogr2
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
WIDTH_C
22
PARAMETER_UNKNOWN
DEF
LOADCONST_VALUE
64
PARAMETER_UNKNOWN
DEF
PREADDER_MODE
SIMPLE
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_0
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_1
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_2
ADD
PARAMETER_UNKNOWN
DEF
PREADDER_DIRECTION_3
ADD
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_C0
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_C0
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL0_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL1_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL2_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL3_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
COEFSEL0_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL1_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL2_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
COEFSEL3_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY1
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_DELAY3
CLOCK0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR1
ACLR0
PARAMETER_UNKNOWN
DEF
SYSTOLIC_ACLR3
ACLR0
PARAMETER_UNKNOWN
DEF
COEF0_0
0
PARAMETER_UNKNOWN
DEF
COEF0_1
0
PARAMETER_UNKNOWN
DEF
COEF0_2
0
PARAMETER_UNKNOWN
DEF
COEF0_3
0
PARAMETER_UNKNOWN
DEF
COEF0_4
0
PARAMETER_UNKNOWN
DEF
COEF0_5
0
PARAMETER_UNKNOWN
DEF
COEF0_6
0
PARAMETER_UNKNOWN
DEF
COEF0_7
0
PARAMETER_UNKNOWN
DEF
COEF1_0
0
PARAMETER_UNKNOWN
DEF
COEF1_1
0
PARAMETER_UNKNOWN
DEF
COEF1_2
0
PARAMETER_UNKNOWN
DEF
COEF1_3
0
PARAMETER_UNKNOWN
DEF
COEF1_4
0
PARAMETER_UNKNOWN
DEF
COEF1_5
0
PARAMETER_UNKNOWN
DEF
COEF1_6
0
PARAMETER_UNKNOWN
DEF
COEF1_7
0
PARAMETER_UNKNOWN
DEF
COEF2_0
0
PARAMETER_UNKNOWN
DEF
COEF2_1
0
PARAMETER_UNKNOWN
DEF
COEF2_2
0
PARAMETER_UNKNOWN
DEF
COEF2_3
0
PARAMETER_UNKNOWN
DEF
COEF2_4
0
PARAMETER_UNKNOWN
DEF
COEF2_5
0
PARAMETER_UNKNOWN
DEF
COEF2_6
0
PARAMETER_UNKNOWN
DEF
COEF2_7
0
PARAMETER_UNKNOWN
DEF
COEF3_0
0
PARAMETER_UNKNOWN
DEF
COEF3_1
0
PARAMETER_UNKNOWN
DEF
COEF3_2
0
PARAMETER_UNKNOWN
DEF
COEF3_3
0
PARAMETER_UNKNOWN
DEF
COEF3_4
0
PARAMETER_UNKNOWN
DEF
COEF3_5
0
PARAMETER_UNKNOWN
DEF
COEF3_6
0
PARAMETER_UNKNOWN
DEF
COEF3_7
0
PARAMETER_UNKNOWN
DEF
WIDTH_COEF
18
PARAMETER_UNKNOWN
DEF
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
ena0
-1
2
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
stratix_mac_out.inc
9ac89b9d6c98d3e379f29a56f74933
altmult_add.tdf
61a6fe8a40fd8b58b1825bd77b5dfb
stratix_mac_mult.inc
39994655f1ee0a1246f2c1a60bc98e4
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(122).cnf
db|LED_hello_world.(122).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
cpu_ociram_default_contents.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_f572
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altrom.inc
192b74eafa8debf2248ea73881e77f91
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|LED_hello_world.(123).cnf
db|LED_hello_world.(123).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
36
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
128
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
36
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
128
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_0a02
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altrom.inc
192b74eafa8debf2248ea73881e77f91
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# macro_sequence

# end
# entity
altera_std_synchronizer
# storage
db|LED_hello_world.(124).cnf
db|LED_hello_world.(124).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altera_std_synchronizer.v
3953f4d05760cbbea8ee11c946b3e47
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
depth
2
PARAMETER_SIGNED_DEC
USR
}
# include_file {
altera_std_synchronizer.v
3953f4d05760cbbea8ee11c946b3e47
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
}
# macro_sequence

# end
# entity
sld_virtual_jtag_basic
# storage
db|LED_hello_world.(125).cnf
db|LED_hello_world.(125).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_virtual_jtag_basic.v
47cfae98cb3c8897dd15a8785bfc75
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
sld_mfg_id
70
PARAMETER_SIGNED_DEC
USR
sld_type_id
34
PARAMETER_SIGNED_DEC
USR
sld_version
3
PARAMETER_SIGNED_DEC
USR
sld_instance_index
0
PARAMETER_SIGNED_DEC
USR
sld_auto_instance_index
YES
PARAMETER_STRING
USR
sld_ir_width
2
PARAMETER_SIGNED_DEC
USR
sld_sim_n_scan
0
PARAMETER_SIGNED_DEC
USR
sld_sim_action

PARAMETER_STRING
USR
sld_sim_total_length
0
PARAMETER_SIGNED_DEC
USR
lpm_type
sld_virtual_jtag_basic
PARAMETER_STRING
DEF
lpm_hint
UNUSED
PARAMETER_STRING
DEF
}
# include_file {
sld_virtual_jtag_basic.v
47cfae98cb3c8897dd15a8785bfc75
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy
}
# macro_sequence

# end
# entity
sld_virtual_jtag_impl
# storage
db|LED_hello_world.(126).cnf
db|LED_hello_world.(126).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_virtual_jtag_basic.v
47cfae98cb3c8897dd15a8785bfc75
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
sld_mfg_id
70
PARAMETER_SIGNED_DEC
USR
sld_type_id
34
PARAMETER_SIGNED_DEC
USR
sld_version
3
PARAMETER_SIGNED_DEC
USR
sld_instance_index
0
PARAMETER_SIGNED_DEC
USR
sld_auto_instance_index
YES
PARAMETER_STRING
USR
sld_ir_width
2
PARAMETER_SIGNED_DEC
USR
SLD_NODE_INFO
420496896
PARAMETER_SIGNED_DEC
DEF
}
# include_file {
sld_virtual_jtag_basic.v
47cfae98cb3c8897dd15a8785bfc75
}
# hierarchies {
CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst
}
# macro_sequence
MASK_8_BITS255INST_BIT_INDEX0MASK_11_BITS2047MFG_BIT_INDEX8MASK_8_BITS255TYPE_BIT_INDEX19MASK_5_BITS31VERION_BIT_INDEX27
# end
# entity
altsyncram
# storage
db|LED_hello_world.(127).cnf
db|LED_hello_world.(127).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
epcs_boot_rom_synth.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_sc31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
altsyncram.tdf
736cf06d2afc9e5e1a8bf0561a916c82
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
a_rdenreg.inc
3fcdce755959d5a8afbe64788d21fb
lpm_decode.inc
10da69a8bbd590d66779e7a142f73790
stratix_ram_block.inc
e3a03868917fb3dd57b6ed1dd195f22
altrom.inc
192b74eafa8debf2248ea73881e77f91
altram.inc
ad5518b39ffd3cf1df377e6360d1c9b6
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
}
# hierarchies {
CORE_SOPC:inst|epcs:the_epcs|altsyncram:the_boot_copier_rom
}
# macro_sequence

# end
# entity
scfifo
# storage
db|LED_hello_world.(128).cnf
db|LED_hello_world.(128).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|scfifo.tdf
892513e141f296ca2a061c832e0b073
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
64
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
6
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_jr21
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
a_i2fifo.inc
bfe272f05af0cf849bd8b4748efceffe
a_dpfifo.inc
37c2d0bb70d5a3f83a4aa09e62c75080
a_fffifo.inc
aa34dd3c645beefc31a3e4ef186db4
a_f2fifo.inc
cebe3836bad826c95e765f77477e8a8b
scfifo.tdf
892513e141f296ca2a061c832e0b073
a_regfifo.inc
8b2977668c8752c10a1f1977c9b9ee6
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
CORE_SOPC:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
}
# macro_sequence

# end
# entity
alt_jtag_atlantic
# storage
db|LED_hello_world.(129).cnf
db|LED_hello_world.(129).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|alt_jtag_atlantic.v
d86551e05817d27f31e31fe2c53f393e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
INSTANCE_ID
0
PARAMETER_SIGNED_DEC
USR
SLD_NODE_INFO
00001100000000000110111000000000
PARAMETER_UNSIGNED_BIN
DEF
SLD_AUTO_INSTANCE_INDEX
YES
PARAMETER_STRING
USR
LOG2_TXFIFO_DEPTH
6
PARAMETER_SIGNED_DEC
USR
LOG2_RXFIFO_DEPTH
6
PARAMETER_SIGNED_DEC
USR
RESERVED
0
PARAMETER_SIGNED_DEC
DEF
DATA_WIDTH
8
PARAMETER_SIGNED_DEC
DEF
NODE_IR_WIDTH
1
PARAMETER_SIGNED_DEC
DEF
SCAN_LENGTH
11
PARAMETER_SIGNED_DEC
DEF
}
# include_file {
alt_jtag_atlantic.v
d86551e05817d27f31e31fe2c53f393e
}
# hierarchies {
CORE_SOPC:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
}
# macro_sequence

# end
# entity
sld_hub
# storage
db|LED_hello_world.(130).cnf
db|LED_hello_world.(130).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_hub.vhd
c788d113824f94d85789fc98ccb05494
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
4
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone IV E
PARAMETER_UNKNOWN
USR
n_nodes
2
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
5
PARAMETER_UNKNOWN
USR
node_info
0000110000000000011011100000000000011001000100000100011000000000
PARAMETER_UNSIGNED_BIN
USR
compilation_mode
1
PARAMETER_UNKNOWN
USR
BROADCAST_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
FORCE_IR_CAPTURE_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
}
# include_file {
sld_hub.vhd
c788d113824f94d85789fc98ccb05494
}
# macro_sequence

# end
# entity
sld_shadow_jsm
# storage
db|LED_hello_world.(131).cnf
db|LED_hello_world.(131).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_hub.vhd
c788d113824f94d85789fc98ccb05494
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
1
PARAMETER_SIGNED_DEC
USR
ip_minor_version
4
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
 constraint(jtag_state)
15 downto 0
PARAMETER_STRING
USR
}
# include_file {
sld_hub.vhd
c788d113824f94d85789fc98ccb05494
}
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|LED_hello_world.(132).cnf
db|LED_hello_world.(132).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|sld_rom_sr.vhd
fdb1f8013679df812f23bf0ce3476a1
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
96
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
95 downto 0
PARAMETER_STRING
USR
}
# include_file {
sld_rom_sr.vhd
fdb1f8013679df812f23bf0ce3476a1
}
# macro_sequence

# end
# entity
lpm_add_sub
# storage
db|LED_hello_world.(133).cnf
db|LED_hello_world.(133).cnf
# case_insensitive
# source_file
c:|altera|11.0|quartus|libraries|megafunctions|lpm_add_sub.tdf
21fac4014af92a431e599d80e9741
7
# user_parameter {
LPM_WIDTH
33
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_qvi
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result32
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab31
-1
3
datab30
-1
3
datab3
-1
3
datab29
-1
3
datab28
-1
3
datab27
-1
3
datab26
-1
3
datab25
-1
3
datab24
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa31
-1
3
dataa30
-1
3
dataa3
-1
3
dataa29
-1
3
dataa28
-1
3
dataa27
-1
3
dataa26
-1
3
dataa25
-1
3
dataa24
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
add_sub
-1
3
datab32
-1
1
dataa32
-1
1
}
# include_file {
aglobal110.inc
f560f9a992734abc3e37886b3957a26a
lpm_add_sub.tdf
21fac4014af92a431e599d80e9741
addcore.inc
e15993f131a5367862d6283fbb5a133
alt_stratix_add_sub.inc
16df31198e4f1dce2b8df944fbafaefe
bypassff.inc
42d08f243d3471f724fd61ea21a0eb9f
look_add.inc
9091c394592369a07bdf7fbf1ce9ced6
altshift.inc
5c767a29f11db3f131fc886ea42a52bd
}
# macro_sequence

# end
# complete

