//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module bl_n_s1_arbitrator (
                            // inputs:
                             bl_n_s1_readdata,
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_read,
                             cpu_data_master_waitrequest,
                             cpu_data_master_write,
                             cpu_data_master_writedata,
                             reset_n,

                            // outputs:
                             bl_n_s1_address,
                             bl_n_s1_chipselect,
                             bl_n_s1_readdata_from_sa,
                             bl_n_s1_reset_n,
                             bl_n_s1_write_n,
                             bl_n_s1_writedata,
                             cpu_data_master_granted_bl_n_s1,
                             cpu_data_master_qualified_request_bl_n_s1,
                             cpu_data_master_read_data_valid_bl_n_s1,
                             cpu_data_master_requests_bl_n_s1,
                             d1_bl_n_s1_end_xfer
                          )
;

  output  [  1: 0] bl_n_s1_address;
  output           bl_n_s1_chipselect;
  output  [ 31: 0] bl_n_s1_readdata_from_sa;
  output           bl_n_s1_reset_n;
  output           bl_n_s1_write_n;
  output  [ 31: 0] bl_n_s1_writedata;
  output           cpu_data_master_granted_bl_n_s1;
  output           cpu_data_master_qualified_request_bl_n_s1;
  output           cpu_data_master_read_data_valid_bl_n_s1;
  output           cpu_data_master_requests_bl_n_s1;
  output           d1_bl_n_s1_end_xfer;
  input   [ 31: 0] bl_n_s1_readdata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] bl_n_s1_address;
  wire             bl_n_s1_allgrants;
  wire             bl_n_s1_allow_new_arb_cycle;
  wire             bl_n_s1_any_bursting_master_saved_grant;
  wire             bl_n_s1_any_continuerequest;
  wire             bl_n_s1_arb_counter_enable;
  reg     [  1: 0] bl_n_s1_arb_share_counter;
  wire    [  1: 0] bl_n_s1_arb_share_counter_next_value;
  wire    [  1: 0] bl_n_s1_arb_share_set_values;
  wire             bl_n_s1_beginbursttransfer_internal;
  wire             bl_n_s1_begins_xfer;
  wire             bl_n_s1_chipselect;
  wire             bl_n_s1_end_xfer;
  wire             bl_n_s1_firsttransfer;
  wire             bl_n_s1_grant_vector;
  wire             bl_n_s1_in_a_read_cycle;
  wire             bl_n_s1_in_a_write_cycle;
  wire             bl_n_s1_master_qreq_vector;
  wire             bl_n_s1_non_bursting_master_requests;
  wire    [ 31: 0] bl_n_s1_readdata_from_sa;
  reg              bl_n_s1_reg_firsttransfer;
  wire             bl_n_s1_reset_n;
  reg              bl_n_s1_slavearbiterlockenable;
  wire             bl_n_s1_slavearbiterlockenable2;
  wire             bl_n_s1_unreg_firsttransfer;
  wire             bl_n_s1_waits_for_read;
  wire             bl_n_s1_waits_for_write;
  wire             bl_n_s1_write_n;
  wire    [ 31: 0] bl_n_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_bl_n_s1;
  wire             cpu_data_master_qualified_request_bl_n_s1;
  wire             cpu_data_master_read_data_valid_bl_n_s1;
  wire             cpu_data_master_requests_bl_n_s1;
  wire             cpu_data_master_saved_grant_bl_n_s1;
  reg              d1_bl_n_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_bl_n_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 26: 0] shifted_address_to_bl_n_s1_from_cpu_data_master;
  wire             wait_for_bl_n_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~bl_n_s1_end_xfer;
    end


  assign bl_n_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_bl_n_s1));
  //assign bl_n_s1_readdata_from_sa = bl_n_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign bl_n_s1_readdata_from_sa = bl_n_s1_readdata;

  assign cpu_data_master_requests_bl_n_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h18b0) & (cpu_data_master_read | cpu_data_master_write);
  //bl_n_s1_arb_share_counter set values, which is an e_mux
  assign bl_n_s1_arb_share_set_values = 1;

  //bl_n_s1_non_bursting_master_requests mux, which is an e_mux
  assign bl_n_s1_non_bursting_master_requests = cpu_data_master_requests_bl_n_s1;

  //bl_n_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign bl_n_s1_any_bursting_master_saved_grant = 0;

  //bl_n_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign bl_n_s1_arb_share_counter_next_value = bl_n_s1_firsttransfer ? (bl_n_s1_arb_share_set_values - 1) : |bl_n_s1_arb_share_counter ? (bl_n_s1_arb_share_counter - 1) : 0;

  //bl_n_s1_allgrants all slave grants, which is an e_mux
  assign bl_n_s1_allgrants = |bl_n_s1_grant_vector;

  //bl_n_s1_end_xfer assignment, which is an e_assign
  assign bl_n_s1_end_xfer = ~(bl_n_s1_waits_for_read | bl_n_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_bl_n_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_bl_n_s1 = bl_n_s1_end_xfer & (~bl_n_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //bl_n_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign bl_n_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_bl_n_s1 & bl_n_s1_allgrants) | (end_xfer_arb_share_counter_term_bl_n_s1 & ~bl_n_s1_non_bursting_master_requests);

  //bl_n_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bl_n_s1_arb_share_counter <= 0;
      else if (bl_n_s1_arb_counter_enable)
          bl_n_s1_arb_share_counter <= bl_n_s1_arb_share_counter_next_value;
    end


  //bl_n_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bl_n_s1_slavearbiterlockenable <= 0;
      else if ((|bl_n_s1_master_qreq_vector & end_xfer_arb_share_counter_term_bl_n_s1) | (end_xfer_arb_share_counter_term_bl_n_s1 & ~bl_n_s1_non_bursting_master_requests))
          bl_n_s1_slavearbiterlockenable <= |bl_n_s1_arb_share_counter_next_value;
    end


  //cpu/data_master bl_n/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = bl_n_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //bl_n_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign bl_n_s1_slavearbiterlockenable2 = |bl_n_s1_arb_share_counter_next_value;

  //cpu/data_master bl_n/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = bl_n_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //bl_n_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign bl_n_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_bl_n_s1 = cpu_data_master_requests_bl_n_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //bl_n_s1_writedata mux, which is an e_mux
  assign bl_n_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_bl_n_s1 = cpu_data_master_qualified_request_bl_n_s1;

  //cpu/data_master saved-grant bl_n/s1, which is an e_assign
  assign cpu_data_master_saved_grant_bl_n_s1 = cpu_data_master_requests_bl_n_s1;

  //allow new arb cycle for bl_n/s1, which is an e_assign
  assign bl_n_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign bl_n_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign bl_n_s1_master_qreq_vector = 1;

  //bl_n_s1_reset_n assignment, which is an e_assign
  assign bl_n_s1_reset_n = reset_n;

  assign bl_n_s1_chipselect = cpu_data_master_granted_bl_n_s1;
  //bl_n_s1_firsttransfer first transaction, which is an e_assign
  assign bl_n_s1_firsttransfer = bl_n_s1_begins_xfer ? bl_n_s1_unreg_firsttransfer : bl_n_s1_reg_firsttransfer;

  //bl_n_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign bl_n_s1_unreg_firsttransfer = ~(bl_n_s1_slavearbiterlockenable & bl_n_s1_any_continuerequest);

  //bl_n_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bl_n_s1_reg_firsttransfer <= 1'b1;
      else if (bl_n_s1_begins_xfer)
          bl_n_s1_reg_firsttransfer <= bl_n_s1_unreg_firsttransfer;
    end


  //bl_n_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign bl_n_s1_beginbursttransfer_internal = bl_n_s1_begins_xfer;

  //~bl_n_s1_write_n assignment, which is an e_mux
  assign bl_n_s1_write_n = ~(cpu_data_master_granted_bl_n_s1 & cpu_data_master_write);

  assign shifted_address_to_bl_n_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //bl_n_s1_address mux, which is an e_mux
  assign bl_n_s1_address = shifted_address_to_bl_n_s1_from_cpu_data_master >> 2;

  //d1_bl_n_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_bl_n_s1_end_xfer <= 1;
      else 
        d1_bl_n_s1_end_xfer <= bl_n_s1_end_xfer;
    end


  //bl_n_s1_waits_for_read in a cycle, which is an e_mux
  assign bl_n_s1_waits_for_read = bl_n_s1_in_a_read_cycle & bl_n_s1_begins_xfer;

  //bl_n_s1_in_a_read_cycle assignment, which is an e_assign
  assign bl_n_s1_in_a_read_cycle = cpu_data_master_granted_bl_n_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = bl_n_s1_in_a_read_cycle;

  //bl_n_s1_waits_for_write in a cycle, which is an e_mux
  assign bl_n_s1_waits_for_write = bl_n_s1_in_a_write_cycle & 0;

  //bl_n_s1_in_a_write_cycle assignment, which is an e_assign
  assign bl_n_s1_in_a_write_cycle = cpu_data_master_granted_bl_n_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = bl_n_s1_in_a_write_cycle;

  assign wait_for_bl_n_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //bl_n/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module bl_p_s1_arbitrator (
                            // inputs:
                             bl_p_s1_readdata,
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_read,
                             cpu_data_master_waitrequest,
                             cpu_data_master_write,
                             cpu_data_master_writedata,
                             reset_n,

                            // outputs:
                             bl_p_s1_address,
                             bl_p_s1_chipselect,
                             bl_p_s1_readdata_from_sa,
                             bl_p_s1_reset_n,
                             bl_p_s1_write_n,
                             bl_p_s1_writedata,
                             cpu_data_master_granted_bl_p_s1,
                             cpu_data_master_qualified_request_bl_p_s1,
                             cpu_data_master_read_data_valid_bl_p_s1,
                             cpu_data_master_requests_bl_p_s1,
                             d1_bl_p_s1_end_xfer
                          )
;

  output  [  1: 0] bl_p_s1_address;
  output           bl_p_s1_chipselect;
  output  [ 31: 0] bl_p_s1_readdata_from_sa;
  output           bl_p_s1_reset_n;
  output           bl_p_s1_write_n;
  output  [ 31: 0] bl_p_s1_writedata;
  output           cpu_data_master_granted_bl_p_s1;
  output           cpu_data_master_qualified_request_bl_p_s1;
  output           cpu_data_master_read_data_valid_bl_p_s1;
  output           cpu_data_master_requests_bl_p_s1;
  output           d1_bl_p_s1_end_xfer;
  input   [ 31: 0] bl_p_s1_readdata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] bl_p_s1_address;
  wire             bl_p_s1_allgrants;
  wire             bl_p_s1_allow_new_arb_cycle;
  wire             bl_p_s1_any_bursting_master_saved_grant;
  wire             bl_p_s1_any_continuerequest;
  wire             bl_p_s1_arb_counter_enable;
  reg     [  1: 0] bl_p_s1_arb_share_counter;
  wire    [  1: 0] bl_p_s1_arb_share_counter_next_value;
  wire    [  1: 0] bl_p_s1_arb_share_set_values;
  wire             bl_p_s1_beginbursttransfer_internal;
  wire             bl_p_s1_begins_xfer;
  wire             bl_p_s1_chipselect;
  wire             bl_p_s1_end_xfer;
  wire             bl_p_s1_firsttransfer;
  wire             bl_p_s1_grant_vector;
  wire             bl_p_s1_in_a_read_cycle;
  wire             bl_p_s1_in_a_write_cycle;
  wire             bl_p_s1_master_qreq_vector;
  wire             bl_p_s1_non_bursting_master_requests;
  wire    [ 31: 0] bl_p_s1_readdata_from_sa;
  reg              bl_p_s1_reg_firsttransfer;
  wire             bl_p_s1_reset_n;
  reg              bl_p_s1_slavearbiterlockenable;
  wire             bl_p_s1_slavearbiterlockenable2;
  wire             bl_p_s1_unreg_firsttransfer;
  wire             bl_p_s1_waits_for_read;
  wire             bl_p_s1_waits_for_write;
  wire             bl_p_s1_write_n;
  wire    [ 31: 0] bl_p_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_bl_p_s1;
  wire             cpu_data_master_qualified_request_bl_p_s1;
  wire             cpu_data_master_read_data_valid_bl_p_s1;
  wire             cpu_data_master_requests_bl_p_s1;
  wire             cpu_data_master_saved_grant_bl_p_s1;
  reg              d1_bl_p_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_bl_p_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 26: 0] shifted_address_to_bl_p_s1_from_cpu_data_master;
  wire             wait_for_bl_p_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~bl_p_s1_end_xfer;
    end


  assign bl_p_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_bl_p_s1));
  //assign bl_p_s1_readdata_from_sa = bl_p_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign bl_p_s1_readdata_from_sa = bl_p_s1_readdata;

  assign cpu_data_master_requests_bl_p_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h18a0) & (cpu_data_master_read | cpu_data_master_write);
  //bl_p_s1_arb_share_counter set values, which is an e_mux
  assign bl_p_s1_arb_share_set_values = 1;

  //bl_p_s1_non_bursting_master_requests mux, which is an e_mux
  assign bl_p_s1_non_bursting_master_requests = cpu_data_master_requests_bl_p_s1;

  //bl_p_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign bl_p_s1_any_bursting_master_saved_grant = 0;

  //bl_p_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign bl_p_s1_arb_share_counter_next_value = bl_p_s1_firsttransfer ? (bl_p_s1_arb_share_set_values - 1) : |bl_p_s1_arb_share_counter ? (bl_p_s1_arb_share_counter - 1) : 0;

  //bl_p_s1_allgrants all slave grants, which is an e_mux
  assign bl_p_s1_allgrants = |bl_p_s1_grant_vector;

  //bl_p_s1_end_xfer assignment, which is an e_assign
  assign bl_p_s1_end_xfer = ~(bl_p_s1_waits_for_read | bl_p_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_bl_p_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_bl_p_s1 = bl_p_s1_end_xfer & (~bl_p_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //bl_p_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign bl_p_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_bl_p_s1 & bl_p_s1_allgrants) | (end_xfer_arb_share_counter_term_bl_p_s1 & ~bl_p_s1_non_bursting_master_requests);

  //bl_p_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bl_p_s1_arb_share_counter <= 0;
      else if (bl_p_s1_arb_counter_enable)
          bl_p_s1_arb_share_counter <= bl_p_s1_arb_share_counter_next_value;
    end


  //bl_p_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bl_p_s1_slavearbiterlockenable <= 0;
      else if ((|bl_p_s1_master_qreq_vector & end_xfer_arb_share_counter_term_bl_p_s1) | (end_xfer_arb_share_counter_term_bl_p_s1 & ~bl_p_s1_non_bursting_master_requests))
          bl_p_s1_slavearbiterlockenable <= |bl_p_s1_arb_share_counter_next_value;
    end


  //cpu/data_master bl_p/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = bl_p_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //bl_p_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign bl_p_s1_slavearbiterlockenable2 = |bl_p_s1_arb_share_counter_next_value;

  //cpu/data_master bl_p/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = bl_p_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //bl_p_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign bl_p_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_bl_p_s1 = cpu_data_master_requests_bl_p_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //bl_p_s1_writedata mux, which is an e_mux
  assign bl_p_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_bl_p_s1 = cpu_data_master_qualified_request_bl_p_s1;

  //cpu/data_master saved-grant bl_p/s1, which is an e_assign
  assign cpu_data_master_saved_grant_bl_p_s1 = cpu_data_master_requests_bl_p_s1;

  //allow new arb cycle for bl_p/s1, which is an e_assign
  assign bl_p_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign bl_p_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign bl_p_s1_master_qreq_vector = 1;

  //bl_p_s1_reset_n assignment, which is an e_assign
  assign bl_p_s1_reset_n = reset_n;

  assign bl_p_s1_chipselect = cpu_data_master_granted_bl_p_s1;
  //bl_p_s1_firsttransfer first transaction, which is an e_assign
  assign bl_p_s1_firsttransfer = bl_p_s1_begins_xfer ? bl_p_s1_unreg_firsttransfer : bl_p_s1_reg_firsttransfer;

  //bl_p_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign bl_p_s1_unreg_firsttransfer = ~(bl_p_s1_slavearbiterlockenable & bl_p_s1_any_continuerequest);

  //bl_p_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bl_p_s1_reg_firsttransfer <= 1'b1;
      else if (bl_p_s1_begins_xfer)
          bl_p_s1_reg_firsttransfer <= bl_p_s1_unreg_firsttransfer;
    end


  //bl_p_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign bl_p_s1_beginbursttransfer_internal = bl_p_s1_begins_xfer;

  //~bl_p_s1_write_n assignment, which is an e_mux
  assign bl_p_s1_write_n = ~(cpu_data_master_granted_bl_p_s1 & cpu_data_master_write);

  assign shifted_address_to_bl_p_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //bl_p_s1_address mux, which is an e_mux
  assign bl_p_s1_address = shifted_address_to_bl_p_s1_from_cpu_data_master >> 2;

  //d1_bl_p_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_bl_p_s1_end_xfer <= 1;
      else 
        d1_bl_p_s1_end_xfer <= bl_p_s1_end_xfer;
    end


  //bl_p_s1_waits_for_read in a cycle, which is an e_mux
  assign bl_p_s1_waits_for_read = bl_p_s1_in_a_read_cycle & bl_p_s1_begins_xfer;

  //bl_p_s1_in_a_read_cycle assignment, which is an e_assign
  assign bl_p_s1_in_a_read_cycle = cpu_data_master_granted_bl_p_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = bl_p_s1_in_a_read_cycle;

  //bl_p_s1_waits_for_write in a cycle, which is an e_mux
  assign bl_p_s1_waits_for_write = bl_p_s1_in_a_write_cycle & 0;

  //bl_p_s1_in_a_write_cycle assignment, which is an e_assign
  assign bl_p_s1_in_a_write_cycle = cpu_data_master_granted_bl_p_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = bl_p_s1_in_a_write_cycle;

  assign wait_for_bl_p_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //bl_p/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_jtag_debug_module_arbitrator (
                                          // inputs:
                                           clk,
                                           cpu_data_master_address_to_slave,
                                           cpu_data_master_byteenable,
                                           cpu_data_master_debugaccess,
                                           cpu_data_master_read,
                                           cpu_data_master_waitrequest,
                                           cpu_data_master_write,
                                           cpu_data_master_writedata,
                                           cpu_instruction_master_address_to_slave,
                                           cpu_instruction_master_latency_counter,
                                           cpu_instruction_master_read,
                                           cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                                           cpu_jtag_debug_module_readdata,
                                           cpu_jtag_debug_module_resetrequest,
                                           reset_n,

                                          // outputs:
                                           cpu_data_master_granted_cpu_jtag_debug_module,
                                           cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_data_master_requests_cpu_jtag_debug_module,
                                           cpu_instruction_master_granted_cpu_jtag_debug_module,
                                           cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_instruction_master_requests_cpu_jtag_debug_module,
                                           cpu_jtag_debug_module_address,
                                           cpu_jtag_debug_module_begintransfer,
                                           cpu_jtag_debug_module_byteenable,
                                           cpu_jtag_debug_module_chipselect,
                                           cpu_jtag_debug_module_debugaccess,
                                           cpu_jtag_debug_module_readdata_from_sa,
                                           cpu_jtag_debug_module_reset_n,
                                           cpu_jtag_debug_module_resetrequest_from_sa,
                                           cpu_jtag_debug_module_write,
                                           cpu_jtag_debug_module_writedata,
                                           d1_cpu_jtag_debug_module_end_xfer
                                        )
;

  output           cpu_data_master_granted_cpu_jtag_debug_module;
  output           cpu_data_master_qualified_request_cpu_jtag_debug_module;
  output           cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  output           cpu_data_master_requests_cpu_jtag_debug_module;
  output           cpu_instruction_master_granted_cpu_jtag_debug_module;
  output           cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  output           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  output           cpu_instruction_master_requests_cpu_jtag_debug_module;
  output  [  8: 0] cpu_jtag_debug_module_address;
  output           cpu_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu_jtag_debug_module_byteenable;
  output           cpu_jtag_debug_module_chipselect;
  output           cpu_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  output           cpu_jtag_debug_module_reset_n;
  output           cpu_jtag_debug_module_resetrequest_from_sa;
  output           cpu_jtag_debug_module_write;
  output  [ 31: 0] cpu_jtag_debug_module_writedata;
  output           d1_cpu_jtag_debug_module_end_xfer;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input            cpu_data_master_debugaccess;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 26: 0] cpu_instruction_master_address_to_slave;
  input            cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  input   [ 31: 0] cpu_jtag_debug_module_readdata;
  input            cpu_jtag_debug_module_resetrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_cpu_jtag_debug_module;
  wire             cpu_data_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_data_master_requests_cpu_jtag_debug_module;
  wire             cpu_data_master_saved_grant_cpu_jtag_debug_module;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_cpu_jtag_debug_module;
  wire             cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_instruction_master_requests_cpu_jtag_debug_module;
  wire             cpu_instruction_master_saved_grant_cpu_jtag_debug_module;
  wire    [  8: 0] cpu_jtag_debug_module_address;
  wire             cpu_jtag_debug_module_allgrants;
  wire             cpu_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu_jtag_debug_module_any_bursting_master_saved_grant;
  wire             cpu_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu_jtag_debug_module_arb_addend;
  wire             cpu_jtag_debug_module_arb_counter_enable;
  reg     [  1: 0] cpu_jtag_debug_module_arb_share_counter;
  wire    [  1: 0] cpu_jtag_debug_module_arb_share_counter_next_value;
  wire    [  1: 0] cpu_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu_jtag_debug_module_arb_winner;
  wire             cpu_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu_jtag_debug_module_begins_xfer;
  wire             cpu_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_jtag_debug_module_byteenable;
  wire             cpu_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu_jtag_debug_module_chosen_master_rot_left;
  wire             cpu_jtag_debug_module_debugaccess;
  wire             cpu_jtag_debug_module_end_xfer;
  wire             cpu_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu_jtag_debug_module_grant_vector;
  wire             cpu_jtag_debug_module_in_a_read_cycle;
  wire             cpu_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu_jtag_debug_module_master_qreq_vector;
  wire             cpu_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  reg              cpu_jtag_debug_module_reg_firsttransfer;
  wire             cpu_jtag_debug_module_reset_n;
  wire             cpu_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu_jtag_debug_module_slavearbiterlockenable;
  wire             cpu_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu_jtag_debug_module_unreg_firsttransfer;
  wire             cpu_jtag_debug_module_waits_for_read;
  wire             cpu_jtag_debug_module_waits_for_write;
  wire             cpu_jtag_debug_module_write;
  wire    [ 31: 0] cpu_jtag_debug_module_writedata;
  reg              d1_cpu_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_cpu_jtag_debug_module;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
  reg              last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
  wire    [ 26: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master;
  wire    [ 26: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master;
  wire             wait_for_cpu_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~cpu_jtag_debug_module_end_xfer;
    end


  assign cpu_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cpu_jtag_debug_module | cpu_instruction_master_qualified_request_cpu_jtag_debug_module));
  //assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata;

  assign cpu_data_master_requests_cpu_jtag_debug_module = ({cpu_data_master_address_to_slave[26 : 11] , 11'b0} == 27'h1000) & (cpu_data_master_read | cpu_data_master_write);
  //cpu_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu_jtag_debug_module_arb_share_set_values = 1;

  //cpu_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu_jtag_debug_module_non_bursting_master_requests = cpu_data_master_requests_cpu_jtag_debug_module |
    cpu_instruction_master_requests_cpu_jtag_debug_module |
    cpu_data_master_requests_cpu_jtag_debug_module |
    cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  assign cpu_jtag_debug_module_any_bursting_master_saved_grant = 0;

  //cpu_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu_jtag_debug_module_arb_share_counter_next_value = cpu_jtag_debug_module_firsttransfer ? (cpu_jtag_debug_module_arb_share_set_values - 1) : |cpu_jtag_debug_module_arb_share_counter ? (cpu_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu_jtag_debug_module_allgrants = (|cpu_jtag_debug_module_grant_vector) |
    (|cpu_jtag_debug_module_grant_vector) |
    (|cpu_jtag_debug_module_grant_vector) |
    (|cpu_jtag_debug_module_grant_vector);

  //cpu_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu_jtag_debug_module_end_xfer = ~(cpu_jtag_debug_module_waits_for_read | cpu_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_jtag_debug_module arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_cpu_jtag_debug_module = cpu_jtag_debug_module_end_xfer & (~cpu_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & cpu_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests);

  //cpu_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu_jtag_debug_module_arb_counter_enable)
          cpu_jtag_debug_module_arb_share_counter <= cpu_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests))
          cpu_jtag_debug_module_slavearbiterlockenable <= |cpu_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu/data_master cpu/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_data_master_continuerequest;

  //cpu_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu_jtag_debug_module_slavearbiterlockenable2 = |cpu_jtag_debug_module_arb_share_counter_next_value;

  //cpu/data_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master cpu/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted cpu/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= 0;
      else 
        last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= cpu_instruction_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_instruction_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module & cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu_jtag_debug_module_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_cpu_jtag_debug_module = cpu_data_master_requests_cpu_jtag_debug_module & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //cpu_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu_jtag_debug_module_writedata = cpu_data_master_writedata;

  assign cpu_instruction_master_requests_cpu_jtag_debug_module = (({cpu_instruction_master_address_to_slave[26 : 11] , 11'b0} == 27'h1000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted cpu/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= 0;
      else 
        last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= cpu_data_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_data_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module & cpu_data_master_requests_cpu_jtag_debug_module;

  assign cpu_instruction_master_qualified_request_cpu_jtag_debug_module = cpu_instruction_master_requests_cpu_jtag_debug_module & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0) | (|cpu_instruction_master_read_data_valid_sdram_s1_shift_register))) | cpu_data_master_arbiterlock);
  //local readdatavalid cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux
  assign cpu_instruction_master_read_data_valid_cpu_jtag_debug_module = cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read & ~cpu_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_master_qreq_vector[0] = cpu_instruction_master_qualified_request_cpu_jtag_debug_module;

  //cpu/instruction_master grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_instruction_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[0];

  //cpu/instruction_master saved-grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_instruction_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[0] && cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu/data_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_master_qreq_vector[1] = cpu_data_master_qualified_request_cpu_jtag_debug_module;

  //cpu/data_master grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_data_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[1];

  //cpu/data_master saved-grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_data_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[1] && cpu_data_master_requests_cpu_jtag_debug_module;

  //cpu/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu_jtag_debug_module_chosen_master_double_vector = {cpu_jtag_debug_module_master_qreq_vector, cpu_jtag_debug_module_master_qreq_vector} & ({~cpu_jtag_debug_module_master_qreq_vector, ~cpu_jtag_debug_module_master_qreq_vector} + cpu_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu_jtag_debug_module_arb_winner = (cpu_jtag_debug_module_allow_new_arb_cycle & | cpu_jtag_debug_module_grant_vector) ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu_jtag_debug_module_allow_new_arb_cycle)
          cpu_jtag_debug_module_saved_chosen_master_vector <= |cpu_jtag_debug_module_grant_vector ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu_jtag_debug_module_grant_vector = {(cpu_jtag_debug_module_chosen_master_double_vector[1] | cpu_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu_jtag_debug_module_chosen_master_double_vector[0] | cpu_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu_jtag_debug_module_chosen_master_rot_left = (cpu_jtag_debug_module_arb_winner << 1) ? (cpu_jtag_debug_module_arb_winner << 1) : 1;

  //cpu/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_arb_addend <= 1;
      else if (|cpu_jtag_debug_module_grant_vector)
          cpu_jtag_debug_module_arb_addend <= cpu_jtag_debug_module_end_xfer? cpu_jtag_debug_module_chosen_master_rot_left : cpu_jtag_debug_module_grant_vector;
    end


  assign cpu_jtag_debug_module_begintransfer = cpu_jtag_debug_module_begins_xfer;
  //cpu_jtag_debug_module_reset_n assignment, which is an e_assign
  assign cpu_jtag_debug_module_reset_n = reset_n;

  //assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest;

  assign cpu_jtag_debug_module_chipselect = cpu_data_master_granted_cpu_jtag_debug_module | cpu_instruction_master_granted_cpu_jtag_debug_module;
  //cpu_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu_jtag_debug_module_firsttransfer = cpu_jtag_debug_module_begins_xfer ? cpu_jtag_debug_module_unreg_firsttransfer : cpu_jtag_debug_module_reg_firsttransfer;

  //cpu_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
  assign cpu_jtag_debug_module_unreg_firsttransfer = ~(cpu_jtag_debug_module_slavearbiterlockenable & cpu_jtag_debug_module_any_continuerequest);

  //cpu_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_reg_firsttransfer <= 1'b1;
      else if (cpu_jtag_debug_module_begins_xfer)
          cpu_jtag_debug_module_reg_firsttransfer <= cpu_jtag_debug_module_unreg_firsttransfer;
    end


  //cpu_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_jtag_debug_module_beginbursttransfer_internal = cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_jtag_debug_module_arbitration_holdoff_internal = cpu_jtag_debug_module_begins_xfer & cpu_jtag_debug_module_firsttransfer;

  //cpu_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_jtag_debug_module_write = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  assign shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master = cpu_data_master_address_to_slave;
  //cpu_jtag_debug_module_address mux, which is an e_mux
  assign cpu_jtag_debug_module_address = (cpu_data_master_granted_cpu_jtag_debug_module)? (shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master >> 2) :
    (shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master >> 2);

  assign shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
  //d1_cpu_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_jtag_debug_module_end_xfer <= 1;
      else 
        d1_cpu_jtag_debug_module_end_xfer <= cpu_jtag_debug_module_end_xfer;
    end


  //cpu_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_read = cpu_jtag_debug_module_in_a_read_cycle & cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_read_cycle = (cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read) | (cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_jtag_debug_module_in_a_read_cycle;

  //cpu_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_write = cpu_jtag_debug_module_in_a_write_cycle & 0;

  //cpu_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_write_cycle = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_jtag_debug_module_counter = 0;
  //cpu_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_jtag_debug_module_byteenable = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_byteenable :
    -1;

  //debugaccess mux, which is an e_mux
  assign cpu_jtag_debug_module_debugaccess = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu/jtag_debug_module enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_cpu_jtag_debug_module + cpu_instruction_master_granted_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_cpu_jtag_debug_module + cpu_instruction_master_saved_grant_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_data_master_arbitrator (
                                    // inputs:
                                     bl_n_s1_readdata_from_sa,
                                     bl_p_s1_readdata_from_sa,
                                     clk,
                                     cpu_data_master_address,
                                     cpu_data_master_byteenable_sdram_s1,
                                     cpu_data_master_granted_bl_n_s1,
                                     cpu_data_master_granted_bl_p_s1,
                                     cpu_data_master_granted_cpu_jtag_debug_module,
                                     cpu_data_master_granted_epcs_epcs_control_port,
                                     cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_granted_lcd32_data_s1,
                                     cpu_data_master_granted_lcd_cs_s1,
                                     cpu_data_master_granted_lcd_rd_s1,
                                     cpu_data_master_granted_lcd_rs_s1,
                                     cpu_data_master_granted_lcd_wr_s1,
                                     cpu_data_master_granted_reset_s1,
                                     cpu_data_master_granted_sdram_s1,
                                     cpu_data_master_granted_spi_touch_spi_control_port,
                                     cpu_data_master_granted_sysid_control_slave,
                                     cpu_data_master_granted_touch_cs_s1,
                                     cpu_data_master_granted_touch_irq_s1,
                                     cpu_data_master_qualified_request_bl_n_s1,
                                     cpu_data_master_qualified_request_bl_p_s1,
                                     cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                     cpu_data_master_qualified_request_epcs_epcs_control_port,
                                     cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_qualified_request_lcd32_data_s1,
                                     cpu_data_master_qualified_request_lcd_cs_s1,
                                     cpu_data_master_qualified_request_lcd_rd_s1,
                                     cpu_data_master_qualified_request_lcd_rs_s1,
                                     cpu_data_master_qualified_request_lcd_wr_s1,
                                     cpu_data_master_qualified_request_reset_s1,
                                     cpu_data_master_qualified_request_sdram_s1,
                                     cpu_data_master_qualified_request_spi_touch_spi_control_port,
                                     cpu_data_master_qualified_request_sysid_control_slave,
                                     cpu_data_master_qualified_request_touch_cs_s1,
                                     cpu_data_master_qualified_request_touch_irq_s1,
                                     cpu_data_master_read,
                                     cpu_data_master_read_data_valid_bl_n_s1,
                                     cpu_data_master_read_data_valid_bl_p_s1,
                                     cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                     cpu_data_master_read_data_valid_epcs_epcs_control_port,
                                     cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_read_data_valid_lcd32_data_s1,
                                     cpu_data_master_read_data_valid_lcd_cs_s1,
                                     cpu_data_master_read_data_valid_lcd_rd_s1,
                                     cpu_data_master_read_data_valid_lcd_rs_s1,
                                     cpu_data_master_read_data_valid_lcd_wr_s1,
                                     cpu_data_master_read_data_valid_reset_s1,
                                     cpu_data_master_read_data_valid_sdram_s1,
                                     cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                     cpu_data_master_read_data_valid_spi_touch_spi_control_port,
                                     cpu_data_master_read_data_valid_sysid_control_slave,
                                     cpu_data_master_read_data_valid_touch_cs_s1,
                                     cpu_data_master_read_data_valid_touch_irq_s1,
                                     cpu_data_master_requests_bl_n_s1,
                                     cpu_data_master_requests_bl_p_s1,
                                     cpu_data_master_requests_cpu_jtag_debug_module,
                                     cpu_data_master_requests_epcs_epcs_control_port,
                                     cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_requests_lcd32_data_s1,
                                     cpu_data_master_requests_lcd_cs_s1,
                                     cpu_data_master_requests_lcd_rd_s1,
                                     cpu_data_master_requests_lcd_rs_s1,
                                     cpu_data_master_requests_lcd_wr_s1,
                                     cpu_data_master_requests_reset_s1,
                                     cpu_data_master_requests_sdram_s1,
                                     cpu_data_master_requests_spi_touch_spi_control_port,
                                     cpu_data_master_requests_sysid_control_slave,
                                     cpu_data_master_requests_touch_cs_s1,
                                     cpu_data_master_requests_touch_irq_s1,
                                     cpu_data_master_write,
                                     cpu_data_master_writedata,
                                     cpu_jtag_debug_module_readdata_from_sa,
                                     d1_bl_n_s1_end_xfer,
                                     d1_bl_p_s1_end_xfer,
                                     d1_cpu_jtag_debug_module_end_xfer,
                                     d1_epcs_epcs_control_port_end_xfer,
                                     d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                     d1_lcd32_data_s1_end_xfer,
                                     d1_lcd_cs_s1_end_xfer,
                                     d1_lcd_rd_s1_end_xfer,
                                     d1_lcd_rs_s1_end_xfer,
                                     d1_lcd_wr_s1_end_xfer,
                                     d1_reset_s1_end_xfer,
                                     d1_sdram_s1_end_xfer,
                                     d1_spi_touch_spi_control_port_end_xfer,
                                     d1_sysid_control_slave_end_xfer,
                                     d1_touch_cs_s1_end_xfer,
                                     d1_touch_irq_s1_end_xfer,
                                     epcs_epcs_control_port_irq_from_sa,
                                     epcs_epcs_control_port_readdata_from_sa,
                                     jtag_uart_avalon_jtag_slave_irq_from_sa,
                                     jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                     jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                     lcd32_data_s1_readdata_from_sa,
                                     lcd_cs_s1_readdata_from_sa,
                                     lcd_rd_s1_readdata_from_sa,
                                     lcd_rs_s1_readdata_from_sa,
                                     lcd_wr_s1_readdata_from_sa,
                                     reset_n,
                                     reset_s1_readdata_from_sa,
                                     sdram_s1_readdata_from_sa,
                                     sdram_s1_waitrequest_from_sa,
                                     spi_touch_spi_control_port_irq_from_sa,
                                     spi_touch_spi_control_port_readdata_from_sa,
                                     sysid_control_slave_readdata_from_sa,
                                     touch_cs_s1_readdata_from_sa,
                                     touch_irq_s1_readdata_from_sa,

                                    // outputs:
                                     cpu_data_master_address_to_slave,
                                     cpu_data_master_dbs_address,
                                     cpu_data_master_dbs_write_16,
                                     cpu_data_master_irq,
                                     cpu_data_master_no_byte_enables_and_last_term,
                                     cpu_data_master_readdata,
                                     cpu_data_master_waitrequest
                                  )
;

  output  [ 26: 0] cpu_data_master_address_to_slave;
  output  [  1: 0] cpu_data_master_dbs_address;
  output  [ 15: 0] cpu_data_master_dbs_write_16;
  output  [ 31: 0] cpu_data_master_irq;
  output           cpu_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu_data_master_readdata;
  output           cpu_data_master_waitrequest;
  input   [ 31: 0] bl_n_s1_readdata_from_sa;
  input   [ 31: 0] bl_p_s1_readdata_from_sa;
  input            clk;
  input   [ 26: 0] cpu_data_master_address;
  input   [  1: 0] cpu_data_master_byteenable_sdram_s1;
  input            cpu_data_master_granted_bl_n_s1;
  input            cpu_data_master_granted_bl_p_s1;
  input            cpu_data_master_granted_cpu_jtag_debug_module;
  input            cpu_data_master_granted_epcs_epcs_control_port;
  input            cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_granted_lcd32_data_s1;
  input            cpu_data_master_granted_lcd_cs_s1;
  input            cpu_data_master_granted_lcd_rd_s1;
  input            cpu_data_master_granted_lcd_rs_s1;
  input            cpu_data_master_granted_lcd_wr_s1;
  input            cpu_data_master_granted_reset_s1;
  input            cpu_data_master_granted_sdram_s1;
  input            cpu_data_master_granted_spi_touch_spi_control_port;
  input            cpu_data_master_granted_sysid_control_slave;
  input            cpu_data_master_granted_touch_cs_s1;
  input            cpu_data_master_granted_touch_irq_s1;
  input            cpu_data_master_qualified_request_bl_n_s1;
  input            cpu_data_master_qualified_request_bl_p_s1;
  input            cpu_data_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_data_master_qualified_request_epcs_epcs_control_port;
  input            cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_qualified_request_lcd32_data_s1;
  input            cpu_data_master_qualified_request_lcd_cs_s1;
  input            cpu_data_master_qualified_request_lcd_rd_s1;
  input            cpu_data_master_qualified_request_lcd_rs_s1;
  input            cpu_data_master_qualified_request_lcd_wr_s1;
  input            cpu_data_master_qualified_request_reset_s1;
  input            cpu_data_master_qualified_request_sdram_s1;
  input            cpu_data_master_qualified_request_spi_touch_spi_control_port;
  input            cpu_data_master_qualified_request_sysid_control_slave;
  input            cpu_data_master_qualified_request_touch_cs_s1;
  input            cpu_data_master_qualified_request_touch_irq_s1;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_bl_n_s1;
  input            cpu_data_master_read_data_valid_bl_p_s1;
  input            cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_data_master_read_data_valid_epcs_epcs_control_port;
  input            cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_read_data_valid_lcd32_data_s1;
  input            cpu_data_master_read_data_valid_lcd_cs_s1;
  input            cpu_data_master_read_data_valid_lcd_rd_s1;
  input            cpu_data_master_read_data_valid_lcd_rs_s1;
  input            cpu_data_master_read_data_valid_lcd_wr_s1;
  input            cpu_data_master_read_data_valid_reset_s1;
  input            cpu_data_master_read_data_valid_sdram_s1;
  input            cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_read_data_valid_spi_touch_spi_control_port;
  input            cpu_data_master_read_data_valid_sysid_control_slave;
  input            cpu_data_master_read_data_valid_touch_cs_s1;
  input            cpu_data_master_read_data_valid_touch_irq_s1;
  input            cpu_data_master_requests_bl_n_s1;
  input            cpu_data_master_requests_bl_p_s1;
  input            cpu_data_master_requests_cpu_jtag_debug_module;
  input            cpu_data_master_requests_epcs_epcs_control_port;
  input            cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_requests_lcd32_data_s1;
  input            cpu_data_master_requests_lcd_cs_s1;
  input            cpu_data_master_requests_lcd_rd_s1;
  input            cpu_data_master_requests_lcd_rs_s1;
  input            cpu_data_master_requests_lcd_wr_s1;
  input            cpu_data_master_requests_reset_s1;
  input            cpu_data_master_requests_sdram_s1;
  input            cpu_data_master_requests_spi_touch_spi_control_port;
  input            cpu_data_master_requests_sysid_control_slave;
  input            cpu_data_master_requests_touch_cs_s1;
  input            cpu_data_master_requests_touch_irq_s1;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_bl_n_s1_end_xfer;
  input            d1_bl_p_s1_end_xfer;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_epcs_epcs_control_port_end_xfer;
  input            d1_jtag_uart_avalon_jtag_slave_end_xfer;
  input            d1_lcd32_data_s1_end_xfer;
  input            d1_lcd_cs_s1_end_xfer;
  input            d1_lcd_rd_s1_end_xfer;
  input            d1_lcd_rs_s1_end_xfer;
  input            d1_lcd_wr_s1_end_xfer;
  input            d1_reset_s1_end_xfer;
  input            d1_sdram_s1_end_xfer;
  input            d1_spi_touch_spi_control_port_end_xfer;
  input            d1_sysid_control_slave_end_xfer;
  input            d1_touch_cs_s1_end_xfer;
  input            d1_touch_irq_s1_end_xfer;
  input            epcs_epcs_control_port_irq_from_sa;
  input   [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  input   [ 31: 0] lcd32_data_s1_readdata_from_sa;
  input   [ 31: 0] lcd_cs_s1_readdata_from_sa;
  input   [ 31: 0] lcd_rd_s1_readdata_from_sa;
  input   [ 31: 0] lcd_rs_s1_readdata_from_sa;
  input   [ 31: 0] lcd_wr_s1_readdata_from_sa;
  input            reset_n;
  input   [ 31: 0] reset_s1_readdata_from_sa;
  input   [ 15: 0] sdram_s1_readdata_from_sa;
  input            sdram_s1_waitrequest_from_sa;
  input            spi_touch_spi_control_port_irq_from_sa;
  input   [ 15: 0] spi_touch_spi_control_port_readdata_from_sa;
  input   [ 31: 0] sysid_control_slave_readdata_from_sa;
  input   [ 31: 0] touch_cs_s1_readdata_from_sa;
  input   [ 31: 0] touch_irq_s1_readdata_from_sa;

  wire    [ 26: 0] cpu_data_master_address_to_slave;
  reg     [  1: 0] cpu_data_master_dbs_address;
  wire    [  1: 0] cpu_data_master_dbs_increment;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_data_master_irq;
  reg              cpu_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_run;
  reg              cpu_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [ 31: 0] p1_registered_cpu_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  wire             r_3;
  reg     [ 31: 0] registered_cpu_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_data_master_qualified_request_bl_n_s1 | ~cpu_data_master_requests_bl_n_s1) & ((~cpu_data_master_qualified_request_bl_n_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_bl_n_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_bl_p_s1 | ~cpu_data_master_requests_bl_p_s1) & ((~cpu_data_master_qualified_request_bl_p_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_bl_p_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_requests_cpu_jtag_debug_module) & (cpu_data_master_granted_cpu_jtag_debug_module | ~cpu_data_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_epcs_epcs_control_port | ~cpu_data_master_requests_epcs_epcs_control_port) & (cpu_data_master_granted_epcs_epcs_control_port | ~cpu_data_master_qualified_request_epcs_epcs_control_port) & ((~cpu_data_master_qualified_request_epcs_epcs_control_port | ~(cpu_data_master_read | cpu_data_master_write) | (1 & 1 & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_epcs_epcs_control_port | ~(cpu_data_master_read | cpu_data_master_write) | (1 & 1 & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

  //cascaded wait assignment, which is an e_assign
  assign cpu_data_master_run = r_0 & r_1 & r_2 & r_3;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_lcd32_data_s1 | ~cpu_data_master_requests_lcd32_data_s1) & ((~cpu_data_master_qualified_request_lcd32_data_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_lcd32_data_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_lcd_cs_s1 | ~cpu_data_master_requests_lcd_cs_s1) & ((~cpu_data_master_qualified_request_lcd_cs_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_lcd_cs_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_lcd_rd_s1 | ~cpu_data_master_requests_lcd_rd_s1) & ((~cpu_data_master_qualified_request_lcd_rd_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_lcd_rd_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_lcd_rs_s1 | ~cpu_data_master_requests_lcd_rs_s1) & ((~cpu_data_master_qualified_request_lcd_rs_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_lcd_rs_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_lcd_wr_s1 | ~cpu_data_master_requests_lcd_wr_s1);

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = ((~cpu_data_master_qualified_request_lcd_wr_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_lcd_wr_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_reset_s1 | ~cpu_data_master_requests_reset_s1) & ((~cpu_data_master_qualified_request_reset_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_reset_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_sdram_s1 | (cpu_data_master_read_data_valid_sdram_s1 & cpu_data_master_dbs_address[1]) | (cpu_data_master_write & !cpu_data_master_byteenable_sdram_s1 & cpu_data_master_dbs_address[1]) | ~cpu_data_master_requests_sdram_s1) & (cpu_data_master_granted_sdram_s1 | ~cpu_data_master_qualified_request_sdram_s1) & ((~cpu_data_master_qualified_request_sdram_s1 | ~cpu_data_master_read | (cpu_data_master_read_data_valid_sdram_s1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sdram_s1 | ~cpu_data_master_write | (1 & ~sdram_s1_waitrequest_from_sa & (cpu_data_master_dbs_address[1]) & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_spi_touch_spi_control_port | ~(cpu_data_master_read | cpu_data_master_write) | (1 & 1 & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_spi_touch_spi_control_port | ~(cpu_data_master_read | cpu_data_master_write) | (1 & 1 & (cpu_data_master_read | cpu_data_master_write)))) & 1 & ((~cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_touch_cs_s1 | ~cpu_data_master_requests_touch_cs_s1) & ((~cpu_data_master_qualified_request_touch_cs_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read)));

  //r_3 master_run cascaded wait assignment, which is an e_assign
  assign r_3 = ((~cpu_data_master_qualified_request_touch_cs_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_touch_irq_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_touch_irq_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_data_master_address_to_slave = {cpu_data_master_address[26],
    1'b0,
    cpu_data_master_address[24 : 0]};

  //cpu/data_master readdata mux, which is an e_mux
  assign cpu_data_master_readdata = ({32 {~cpu_data_master_requests_bl_n_s1}} | bl_n_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_bl_p_s1}} | bl_p_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_cpu_jtag_debug_module}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_epcs_epcs_control_port}} | epcs_epcs_control_port_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | registered_cpu_data_master_readdata) &
    ({32 {~cpu_data_master_requests_lcd32_data_s1}} | lcd32_data_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_lcd_cs_s1}} | lcd_cs_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_lcd_rd_s1}} | lcd_rd_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_lcd_rs_s1}} | lcd_rs_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_lcd_wr_s1}} | lcd_wr_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_reset_s1}} | reset_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_sdram_s1}} | registered_cpu_data_master_readdata) &
    ({32 {~cpu_data_master_requests_spi_touch_spi_control_port}} | spi_touch_spi_control_port_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_sysid_control_slave}} | sysid_control_slave_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_touch_cs_s1}} | touch_cs_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_touch_irq_s1}} | touch_irq_s1_readdata_from_sa);

  //actual waitrequest port, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_waitrequest <= ~0;
      else 
        cpu_data_master_waitrequest <= ~((~(cpu_data_master_read | cpu_data_master_write))? 0: (cpu_data_master_run & cpu_data_master_waitrequest));
    end


  //irq assign, which is an e_assign
  assign cpu_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    spi_touch_spi_control_port_irq_from_sa,
    jtag_uart_avalon_jtag_slave_irq_from_sa,
    epcs_epcs_control_port_irq_from_sa};

  //unpredictable registered wait state incoming data, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          registered_cpu_data_master_readdata <= 0;
      else 
        registered_cpu_data_master_readdata <= p1_registered_cpu_data_master_readdata;
    end


  //registered readdata mux, which is an e_mux
  assign p1_registered_cpu_data_master_readdata = ({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | jtag_uart_avalon_jtag_slave_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_sdram_s1}} | {sdram_s1_readdata_from_sa[15 : 0],
    dbs_16_reg_segment_0});

  //no_byte_enables_and_last_term, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_no_byte_enables_and_last_term <= 0;
      else 
        cpu_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
    end


  //compute the last dbs term, which is an e_mux
  assign last_dbs_term_and_run = (cpu_data_master_dbs_address == 2'b10) & cpu_data_master_write & !cpu_data_master_byteenable_sdram_s1;

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (((~cpu_data_master_no_byte_enables_and_last_term) & cpu_data_master_requests_sdram_s1 & cpu_data_master_write & !cpu_data_master_byteenable_sdram_s1)) |
    cpu_data_master_read_data_valid_sdram_s1 |
    (cpu_data_master_granted_sdram_s1 & cpu_data_master_write & 1 & 1 & ~sdram_s1_waitrequest_from_sa);

  //input to dbs-16 stored 0, which is an e_mux
  assign p1_dbs_16_reg_segment_0 = sdram_s1_readdata_from_sa;

  //dbs register for dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_16_reg_segment_0 <= 0;
      else if (dbs_count_enable & ((cpu_data_master_dbs_address[1]) == 0))
          dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
    end


  //mux write dbs 1, which is an e_mux
  assign cpu_data_master_dbs_write_16 = (cpu_data_master_dbs_address[1])? cpu_data_master_writedata[31 : 16] :
    cpu_data_master_writedata[15 : 0];

  //dbs count increment, which is an e_mux
  assign cpu_data_master_dbs_increment = (cpu_data_master_requests_sdram_s1)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_data_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_data_master_dbs_address + cpu_data_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable &
    (~(cpu_data_master_requests_sdram_s1 & ~cpu_data_master_waitrequest));

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_data_master_dbs_address <= next_dbs_address;
    end



endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_instruction_master_arbitrator (
                                           // inputs:
                                            clk,
                                            cpu_instruction_master_address,
                                            cpu_instruction_master_granted_cpu_jtag_debug_module,
                                            cpu_instruction_master_granted_epcs_epcs_control_port,
                                            cpu_instruction_master_granted_sdram_s1,
                                            cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                            cpu_instruction_master_qualified_request_epcs_epcs_control_port,
                                            cpu_instruction_master_qualified_request_sdram_s1,
                                            cpu_instruction_master_read,
                                            cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                            cpu_instruction_master_read_data_valid_epcs_epcs_control_port,
                                            cpu_instruction_master_read_data_valid_sdram_s1,
                                            cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                                            cpu_instruction_master_requests_cpu_jtag_debug_module,
                                            cpu_instruction_master_requests_epcs_epcs_control_port,
                                            cpu_instruction_master_requests_sdram_s1,
                                            cpu_jtag_debug_module_readdata_from_sa,
                                            d1_cpu_jtag_debug_module_end_xfer,
                                            d1_epcs_epcs_control_port_end_xfer,
                                            d1_sdram_s1_end_xfer,
                                            epcs_epcs_control_port_readdata_from_sa,
                                            reset_n,
                                            sdram_s1_readdata_from_sa,
                                            sdram_s1_waitrequest_from_sa,

                                           // outputs:
                                            cpu_instruction_master_address_to_slave,
                                            cpu_instruction_master_dbs_address,
                                            cpu_instruction_master_latency_counter,
                                            cpu_instruction_master_readdata,
                                            cpu_instruction_master_readdatavalid,
                                            cpu_instruction_master_waitrequest
                                         )
;

  output  [ 26: 0] cpu_instruction_master_address_to_slave;
  output  [  1: 0] cpu_instruction_master_dbs_address;
  output           cpu_instruction_master_latency_counter;
  output  [ 31: 0] cpu_instruction_master_readdata;
  output           cpu_instruction_master_readdatavalid;
  output           cpu_instruction_master_waitrequest;
  input            clk;
  input   [ 26: 0] cpu_instruction_master_address;
  input            cpu_instruction_master_granted_cpu_jtag_debug_module;
  input            cpu_instruction_master_granted_epcs_epcs_control_port;
  input            cpu_instruction_master_granted_sdram_s1;
  input            cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_instruction_master_qualified_request_epcs_epcs_control_port;
  input            cpu_instruction_master_qualified_request_sdram_s1;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_instruction_master_read_data_valid_epcs_epcs_control_port;
  input            cpu_instruction_master_read_data_valid_sdram_s1;
  input            cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_instruction_master_requests_cpu_jtag_debug_module;
  input            cpu_instruction_master_requests_epcs_epcs_control_port;
  input            cpu_instruction_master_requests_sdram_s1;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_epcs_epcs_control_port_end_xfer;
  input            d1_sdram_s1_end_xfer;
  input   [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
  input            reset_n;
  input   [ 15: 0] sdram_s1_readdata_from_sa;
  input            sdram_s1_waitrequest_from_sa;

  reg              active_and_waiting_last_time;
  reg     [ 26: 0] cpu_instruction_master_address_last_time;
  wire    [ 26: 0] cpu_instruction_master_address_to_slave;
  reg     [  1: 0] cpu_instruction_master_dbs_address;
  wire    [  1: 0] cpu_instruction_master_dbs_increment;
  reg     [  1: 0] cpu_instruction_master_dbs_rdv_counter;
  wire    [  1: 0] cpu_instruction_master_dbs_rdv_counter_inc;
  wire             cpu_instruction_master_is_granted_some_slave;
  reg              cpu_instruction_master_latency_counter;
  wire    [  1: 0] cpu_instruction_master_next_dbs_rdv_counter;
  reg              cpu_instruction_master_read_but_no_slave_selected;
  reg              cpu_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_instruction_master_readdata;
  wire             cpu_instruction_master_readdatavalid;
  wire             cpu_instruction_master_run;
  wire             cpu_instruction_master_waitrequest;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  reg     [ 15: 0] dbs_latent_16_reg_segment_0;
  wire             dbs_rdv_count_enable;
  wire             dbs_rdv_counter_overflow;
  wire             latency_load_value;
  wire    [  1: 0] next_dbs_address;
  wire             p1_cpu_instruction_master_latency_counter;
  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;
  wire             pre_dbs_count_enable;
  wire             pre_flush_cpu_instruction_master_readdatavalid;
  wire             r_0;
  wire             r_2;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_requests_cpu_jtag_debug_module) & (cpu_instruction_master_granted_cpu_jtag_debug_module | ~cpu_instruction_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_read | (1 & ~d1_cpu_jtag_debug_module_end_xfer & cpu_instruction_master_read))) & 1 & (cpu_instruction_master_qualified_request_epcs_epcs_control_port | ~cpu_instruction_master_requests_epcs_epcs_control_port) & (cpu_instruction_master_granted_epcs_epcs_control_port | ~cpu_instruction_master_qualified_request_epcs_epcs_control_port) & ((~cpu_instruction_master_qualified_request_epcs_epcs_control_port | ~(cpu_instruction_master_read) | (1 & ~d1_epcs_epcs_control_port_end_xfer & (cpu_instruction_master_read))));

  //cascaded wait assignment, which is an e_assign
  assign cpu_instruction_master_run = r_0 & r_2;

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = 1 & (cpu_instruction_master_qualified_request_sdram_s1 | ~cpu_instruction_master_requests_sdram_s1) & (cpu_instruction_master_granted_sdram_s1 | ~cpu_instruction_master_qualified_request_sdram_s1) & ((~cpu_instruction_master_qualified_request_sdram_s1 | ~cpu_instruction_master_read | (1 & ~sdram_s1_waitrequest_from_sa & (cpu_instruction_master_dbs_address[1]) & cpu_instruction_master_read)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_instruction_master_address_to_slave = {cpu_instruction_master_address[26],
    1'b0,
    cpu_instruction_master_address[24 : 0]};

  //cpu_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_but_no_slave_selected <= 0;
      else 
        cpu_instruction_master_read_but_no_slave_selected <= cpu_instruction_master_read & cpu_instruction_master_run & ~cpu_instruction_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_instruction_master_is_granted_some_slave = cpu_instruction_master_granted_cpu_jtag_debug_module |
    cpu_instruction_master_granted_epcs_epcs_control_port |
    cpu_instruction_master_granted_sdram_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_instruction_master_readdatavalid = cpu_instruction_master_read_data_valid_sdram_s1 & dbs_rdv_counter_overflow;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_instruction_master_readdatavalid = cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid |
    cpu_instruction_master_read_data_valid_cpu_jtag_debug_module |
    cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid |
    cpu_instruction_master_read_data_valid_epcs_epcs_control_port |
    cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid;

  //cpu/instruction_master readdata mux, which is an e_mux
  assign cpu_instruction_master_readdata = ({32 {~(cpu_instruction_master_qualified_request_cpu_jtag_debug_module & cpu_instruction_master_read)}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~(cpu_instruction_master_qualified_request_epcs_epcs_control_port & cpu_instruction_master_read)}} | epcs_epcs_control_port_readdata_from_sa) &
    ({32 {~cpu_instruction_master_read_data_valid_sdram_s1}} | {sdram_s1_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0});

  //actual waitrequest port, which is an e_assign
  assign cpu_instruction_master_waitrequest = ~cpu_instruction_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_latency_counter <= 0;
      else 
        cpu_instruction_master_latency_counter <= p1_cpu_instruction_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_instruction_master_latency_counter = ((cpu_instruction_master_run & cpu_instruction_master_read))? latency_load_value :
    (cpu_instruction_master_latency_counter)? cpu_instruction_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //input to latent dbs-16 stored 0, which is an e_mux
  assign p1_dbs_latent_16_reg_segment_0 = sdram_s1_readdata_from_sa;

  //dbs register for latent dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_16_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1]) == 0))
          dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
    end


  //dbs count increment, which is an e_mux
  assign cpu_instruction_master_dbs_increment = (cpu_instruction_master_requests_sdram_s1)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_instruction_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_instruction_master_dbs_address + cpu_instruction_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_instruction_master_dbs_address <= next_dbs_address;
    end


  //p1 dbs rdv counter, which is an e_assign
  assign cpu_instruction_master_next_dbs_rdv_counter = cpu_instruction_master_dbs_rdv_counter + cpu_instruction_master_dbs_rdv_counter_inc;

  //cpu_instruction_master_rdv_inc_mux, which is an e_mux
  assign cpu_instruction_master_dbs_rdv_counter_inc = 2;

  //master any slave rdv, which is an e_mux
  assign dbs_rdv_count_enable = cpu_instruction_master_read_data_valid_sdram_s1;

  //dbs rdv counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_dbs_rdv_counter <= 0;
      else if (dbs_rdv_count_enable)
          cpu_instruction_master_dbs_rdv_counter <= cpu_instruction_master_next_dbs_rdv_counter;
    end


  //dbs rdv counter overflow, which is an e_assign
  assign dbs_rdv_counter_overflow = cpu_instruction_master_dbs_rdv_counter[1] & ~cpu_instruction_master_next_dbs_rdv_counter[1];

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = cpu_instruction_master_granted_sdram_s1 & cpu_instruction_master_read & 1 & 1 & ~sdram_s1_waitrequest_from_sa;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_address_last_time <= 0;
      else 
        cpu_instruction_master_address_last_time <= cpu_instruction_master_address;
    end


  //cpu/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= cpu_instruction_master_waitrequest & (cpu_instruction_master_read);
    end


  //cpu_instruction_master_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_instruction_master_address != cpu_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_last_time <= 0;
      else 
        cpu_instruction_master_read_last_time <= cpu_instruction_master_read;
    end


  //cpu_instruction_master_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_instruction_master_read != cpu_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module epcs_epcs_control_port_arbitrator (
                                           // inputs:
                                            clk,
                                            cpu_data_master_address_to_slave,
                                            cpu_data_master_read,
                                            cpu_data_master_write,
                                            cpu_data_master_writedata,
                                            cpu_instruction_master_address_to_slave,
                                            cpu_instruction_master_latency_counter,
                                            cpu_instruction_master_read,
                                            cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                                            epcs_epcs_control_port_dataavailable,
                                            epcs_epcs_control_port_endofpacket,
                                            epcs_epcs_control_port_irq,
                                            epcs_epcs_control_port_readdata,
                                            epcs_epcs_control_port_readyfordata,
                                            reset_n,

                                           // outputs:
                                            cpu_data_master_granted_epcs_epcs_control_port,
                                            cpu_data_master_qualified_request_epcs_epcs_control_port,
                                            cpu_data_master_read_data_valid_epcs_epcs_control_port,
                                            cpu_data_master_requests_epcs_epcs_control_port,
                                            cpu_instruction_master_granted_epcs_epcs_control_port,
                                            cpu_instruction_master_qualified_request_epcs_epcs_control_port,
                                            cpu_instruction_master_read_data_valid_epcs_epcs_control_port,
                                            cpu_instruction_master_requests_epcs_epcs_control_port,
                                            d1_epcs_epcs_control_port_end_xfer,
                                            epcs_epcs_control_port_address,
                                            epcs_epcs_control_port_chipselect,
                                            epcs_epcs_control_port_dataavailable_from_sa,
                                            epcs_epcs_control_port_endofpacket_from_sa,
                                            epcs_epcs_control_port_irq_from_sa,
                                            epcs_epcs_control_port_read_n,
                                            epcs_epcs_control_port_readdata_from_sa,
                                            epcs_epcs_control_port_readyfordata_from_sa,
                                            epcs_epcs_control_port_reset_n,
                                            epcs_epcs_control_port_write_n,
                                            epcs_epcs_control_port_writedata
                                         )
;

  output           cpu_data_master_granted_epcs_epcs_control_port;
  output           cpu_data_master_qualified_request_epcs_epcs_control_port;
  output           cpu_data_master_read_data_valid_epcs_epcs_control_port;
  output           cpu_data_master_requests_epcs_epcs_control_port;
  output           cpu_instruction_master_granted_epcs_epcs_control_port;
  output           cpu_instruction_master_qualified_request_epcs_epcs_control_port;
  output           cpu_instruction_master_read_data_valid_epcs_epcs_control_port;
  output           cpu_instruction_master_requests_epcs_epcs_control_port;
  output           d1_epcs_epcs_control_port_end_xfer;
  output  [  8: 0] epcs_epcs_control_port_address;
  output           epcs_epcs_control_port_chipselect;
  output           epcs_epcs_control_port_dataavailable_from_sa;
  output           epcs_epcs_control_port_endofpacket_from_sa;
  output           epcs_epcs_control_port_irq_from_sa;
  output           epcs_epcs_control_port_read_n;
  output  [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
  output           epcs_epcs_control_port_readyfordata_from_sa;
  output           epcs_epcs_control_port_reset_n;
  output           epcs_epcs_control_port_write_n;
  output  [ 31: 0] epcs_epcs_control_port_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 26: 0] cpu_instruction_master_address_to_slave;
  input            cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  input            epcs_epcs_control_port_dataavailable;
  input            epcs_epcs_control_port_endofpacket;
  input            epcs_epcs_control_port_irq;
  input   [ 31: 0] epcs_epcs_control_port_readdata;
  input            epcs_epcs_control_port_readyfordata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_epcs_epcs_control_port;
  wire             cpu_data_master_qualified_request_epcs_epcs_control_port;
  wire             cpu_data_master_read_data_valid_epcs_epcs_control_port;
  wire             cpu_data_master_requests_epcs_epcs_control_port;
  wire             cpu_data_master_saved_grant_epcs_epcs_control_port;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_epcs_epcs_control_port;
  wire             cpu_instruction_master_qualified_request_epcs_epcs_control_port;
  wire             cpu_instruction_master_read_data_valid_epcs_epcs_control_port;
  wire             cpu_instruction_master_requests_epcs_epcs_control_port;
  wire             cpu_instruction_master_saved_grant_epcs_epcs_control_port;
  reg              d1_epcs_epcs_control_port_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_epcs_epcs_control_port;
  wire    [  8: 0] epcs_epcs_control_port_address;
  wire             epcs_epcs_control_port_allgrants;
  wire             epcs_epcs_control_port_allow_new_arb_cycle;
  wire             epcs_epcs_control_port_any_bursting_master_saved_grant;
  wire             epcs_epcs_control_port_any_continuerequest;
  reg     [  1: 0] epcs_epcs_control_port_arb_addend;
  wire             epcs_epcs_control_port_arb_counter_enable;
  reg     [  1: 0] epcs_epcs_control_port_arb_share_counter;
  wire    [  1: 0] epcs_epcs_control_port_arb_share_counter_next_value;
  wire    [  1: 0] epcs_epcs_control_port_arb_share_set_values;
  wire    [  1: 0] epcs_epcs_control_port_arb_winner;
  wire             epcs_epcs_control_port_arbitration_holdoff_internal;
  wire             epcs_epcs_control_port_beginbursttransfer_internal;
  wire             epcs_epcs_control_port_begins_xfer;
  wire             epcs_epcs_control_port_chipselect;
  wire    [  3: 0] epcs_epcs_control_port_chosen_master_double_vector;
  wire    [  1: 0] epcs_epcs_control_port_chosen_master_rot_left;
  wire             epcs_epcs_control_port_dataavailable_from_sa;
  wire             epcs_epcs_control_port_end_xfer;
  wire             epcs_epcs_control_port_endofpacket_from_sa;
  wire             epcs_epcs_control_port_firsttransfer;
  wire    [  1: 0] epcs_epcs_control_port_grant_vector;
  wire             epcs_epcs_control_port_in_a_read_cycle;
  wire             epcs_epcs_control_port_in_a_write_cycle;
  wire             epcs_epcs_control_port_irq_from_sa;
  wire    [  1: 0] epcs_epcs_control_port_master_qreq_vector;
  wire             epcs_epcs_control_port_non_bursting_master_requests;
  wire             epcs_epcs_control_port_read_n;
  wire    [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
  wire             epcs_epcs_control_port_readyfordata_from_sa;
  reg              epcs_epcs_control_port_reg_firsttransfer;
  wire             epcs_epcs_control_port_reset_n;
  reg     [  1: 0] epcs_epcs_control_port_saved_chosen_master_vector;
  reg              epcs_epcs_control_port_slavearbiterlockenable;
  wire             epcs_epcs_control_port_slavearbiterlockenable2;
  wire             epcs_epcs_control_port_unreg_firsttransfer;
  wire             epcs_epcs_control_port_waits_for_read;
  wire             epcs_epcs_control_port_waits_for_write;
  wire             epcs_epcs_control_port_write_n;
  wire    [ 31: 0] epcs_epcs_control_port_writedata;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port;
  reg              last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port;
  wire    [ 26: 0] shifted_address_to_epcs_epcs_control_port_from_cpu_data_master;
  wire    [ 26: 0] shifted_address_to_epcs_epcs_control_port_from_cpu_instruction_master;
  wire             wait_for_epcs_epcs_control_port_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~epcs_epcs_control_port_end_xfer;
    end


  assign epcs_epcs_control_port_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_epcs_epcs_control_port | cpu_instruction_master_qualified_request_epcs_epcs_control_port));
  //assign epcs_epcs_control_port_readdata_from_sa = epcs_epcs_control_port_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_epcs_control_port_readdata_from_sa = epcs_epcs_control_port_readdata;

  assign cpu_data_master_requests_epcs_epcs_control_port = ({cpu_data_master_address_to_slave[26 : 11] , 11'b0} == 27'h0) & (cpu_data_master_read | cpu_data_master_write);
  //assign epcs_epcs_control_port_dataavailable_from_sa = epcs_epcs_control_port_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_epcs_control_port_dataavailable_from_sa = epcs_epcs_control_port_dataavailable;

  //assign epcs_epcs_control_port_readyfordata_from_sa = epcs_epcs_control_port_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_epcs_control_port_readyfordata_from_sa = epcs_epcs_control_port_readyfordata;

  //epcs_epcs_control_port_arb_share_counter set values, which is an e_mux
  assign epcs_epcs_control_port_arb_share_set_values = 1;

  //epcs_epcs_control_port_non_bursting_master_requests mux, which is an e_mux
  assign epcs_epcs_control_port_non_bursting_master_requests = cpu_data_master_requests_epcs_epcs_control_port |
    cpu_instruction_master_requests_epcs_epcs_control_port |
    cpu_data_master_requests_epcs_epcs_control_port |
    cpu_instruction_master_requests_epcs_epcs_control_port;

  //epcs_epcs_control_port_any_bursting_master_saved_grant mux, which is an e_mux
  assign epcs_epcs_control_port_any_bursting_master_saved_grant = 0;

  //epcs_epcs_control_port_arb_share_counter_next_value assignment, which is an e_assign
  assign epcs_epcs_control_port_arb_share_counter_next_value = epcs_epcs_control_port_firsttransfer ? (epcs_epcs_control_port_arb_share_set_values - 1) : |epcs_epcs_control_port_arb_share_counter ? (epcs_epcs_control_port_arb_share_counter - 1) : 0;

  //epcs_epcs_control_port_allgrants all slave grants, which is an e_mux
  assign epcs_epcs_control_port_allgrants = (|epcs_epcs_control_port_grant_vector) |
    (|epcs_epcs_control_port_grant_vector) |
    (|epcs_epcs_control_port_grant_vector) |
    (|epcs_epcs_control_port_grant_vector);

  //epcs_epcs_control_port_end_xfer assignment, which is an e_assign
  assign epcs_epcs_control_port_end_xfer = ~(epcs_epcs_control_port_waits_for_read | epcs_epcs_control_port_waits_for_write);

  //end_xfer_arb_share_counter_term_epcs_epcs_control_port arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_epcs_epcs_control_port = epcs_epcs_control_port_end_xfer & (~epcs_epcs_control_port_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //epcs_epcs_control_port_arb_share_counter arbitration counter enable, which is an e_assign
  assign epcs_epcs_control_port_arb_counter_enable = (end_xfer_arb_share_counter_term_epcs_epcs_control_port & epcs_epcs_control_port_allgrants) | (end_xfer_arb_share_counter_term_epcs_epcs_control_port & ~epcs_epcs_control_port_non_bursting_master_requests);

  //epcs_epcs_control_port_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_epcs_control_port_arb_share_counter <= 0;
      else if (epcs_epcs_control_port_arb_counter_enable)
          epcs_epcs_control_port_arb_share_counter <= epcs_epcs_control_port_arb_share_counter_next_value;
    end


  //epcs_epcs_control_port_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_epcs_control_port_slavearbiterlockenable <= 0;
      else if ((|epcs_epcs_control_port_master_qreq_vector & end_xfer_arb_share_counter_term_epcs_epcs_control_port) | (end_xfer_arb_share_counter_term_epcs_epcs_control_port & ~epcs_epcs_control_port_non_bursting_master_requests))
          epcs_epcs_control_port_slavearbiterlockenable <= |epcs_epcs_control_port_arb_share_counter_next_value;
    end


  //cpu/data_master epcs/epcs_control_port arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = epcs_epcs_control_port_slavearbiterlockenable & cpu_data_master_continuerequest;

  //epcs_epcs_control_port_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign epcs_epcs_control_port_slavearbiterlockenable2 = |epcs_epcs_control_port_arb_share_counter_next_value;

  //cpu/data_master epcs/epcs_control_port arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = epcs_epcs_control_port_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master epcs/epcs_control_port arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = epcs_epcs_control_port_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master epcs/epcs_control_port arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = epcs_epcs_control_port_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted epcs/epcs_control_port last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port <= 0;
      else 
        last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port <= cpu_instruction_master_saved_grant_epcs_epcs_control_port ? 1 : (epcs_epcs_control_port_arbitration_holdoff_internal | ~cpu_instruction_master_requests_epcs_epcs_control_port) ? 0 : last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port & cpu_instruction_master_requests_epcs_epcs_control_port;

  //epcs_epcs_control_port_any_continuerequest at least one master continues requesting, which is an e_mux
  assign epcs_epcs_control_port_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_epcs_epcs_control_port = cpu_data_master_requests_epcs_epcs_control_port & ~(cpu_instruction_master_arbiterlock);
  //epcs_epcs_control_port_writedata mux, which is an e_mux
  assign epcs_epcs_control_port_writedata = cpu_data_master_writedata;

  //assign epcs_epcs_control_port_endofpacket_from_sa = epcs_epcs_control_port_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_epcs_control_port_endofpacket_from_sa = epcs_epcs_control_port_endofpacket;

  assign cpu_instruction_master_requests_epcs_epcs_control_port = (({cpu_instruction_master_address_to_slave[26 : 11] , 11'b0} == 27'h0) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted epcs/epcs_control_port last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port <= 0;
      else 
        last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port <= cpu_data_master_saved_grant_epcs_epcs_control_port ? 1 : (epcs_epcs_control_port_arbitration_holdoff_internal | ~cpu_data_master_requests_epcs_epcs_control_port) ? 0 : last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port & cpu_data_master_requests_epcs_epcs_control_port;

  assign cpu_instruction_master_qualified_request_epcs_epcs_control_port = cpu_instruction_master_requests_epcs_epcs_control_port & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0) | (|cpu_instruction_master_read_data_valid_sdram_s1_shift_register))) | cpu_data_master_arbiterlock);
  //local readdatavalid cpu_instruction_master_read_data_valid_epcs_epcs_control_port, which is an e_mux
  assign cpu_instruction_master_read_data_valid_epcs_epcs_control_port = cpu_instruction_master_granted_epcs_epcs_control_port & cpu_instruction_master_read & ~epcs_epcs_control_port_waits_for_read;

  //allow new arb cycle for epcs/epcs_control_port, which is an e_assign
  assign epcs_epcs_control_port_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for epcs/epcs_control_port, which is an e_assign
  assign epcs_epcs_control_port_master_qreq_vector[0] = cpu_instruction_master_qualified_request_epcs_epcs_control_port;

  //cpu/instruction_master grant epcs/epcs_control_port, which is an e_assign
  assign cpu_instruction_master_granted_epcs_epcs_control_port = epcs_epcs_control_port_grant_vector[0];

  //cpu/instruction_master saved-grant epcs/epcs_control_port, which is an e_assign
  assign cpu_instruction_master_saved_grant_epcs_epcs_control_port = epcs_epcs_control_port_arb_winner[0] && cpu_instruction_master_requests_epcs_epcs_control_port;

  //cpu/data_master assignment into master qualified-requests vector for epcs/epcs_control_port, which is an e_assign
  assign epcs_epcs_control_port_master_qreq_vector[1] = cpu_data_master_qualified_request_epcs_epcs_control_port;

  //cpu/data_master grant epcs/epcs_control_port, which is an e_assign
  assign cpu_data_master_granted_epcs_epcs_control_port = epcs_epcs_control_port_grant_vector[1];

  //cpu/data_master saved-grant epcs/epcs_control_port, which is an e_assign
  assign cpu_data_master_saved_grant_epcs_epcs_control_port = epcs_epcs_control_port_arb_winner[1] && cpu_data_master_requests_epcs_epcs_control_port;

  //epcs/epcs_control_port chosen-master double-vector, which is an e_assign
  assign epcs_epcs_control_port_chosen_master_double_vector = {epcs_epcs_control_port_master_qreq_vector, epcs_epcs_control_port_master_qreq_vector} & ({~epcs_epcs_control_port_master_qreq_vector, ~epcs_epcs_control_port_master_qreq_vector} + epcs_epcs_control_port_arb_addend);

  //stable onehot encoding of arb winner
  assign epcs_epcs_control_port_arb_winner = (epcs_epcs_control_port_allow_new_arb_cycle & | epcs_epcs_control_port_grant_vector) ? epcs_epcs_control_port_grant_vector : epcs_epcs_control_port_saved_chosen_master_vector;

  //saved epcs_epcs_control_port_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_epcs_control_port_saved_chosen_master_vector <= 0;
      else if (epcs_epcs_control_port_allow_new_arb_cycle)
          epcs_epcs_control_port_saved_chosen_master_vector <= |epcs_epcs_control_port_grant_vector ? epcs_epcs_control_port_grant_vector : epcs_epcs_control_port_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign epcs_epcs_control_port_grant_vector = {(epcs_epcs_control_port_chosen_master_double_vector[1] | epcs_epcs_control_port_chosen_master_double_vector[3]),
    (epcs_epcs_control_port_chosen_master_double_vector[0] | epcs_epcs_control_port_chosen_master_double_vector[2])};

  //epcs/epcs_control_port chosen master rotated left, which is an e_assign
  assign epcs_epcs_control_port_chosen_master_rot_left = (epcs_epcs_control_port_arb_winner << 1) ? (epcs_epcs_control_port_arb_winner << 1) : 1;

  //epcs/epcs_control_port's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_epcs_control_port_arb_addend <= 1;
      else if (|epcs_epcs_control_port_grant_vector)
          epcs_epcs_control_port_arb_addend <= epcs_epcs_control_port_end_xfer? epcs_epcs_control_port_chosen_master_rot_left : epcs_epcs_control_port_grant_vector;
    end


  //epcs_epcs_control_port_reset_n assignment, which is an e_assign
  assign epcs_epcs_control_port_reset_n = reset_n;

  assign epcs_epcs_control_port_chipselect = cpu_data_master_granted_epcs_epcs_control_port | cpu_instruction_master_granted_epcs_epcs_control_port;
  //epcs_epcs_control_port_firsttransfer first transaction, which is an e_assign
  assign epcs_epcs_control_port_firsttransfer = epcs_epcs_control_port_begins_xfer ? epcs_epcs_control_port_unreg_firsttransfer : epcs_epcs_control_port_reg_firsttransfer;

  //epcs_epcs_control_port_unreg_firsttransfer first transaction, which is an e_assign
  assign epcs_epcs_control_port_unreg_firsttransfer = ~(epcs_epcs_control_port_slavearbiterlockenable & epcs_epcs_control_port_any_continuerequest);

  //epcs_epcs_control_port_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          epcs_epcs_control_port_reg_firsttransfer <= 1'b1;
      else if (epcs_epcs_control_port_begins_xfer)
          epcs_epcs_control_port_reg_firsttransfer <= epcs_epcs_control_port_unreg_firsttransfer;
    end


  //epcs_epcs_control_port_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign epcs_epcs_control_port_beginbursttransfer_internal = epcs_epcs_control_port_begins_xfer;

  //epcs_epcs_control_port_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign epcs_epcs_control_port_arbitration_holdoff_internal = epcs_epcs_control_port_begins_xfer & epcs_epcs_control_port_firsttransfer;

  //~epcs_epcs_control_port_read_n assignment, which is an e_mux
  assign epcs_epcs_control_port_read_n = ~((cpu_data_master_granted_epcs_epcs_control_port & cpu_data_master_read) | (cpu_instruction_master_granted_epcs_epcs_control_port & cpu_instruction_master_read));

  //~epcs_epcs_control_port_write_n assignment, which is an e_mux
  assign epcs_epcs_control_port_write_n = ~(cpu_data_master_granted_epcs_epcs_control_port & cpu_data_master_write);

  assign shifted_address_to_epcs_epcs_control_port_from_cpu_data_master = cpu_data_master_address_to_slave;
  //epcs_epcs_control_port_address mux, which is an e_mux
  assign epcs_epcs_control_port_address = (cpu_data_master_granted_epcs_epcs_control_port)? (shifted_address_to_epcs_epcs_control_port_from_cpu_data_master >> 2) :
    (shifted_address_to_epcs_epcs_control_port_from_cpu_instruction_master >> 2);

  assign shifted_address_to_epcs_epcs_control_port_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
  //d1_epcs_epcs_control_port_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_epcs_epcs_control_port_end_xfer <= 1;
      else 
        d1_epcs_epcs_control_port_end_xfer <= epcs_epcs_control_port_end_xfer;
    end


  //epcs_epcs_control_port_waits_for_read in a cycle, which is an e_mux
  assign epcs_epcs_control_port_waits_for_read = epcs_epcs_control_port_in_a_read_cycle & epcs_epcs_control_port_begins_xfer;

  //epcs_epcs_control_port_in_a_read_cycle assignment, which is an e_assign
  assign epcs_epcs_control_port_in_a_read_cycle = (cpu_data_master_granted_epcs_epcs_control_port & cpu_data_master_read) | (cpu_instruction_master_granted_epcs_epcs_control_port & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = epcs_epcs_control_port_in_a_read_cycle;

  //epcs_epcs_control_port_waits_for_write in a cycle, which is an e_mux
  assign epcs_epcs_control_port_waits_for_write = epcs_epcs_control_port_in_a_write_cycle & epcs_epcs_control_port_begins_xfer;

  //epcs_epcs_control_port_in_a_write_cycle assignment, which is an e_assign
  assign epcs_epcs_control_port_in_a_write_cycle = cpu_data_master_granted_epcs_epcs_control_port & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = epcs_epcs_control_port_in_a_write_cycle;

  assign wait_for_epcs_epcs_control_port_counter = 0;
  //assign epcs_epcs_control_port_irq_from_sa = epcs_epcs_control_port_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign epcs_epcs_control_port_irq_from_sa = epcs_epcs_control_port_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //epcs/epcs_control_port enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_epcs_epcs_control_port + cpu_instruction_master_granted_epcs_epcs_control_port > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_epcs_epcs_control_port + cpu_instruction_master_saved_grant_epcs_epcs_control_port > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module jtag_uart_avalon_jtag_slave_arbitrator (
                                                // inputs:
                                                 clk,
                                                 cpu_data_master_address_to_slave,
                                                 cpu_data_master_read,
                                                 cpu_data_master_waitrequest,
                                                 cpu_data_master_write,
                                                 cpu_data_master_writedata,
                                                 jtag_uart_avalon_jtag_slave_dataavailable,
                                                 jtag_uart_avalon_jtag_slave_irq,
                                                 jtag_uart_avalon_jtag_slave_readdata,
                                                 jtag_uart_avalon_jtag_slave_readyfordata,
                                                 jtag_uart_avalon_jtag_slave_waitrequest,
                                                 reset_n,

                                                // outputs:
                                                 cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                                 d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                                 jtag_uart_avalon_jtag_slave_address,
                                                 jtag_uart_avalon_jtag_slave_chipselect,
                                                 jtag_uart_avalon_jtag_slave_dataavailable_from_sa,
                                                 jtag_uart_avalon_jtag_slave_irq_from_sa,
                                                 jtag_uart_avalon_jtag_slave_read_n,
                                                 jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                                 jtag_uart_avalon_jtag_slave_readyfordata_from_sa,
                                                 jtag_uart_avalon_jtag_slave_reset_n,
                                                 jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                                 jtag_uart_avalon_jtag_slave_write_n,
                                                 jtag_uart_avalon_jtag_slave_writedata
                                              )
;

  output           cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  output           d1_jtag_uart_avalon_jtag_slave_end_xfer;
  output           jtag_uart_avalon_jtag_slave_address;
  output           jtag_uart_avalon_jtag_slave_chipselect;
  output           jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  output           jtag_uart_avalon_jtag_slave_irq_from_sa;
  output           jtag_uart_avalon_jtag_slave_read_n;
  output  [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  output           jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  output           jtag_uart_avalon_jtag_slave_reset_n;
  output           jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  output           jtag_uart_avalon_jtag_slave_write_n;
  output  [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            jtag_uart_avalon_jtag_slave_dataavailable;
  input            jtag_uart_avalon_jtag_slave_irq;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
  input            jtag_uart_avalon_jtag_slave_readyfordata;
  input            jtag_uart_avalon_jtag_slave_waitrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave;
  reg              d1_jtag_uart_avalon_jtag_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             jtag_uart_avalon_jtag_slave_address;
  wire             jtag_uart_avalon_jtag_slave_allgrants;
  wire             jtag_uart_avalon_jtag_slave_allow_new_arb_cycle;
  wire             jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant;
  wire             jtag_uart_avalon_jtag_slave_any_continuerequest;
  wire             jtag_uart_avalon_jtag_slave_arb_counter_enable;
  reg     [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_counter;
  wire    [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
  wire    [  1: 0] jtag_uart_avalon_jtag_slave_arb_share_set_values;
  wire             jtag_uart_avalon_jtag_slave_beginbursttransfer_internal;
  wire             jtag_uart_avalon_jtag_slave_begins_xfer;
  wire             jtag_uart_avalon_jtag_slave_chipselect;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_end_xfer;
  wire             jtag_uart_avalon_jtag_slave_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_grant_vector;
  wire             jtag_uart_avalon_jtag_slave_in_a_read_cycle;
  wire             jtag_uart_avalon_jtag_slave_in_a_write_cycle;
  wire             jtag_uart_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_avalon_jtag_slave_master_qreq_vector;
  wire             jtag_uart_avalon_jtag_slave_non_bursting_master_requests;
  wire             jtag_uart_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  reg              jtag_uart_avalon_jtag_slave_reg_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_reset_n;
  reg              jtag_uart_avalon_jtag_slave_slavearbiterlockenable;
  wire             jtag_uart_avalon_jtag_slave_slavearbiterlockenable2;
  wire             jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_avalon_jtag_slave_waits_for_read;
  wire             jtag_uart_avalon_jtag_slave_waits_for_write;
  wire             jtag_uart_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  wire    [ 26: 0] shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master;
  wire             wait_for_jtag_uart_avalon_jtag_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~jtag_uart_avalon_jtag_slave_end_xfer;
    end


  assign jtag_uart_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave));
  //assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata;

  assign cpu_data_master_requests_jtag_uart_avalon_jtag_slave = ({cpu_data_master_address_to_slave[26 : 3] , 3'b0} == 27'h18c8) & (cpu_data_master_read | cpu_data_master_write);
  //assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable;

  //assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata;

  //assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest;

  //jtag_uart_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_arb_share_set_values = 1;

  //jtag_uart_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_non_bursting_master_requests = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

  //jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant = 0;

  //jtag_uart_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_avalon_jtag_slave_firsttransfer ? (jtag_uart_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_avalon_jtag_slave_arb_share_counter ? (jtag_uart_avalon_jtag_slave_arb_share_counter - 1) : 0;

  //jtag_uart_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_allgrants = |jtag_uart_avalon_jtag_slave_grant_vector;

  //jtag_uart_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_end_xfer = ~(jtag_uart_avalon_jtag_slave_waits_for_read | jtag_uart_avalon_jtag_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave = jtag_uart_avalon_jtag_slave_end_xfer & (~jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //jtag_uart_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & jtag_uart_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests);

  //jtag_uart_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_arb_share_counter <= 0;
      else if (jtag_uart_avalon_jtag_slave_arb_counter_enable)
          jtag_uart_avalon_jtag_slave_arb_share_counter <= jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //jtag_uart_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= 0;
      else if ((|jtag_uart_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests))
          jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = jtag_uart_avalon_jtag_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;

  //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //jtag_uart_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave & ~((cpu_data_master_read & (~cpu_data_master_waitrequest)) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //jtag_uart_avalon_jtag_slave_writedata mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_jtag_uart_avalon_jtag_slave = cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;

  //cpu/data_master saved-grant jtag_uart/avalon_jtag_slave, which is an e_assign
  assign cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

  //allow new arb cycle for jtag_uart/avalon_jtag_slave, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign jtag_uart_avalon_jtag_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign jtag_uart_avalon_jtag_slave_master_qreq_vector = 1;

  //jtag_uart_avalon_jtag_slave_reset_n assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_reset_n = reset_n;

  assign jtag_uart_avalon_jtag_slave_chipselect = cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  //jtag_uart_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_firsttransfer = jtag_uart_avalon_jtag_slave_begins_xfer ? jtag_uart_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_avalon_jtag_slave_reg_firsttransfer;

  //jtag_uart_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_avalon_jtag_slave_any_continuerequest);

  //jtag_uart_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
      else if (jtag_uart_avalon_jtag_slave_begins_xfer)
          jtag_uart_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
    end


  //jtag_uart_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_avalon_jtag_slave_begins_xfer;

  //~jtag_uart_avalon_jtag_slave_read_n assignment, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_read_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read);

  //~jtag_uart_avalon_jtag_slave_write_n assignment, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_write_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write);

  assign shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //jtag_uart_avalon_jtag_slave_address mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_address = shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master >> 2;

  //d1_jtag_uart_avalon_jtag_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_jtag_uart_avalon_jtag_slave_end_xfer <= 1;
      else 
        d1_jtag_uart_avalon_jtag_slave_end_xfer <= jtag_uart_avalon_jtag_slave_end_xfer;
    end


  //jtag_uart_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_waits_for_read = jtag_uart_avalon_jtag_slave_in_a_read_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_in_a_read_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = jtag_uart_avalon_jtag_slave_in_a_read_cycle;

  //jtag_uart_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_waits_for_write = jtag_uart_avalon_jtag_slave_in_a_write_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_in_a_write_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = jtag_uart_avalon_jtag_slave_in_a_write_cycle;

  assign wait_for_jtag_uart_avalon_jtag_slave_counter = 0;
  //assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart/avalon_jtag_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module lcd32_data_s1_arbitrator (
                                  // inputs:
                                   clk,
                                   cpu_data_master_address_to_slave,
                                   cpu_data_master_read,
                                   cpu_data_master_waitrequest,
                                   cpu_data_master_write,
                                   cpu_data_master_writedata,
                                   lcd32_data_s1_readdata,
                                   reset_n,

                                  // outputs:
                                   cpu_data_master_granted_lcd32_data_s1,
                                   cpu_data_master_qualified_request_lcd32_data_s1,
                                   cpu_data_master_read_data_valid_lcd32_data_s1,
                                   cpu_data_master_requests_lcd32_data_s1,
                                   d1_lcd32_data_s1_end_xfer,
                                   lcd32_data_s1_address,
                                   lcd32_data_s1_chipselect,
                                   lcd32_data_s1_readdata_from_sa,
                                   lcd32_data_s1_reset_n,
                                   lcd32_data_s1_write_n,
                                   lcd32_data_s1_writedata
                                )
;

  output           cpu_data_master_granted_lcd32_data_s1;
  output           cpu_data_master_qualified_request_lcd32_data_s1;
  output           cpu_data_master_read_data_valid_lcd32_data_s1;
  output           cpu_data_master_requests_lcd32_data_s1;
  output           d1_lcd32_data_s1_end_xfer;
  output  [  1: 0] lcd32_data_s1_address;
  output           lcd32_data_s1_chipselect;
  output  [ 31: 0] lcd32_data_s1_readdata_from_sa;
  output           lcd32_data_s1_reset_n;
  output           lcd32_data_s1_write_n;
  output  [ 31: 0] lcd32_data_s1_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] lcd32_data_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_lcd32_data_s1;
  wire             cpu_data_master_qualified_request_lcd32_data_s1;
  wire             cpu_data_master_read_data_valid_lcd32_data_s1;
  wire             cpu_data_master_requests_lcd32_data_s1;
  wire             cpu_data_master_saved_grant_lcd32_data_s1;
  reg              d1_lcd32_data_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_lcd32_data_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] lcd32_data_s1_address;
  wire             lcd32_data_s1_allgrants;
  wire             lcd32_data_s1_allow_new_arb_cycle;
  wire             lcd32_data_s1_any_bursting_master_saved_grant;
  wire             lcd32_data_s1_any_continuerequest;
  wire             lcd32_data_s1_arb_counter_enable;
  reg     [  1: 0] lcd32_data_s1_arb_share_counter;
  wire    [  1: 0] lcd32_data_s1_arb_share_counter_next_value;
  wire    [  1: 0] lcd32_data_s1_arb_share_set_values;
  wire             lcd32_data_s1_beginbursttransfer_internal;
  wire             lcd32_data_s1_begins_xfer;
  wire             lcd32_data_s1_chipselect;
  wire             lcd32_data_s1_end_xfer;
  wire             lcd32_data_s1_firsttransfer;
  wire             lcd32_data_s1_grant_vector;
  wire             lcd32_data_s1_in_a_read_cycle;
  wire             lcd32_data_s1_in_a_write_cycle;
  wire             lcd32_data_s1_master_qreq_vector;
  wire             lcd32_data_s1_non_bursting_master_requests;
  wire    [ 31: 0] lcd32_data_s1_readdata_from_sa;
  reg              lcd32_data_s1_reg_firsttransfer;
  wire             lcd32_data_s1_reset_n;
  reg              lcd32_data_s1_slavearbiterlockenable;
  wire             lcd32_data_s1_slavearbiterlockenable2;
  wire             lcd32_data_s1_unreg_firsttransfer;
  wire             lcd32_data_s1_waits_for_read;
  wire             lcd32_data_s1_waits_for_write;
  wire             lcd32_data_s1_write_n;
  wire    [ 31: 0] lcd32_data_s1_writedata;
  wire    [ 26: 0] shifted_address_to_lcd32_data_s1_from_cpu_data_master;
  wire             wait_for_lcd32_data_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~lcd32_data_s1_end_xfer;
    end


  assign lcd32_data_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_lcd32_data_s1));
  //assign lcd32_data_s1_readdata_from_sa = lcd32_data_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign lcd32_data_s1_readdata_from_sa = lcd32_data_s1_readdata;

  assign cpu_data_master_requests_lcd32_data_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1880) & (cpu_data_master_read | cpu_data_master_write);
  //lcd32_data_s1_arb_share_counter set values, which is an e_mux
  assign lcd32_data_s1_arb_share_set_values = 1;

  //lcd32_data_s1_non_bursting_master_requests mux, which is an e_mux
  assign lcd32_data_s1_non_bursting_master_requests = cpu_data_master_requests_lcd32_data_s1;

  //lcd32_data_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign lcd32_data_s1_any_bursting_master_saved_grant = 0;

  //lcd32_data_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign lcd32_data_s1_arb_share_counter_next_value = lcd32_data_s1_firsttransfer ? (lcd32_data_s1_arb_share_set_values - 1) : |lcd32_data_s1_arb_share_counter ? (lcd32_data_s1_arb_share_counter - 1) : 0;

  //lcd32_data_s1_allgrants all slave grants, which is an e_mux
  assign lcd32_data_s1_allgrants = |lcd32_data_s1_grant_vector;

  //lcd32_data_s1_end_xfer assignment, which is an e_assign
  assign lcd32_data_s1_end_xfer = ~(lcd32_data_s1_waits_for_read | lcd32_data_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_lcd32_data_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_lcd32_data_s1 = lcd32_data_s1_end_xfer & (~lcd32_data_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //lcd32_data_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign lcd32_data_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_lcd32_data_s1 & lcd32_data_s1_allgrants) | (end_xfer_arb_share_counter_term_lcd32_data_s1 & ~lcd32_data_s1_non_bursting_master_requests);

  //lcd32_data_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd32_data_s1_arb_share_counter <= 0;
      else if (lcd32_data_s1_arb_counter_enable)
          lcd32_data_s1_arb_share_counter <= lcd32_data_s1_arb_share_counter_next_value;
    end


  //lcd32_data_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd32_data_s1_slavearbiterlockenable <= 0;
      else if ((|lcd32_data_s1_master_qreq_vector & end_xfer_arb_share_counter_term_lcd32_data_s1) | (end_xfer_arb_share_counter_term_lcd32_data_s1 & ~lcd32_data_s1_non_bursting_master_requests))
          lcd32_data_s1_slavearbiterlockenable <= |lcd32_data_s1_arb_share_counter_next_value;
    end


  //cpu/data_master lcd32_data/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = lcd32_data_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //lcd32_data_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign lcd32_data_s1_slavearbiterlockenable2 = |lcd32_data_s1_arb_share_counter_next_value;

  //cpu/data_master lcd32_data/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = lcd32_data_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //lcd32_data_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign lcd32_data_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_lcd32_data_s1 = cpu_data_master_requests_lcd32_data_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //lcd32_data_s1_writedata mux, which is an e_mux
  assign lcd32_data_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_lcd32_data_s1 = cpu_data_master_qualified_request_lcd32_data_s1;

  //cpu/data_master saved-grant lcd32_data/s1, which is an e_assign
  assign cpu_data_master_saved_grant_lcd32_data_s1 = cpu_data_master_requests_lcd32_data_s1;

  //allow new arb cycle for lcd32_data/s1, which is an e_assign
  assign lcd32_data_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign lcd32_data_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign lcd32_data_s1_master_qreq_vector = 1;

  //lcd32_data_s1_reset_n assignment, which is an e_assign
  assign lcd32_data_s1_reset_n = reset_n;

  assign lcd32_data_s1_chipselect = cpu_data_master_granted_lcd32_data_s1;
  //lcd32_data_s1_firsttransfer first transaction, which is an e_assign
  assign lcd32_data_s1_firsttransfer = lcd32_data_s1_begins_xfer ? lcd32_data_s1_unreg_firsttransfer : lcd32_data_s1_reg_firsttransfer;

  //lcd32_data_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign lcd32_data_s1_unreg_firsttransfer = ~(lcd32_data_s1_slavearbiterlockenable & lcd32_data_s1_any_continuerequest);

  //lcd32_data_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd32_data_s1_reg_firsttransfer <= 1'b1;
      else if (lcd32_data_s1_begins_xfer)
          lcd32_data_s1_reg_firsttransfer <= lcd32_data_s1_unreg_firsttransfer;
    end


  //lcd32_data_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign lcd32_data_s1_beginbursttransfer_internal = lcd32_data_s1_begins_xfer;

  //~lcd32_data_s1_write_n assignment, which is an e_mux
  assign lcd32_data_s1_write_n = ~(cpu_data_master_granted_lcd32_data_s1 & cpu_data_master_write);

  assign shifted_address_to_lcd32_data_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //lcd32_data_s1_address mux, which is an e_mux
  assign lcd32_data_s1_address = shifted_address_to_lcd32_data_s1_from_cpu_data_master >> 2;

  //d1_lcd32_data_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_lcd32_data_s1_end_xfer <= 1;
      else 
        d1_lcd32_data_s1_end_xfer <= lcd32_data_s1_end_xfer;
    end


  //lcd32_data_s1_waits_for_read in a cycle, which is an e_mux
  assign lcd32_data_s1_waits_for_read = lcd32_data_s1_in_a_read_cycle & lcd32_data_s1_begins_xfer;

  //lcd32_data_s1_in_a_read_cycle assignment, which is an e_assign
  assign lcd32_data_s1_in_a_read_cycle = cpu_data_master_granted_lcd32_data_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = lcd32_data_s1_in_a_read_cycle;

  //lcd32_data_s1_waits_for_write in a cycle, which is an e_mux
  assign lcd32_data_s1_waits_for_write = lcd32_data_s1_in_a_write_cycle & 0;

  //lcd32_data_s1_in_a_write_cycle assignment, which is an e_assign
  assign lcd32_data_s1_in_a_write_cycle = cpu_data_master_granted_lcd32_data_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = lcd32_data_s1_in_a_write_cycle;

  assign wait_for_lcd32_data_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //lcd32_data/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module lcd_cs_s1_arbitrator (
                              // inputs:
                               clk,
                               cpu_data_master_address_to_slave,
                               cpu_data_master_read,
                               cpu_data_master_waitrequest,
                               cpu_data_master_write,
                               cpu_data_master_writedata,
                               lcd_cs_s1_readdata,
                               reset_n,

                              // outputs:
                               cpu_data_master_granted_lcd_cs_s1,
                               cpu_data_master_qualified_request_lcd_cs_s1,
                               cpu_data_master_read_data_valid_lcd_cs_s1,
                               cpu_data_master_requests_lcd_cs_s1,
                               d1_lcd_cs_s1_end_xfer,
                               lcd_cs_s1_address,
                               lcd_cs_s1_chipselect,
                               lcd_cs_s1_readdata_from_sa,
                               lcd_cs_s1_reset_n,
                               lcd_cs_s1_write_n,
                               lcd_cs_s1_writedata
                            )
;

  output           cpu_data_master_granted_lcd_cs_s1;
  output           cpu_data_master_qualified_request_lcd_cs_s1;
  output           cpu_data_master_read_data_valid_lcd_cs_s1;
  output           cpu_data_master_requests_lcd_cs_s1;
  output           d1_lcd_cs_s1_end_xfer;
  output  [  1: 0] lcd_cs_s1_address;
  output           lcd_cs_s1_chipselect;
  output  [ 31: 0] lcd_cs_s1_readdata_from_sa;
  output           lcd_cs_s1_reset_n;
  output           lcd_cs_s1_write_n;
  output  [ 31: 0] lcd_cs_s1_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] lcd_cs_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_lcd_cs_s1;
  wire             cpu_data_master_qualified_request_lcd_cs_s1;
  wire             cpu_data_master_read_data_valid_lcd_cs_s1;
  wire             cpu_data_master_requests_lcd_cs_s1;
  wire             cpu_data_master_saved_grant_lcd_cs_s1;
  reg              d1_lcd_cs_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_lcd_cs_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] lcd_cs_s1_address;
  wire             lcd_cs_s1_allgrants;
  wire             lcd_cs_s1_allow_new_arb_cycle;
  wire             lcd_cs_s1_any_bursting_master_saved_grant;
  wire             lcd_cs_s1_any_continuerequest;
  wire             lcd_cs_s1_arb_counter_enable;
  reg     [  1: 0] lcd_cs_s1_arb_share_counter;
  wire    [  1: 0] lcd_cs_s1_arb_share_counter_next_value;
  wire    [  1: 0] lcd_cs_s1_arb_share_set_values;
  wire             lcd_cs_s1_beginbursttransfer_internal;
  wire             lcd_cs_s1_begins_xfer;
  wire             lcd_cs_s1_chipselect;
  wire             lcd_cs_s1_end_xfer;
  wire             lcd_cs_s1_firsttransfer;
  wire             lcd_cs_s1_grant_vector;
  wire             lcd_cs_s1_in_a_read_cycle;
  wire             lcd_cs_s1_in_a_write_cycle;
  wire             lcd_cs_s1_master_qreq_vector;
  wire             lcd_cs_s1_non_bursting_master_requests;
  wire    [ 31: 0] lcd_cs_s1_readdata_from_sa;
  reg              lcd_cs_s1_reg_firsttransfer;
  wire             lcd_cs_s1_reset_n;
  reg              lcd_cs_s1_slavearbiterlockenable;
  wire             lcd_cs_s1_slavearbiterlockenable2;
  wire             lcd_cs_s1_unreg_firsttransfer;
  wire             lcd_cs_s1_waits_for_read;
  wire             lcd_cs_s1_waits_for_write;
  wire             lcd_cs_s1_write_n;
  wire    [ 31: 0] lcd_cs_s1_writedata;
  wire    [ 26: 0] shifted_address_to_lcd_cs_s1_from_cpu_data_master;
  wire             wait_for_lcd_cs_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~lcd_cs_s1_end_xfer;
    end


  assign lcd_cs_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_lcd_cs_s1));
  //assign lcd_cs_s1_readdata_from_sa = lcd_cs_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign lcd_cs_s1_readdata_from_sa = lcd_cs_s1_readdata;

  assign cpu_data_master_requests_lcd_cs_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1820) & (cpu_data_master_read | cpu_data_master_write);
  //lcd_cs_s1_arb_share_counter set values, which is an e_mux
  assign lcd_cs_s1_arb_share_set_values = 1;

  //lcd_cs_s1_non_bursting_master_requests mux, which is an e_mux
  assign lcd_cs_s1_non_bursting_master_requests = cpu_data_master_requests_lcd_cs_s1;

  //lcd_cs_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign lcd_cs_s1_any_bursting_master_saved_grant = 0;

  //lcd_cs_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign lcd_cs_s1_arb_share_counter_next_value = lcd_cs_s1_firsttransfer ? (lcd_cs_s1_arb_share_set_values - 1) : |lcd_cs_s1_arb_share_counter ? (lcd_cs_s1_arb_share_counter - 1) : 0;

  //lcd_cs_s1_allgrants all slave grants, which is an e_mux
  assign lcd_cs_s1_allgrants = |lcd_cs_s1_grant_vector;

  //lcd_cs_s1_end_xfer assignment, which is an e_assign
  assign lcd_cs_s1_end_xfer = ~(lcd_cs_s1_waits_for_read | lcd_cs_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_lcd_cs_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_lcd_cs_s1 = lcd_cs_s1_end_xfer & (~lcd_cs_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //lcd_cs_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign lcd_cs_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_lcd_cs_s1 & lcd_cs_s1_allgrants) | (end_xfer_arb_share_counter_term_lcd_cs_s1 & ~lcd_cs_s1_non_bursting_master_requests);

  //lcd_cs_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_cs_s1_arb_share_counter <= 0;
      else if (lcd_cs_s1_arb_counter_enable)
          lcd_cs_s1_arb_share_counter <= lcd_cs_s1_arb_share_counter_next_value;
    end


  //lcd_cs_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_cs_s1_slavearbiterlockenable <= 0;
      else if ((|lcd_cs_s1_master_qreq_vector & end_xfer_arb_share_counter_term_lcd_cs_s1) | (end_xfer_arb_share_counter_term_lcd_cs_s1 & ~lcd_cs_s1_non_bursting_master_requests))
          lcd_cs_s1_slavearbiterlockenable <= |lcd_cs_s1_arb_share_counter_next_value;
    end


  //cpu/data_master lcd_cs/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = lcd_cs_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //lcd_cs_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign lcd_cs_s1_slavearbiterlockenable2 = |lcd_cs_s1_arb_share_counter_next_value;

  //cpu/data_master lcd_cs/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = lcd_cs_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //lcd_cs_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign lcd_cs_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_lcd_cs_s1 = cpu_data_master_requests_lcd_cs_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //lcd_cs_s1_writedata mux, which is an e_mux
  assign lcd_cs_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_lcd_cs_s1 = cpu_data_master_qualified_request_lcd_cs_s1;

  //cpu/data_master saved-grant lcd_cs/s1, which is an e_assign
  assign cpu_data_master_saved_grant_lcd_cs_s1 = cpu_data_master_requests_lcd_cs_s1;

  //allow new arb cycle for lcd_cs/s1, which is an e_assign
  assign lcd_cs_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign lcd_cs_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign lcd_cs_s1_master_qreq_vector = 1;

  //lcd_cs_s1_reset_n assignment, which is an e_assign
  assign lcd_cs_s1_reset_n = reset_n;

  assign lcd_cs_s1_chipselect = cpu_data_master_granted_lcd_cs_s1;
  //lcd_cs_s1_firsttransfer first transaction, which is an e_assign
  assign lcd_cs_s1_firsttransfer = lcd_cs_s1_begins_xfer ? lcd_cs_s1_unreg_firsttransfer : lcd_cs_s1_reg_firsttransfer;

  //lcd_cs_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign lcd_cs_s1_unreg_firsttransfer = ~(lcd_cs_s1_slavearbiterlockenable & lcd_cs_s1_any_continuerequest);

  //lcd_cs_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_cs_s1_reg_firsttransfer <= 1'b1;
      else if (lcd_cs_s1_begins_xfer)
          lcd_cs_s1_reg_firsttransfer <= lcd_cs_s1_unreg_firsttransfer;
    end


  //lcd_cs_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign lcd_cs_s1_beginbursttransfer_internal = lcd_cs_s1_begins_xfer;

  //~lcd_cs_s1_write_n assignment, which is an e_mux
  assign lcd_cs_s1_write_n = ~(cpu_data_master_granted_lcd_cs_s1 & cpu_data_master_write);

  assign shifted_address_to_lcd_cs_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //lcd_cs_s1_address mux, which is an e_mux
  assign lcd_cs_s1_address = shifted_address_to_lcd_cs_s1_from_cpu_data_master >> 2;

  //d1_lcd_cs_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_lcd_cs_s1_end_xfer <= 1;
      else 
        d1_lcd_cs_s1_end_xfer <= lcd_cs_s1_end_xfer;
    end


  //lcd_cs_s1_waits_for_read in a cycle, which is an e_mux
  assign lcd_cs_s1_waits_for_read = lcd_cs_s1_in_a_read_cycle & lcd_cs_s1_begins_xfer;

  //lcd_cs_s1_in_a_read_cycle assignment, which is an e_assign
  assign lcd_cs_s1_in_a_read_cycle = cpu_data_master_granted_lcd_cs_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = lcd_cs_s1_in_a_read_cycle;

  //lcd_cs_s1_waits_for_write in a cycle, which is an e_mux
  assign lcd_cs_s1_waits_for_write = lcd_cs_s1_in_a_write_cycle & 0;

  //lcd_cs_s1_in_a_write_cycle assignment, which is an e_assign
  assign lcd_cs_s1_in_a_write_cycle = cpu_data_master_granted_lcd_cs_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = lcd_cs_s1_in_a_write_cycle;

  assign wait_for_lcd_cs_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //lcd_cs/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module lcd_rd_s1_arbitrator (
                              // inputs:
                               clk,
                               cpu_data_master_address_to_slave,
                               cpu_data_master_read,
                               cpu_data_master_waitrequest,
                               cpu_data_master_write,
                               cpu_data_master_writedata,
                               lcd_rd_s1_readdata,
                               reset_n,

                              // outputs:
                               cpu_data_master_granted_lcd_rd_s1,
                               cpu_data_master_qualified_request_lcd_rd_s1,
                               cpu_data_master_read_data_valid_lcd_rd_s1,
                               cpu_data_master_requests_lcd_rd_s1,
                               d1_lcd_rd_s1_end_xfer,
                               lcd_rd_s1_address,
                               lcd_rd_s1_chipselect,
                               lcd_rd_s1_readdata_from_sa,
                               lcd_rd_s1_reset_n,
                               lcd_rd_s1_write_n,
                               lcd_rd_s1_writedata
                            )
;

  output           cpu_data_master_granted_lcd_rd_s1;
  output           cpu_data_master_qualified_request_lcd_rd_s1;
  output           cpu_data_master_read_data_valid_lcd_rd_s1;
  output           cpu_data_master_requests_lcd_rd_s1;
  output           d1_lcd_rd_s1_end_xfer;
  output  [  1: 0] lcd_rd_s1_address;
  output           lcd_rd_s1_chipselect;
  output  [ 31: 0] lcd_rd_s1_readdata_from_sa;
  output           lcd_rd_s1_reset_n;
  output           lcd_rd_s1_write_n;
  output  [ 31: 0] lcd_rd_s1_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] lcd_rd_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_lcd_rd_s1;
  wire             cpu_data_master_qualified_request_lcd_rd_s1;
  wire             cpu_data_master_read_data_valid_lcd_rd_s1;
  wire             cpu_data_master_requests_lcd_rd_s1;
  wire             cpu_data_master_saved_grant_lcd_rd_s1;
  reg              d1_lcd_rd_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_lcd_rd_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] lcd_rd_s1_address;
  wire             lcd_rd_s1_allgrants;
  wire             lcd_rd_s1_allow_new_arb_cycle;
  wire             lcd_rd_s1_any_bursting_master_saved_grant;
  wire             lcd_rd_s1_any_continuerequest;
  wire             lcd_rd_s1_arb_counter_enable;
  reg     [  1: 0] lcd_rd_s1_arb_share_counter;
  wire    [  1: 0] lcd_rd_s1_arb_share_counter_next_value;
  wire    [  1: 0] lcd_rd_s1_arb_share_set_values;
  wire             lcd_rd_s1_beginbursttransfer_internal;
  wire             lcd_rd_s1_begins_xfer;
  wire             lcd_rd_s1_chipselect;
  wire             lcd_rd_s1_end_xfer;
  wire             lcd_rd_s1_firsttransfer;
  wire             lcd_rd_s1_grant_vector;
  wire             lcd_rd_s1_in_a_read_cycle;
  wire             lcd_rd_s1_in_a_write_cycle;
  wire             lcd_rd_s1_master_qreq_vector;
  wire             lcd_rd_s1_non_bursting_master_requests;
  wire    [ 31: 0] lcd_rd_s1_readdata_from_sa;
  reg              lcd_rd_s1_reg_firsttransfer;
  wire             lcd_rd_s1_reset_n;
  reg              lcd_rd_s1_slavearbiterlockenable;
  wire             lcd_rd_s1_slavearbiterlockenable2;
  wire             lcd_rd_s1_unreg_firsttransfer;
  wire             lcd_rd_s1_waits_for_read;
  wire             lcd_rd_s1_waits_for_write;
  wire             lcd_rd_s1_write_n;
  wire    [ 31: 0] lcd_rd_s1_writedata;
  wire    [ 26: 0] shifted_address_to_lcd_rd_s1_from_cpu_data_master;
  wire             wait_for_lcd_rd_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~lcd_rd_s1_end_xfer;
    end


  assign lcd_rd_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_lcd_rd_s1));
  //assign lcd_rd_s1_readdata_from_sa = lcd_rd_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign lcd_rd_s1_readdata_from_sa = lcd_rd_s1_readdata;

  assign cpu_data_master_requests_lcd_rd_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1890) & (cpu_data_master_read | cpu_data_master_write);
  //lcd_rd_s1_arb_share_counter set values, which is an e_mux
  assign lcd_rd_s1_arb_share_set_values = 1;

  //lcd_rd_s1_non_bursting_master_requests mux, which is an e_mux
  assign lcd_rd_s1_non_bursting_master_requests = cpu_data_master_requests_lcd_rd_s1;

  //lcd_rd_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign lcd_rd_s1_any_bursting_master_saved_grant = 0;

  //lcd_rd_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign lcd_rd_s1_arb_share_counter_next_value = lcd_rd_s1_firsttransfer ? (lcd_rd_s1_arb_share_set_values - 1) : |lcd_rd_s1_arb_share_counter ? (lcd_rd_s1_arb_share_counter - 1) : 0;

  //lcd_rd_s1_allgrants all slave grants, which is an e_mux
  assign lcd_rd_s1_allgrants = |lcd_rd_s1_grant_vector;

  //lcd_rd_s1_end_xfer assignment, which is an e_assign
  assign lcd_rd_s1_end_xfer = ~(lcd_rd_s1_waits_for_read | lcd_rd_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_lcd_rd_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_lcd_rd_s1 = lcd_rd_s1_end_xfer & (~lcd_rd_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //lcd_rd_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign lcd_rd_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_lcd_rd_s1 & lcd_rd_s1_allgrants) | (end_xfer_arb_share_counter_term_lcd_rd_s1 & ~lcd_rd_s1_non_bursting_master_requests);

  //lcd_rd_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_rd_s1_arb_share_counter <= 0;
      else if (lcd_rd_s1_arb_counter_enable)
          lcd_rd_s1_arb_share_counter <= lcd_rd_s1_arb_share_counter_next_value;
    end


  //lcd_rd_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_rd_s1_slavearbiterlockenable <= 0;
      else if ((|lcd_rd_s1_master_qreq_vector & end_xfer_arb_share_counter_term_lcd_rd_s1) | (end_xfer_arb_share_counter_term_lcd_rd_s1 & ~lcd_rd_s1_non_bursting_master_requests))
          lcd_rd_s1_slavearbiterlockenable <= |lcd_rd_s1_arb_share_counter_next_value;
    end


  //cpu/data_master lcd_rd/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = lcd_rd_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //lcd_rd_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign lcd_rd_s1_slavearbiterlockenable2 = |lcd_rd_s1_arb_share_counter_next_value;

  //cpu/data_master lcd_rd/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = lcd_rd_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //lcd_rd_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign lcd_rd_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_lcd_rd_s1 = cpu_data_master_requests_lcd_rd_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //lcd_rd_s1_writedata mux, which is an e_mux
  assign lcd_rd_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_lcd_rd_s1 = cpu_data_master_qualified_request_lcd_rd_s1;

  //cpu/data_master saved-grant lcd_rd/s1, which is an e_assign
  assign cpu_data_master_saved_grant_lcd_rd_s1 = cpu_data_master_requests_lcd_rd_s1;

  //allow new arb cycle for lcd_rd/s1, which is an e_assign
  assign lcd_rd_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign lcd_rd_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign lcd_rd_s1_master_qreq_vector = 1;

  //lcd_rd_s1_reset_n assignment, which is an e_assign
  assign lcd_rd_s1_reset_n = reset_n;

  assign lcd_rd_s1_chipselect = cpu_data_master_granted_lcd_rd_s1;
  //lcd_rd_s1_firsttransfer first transaction, which is an e_assign
  assign lcd_rd_s1_firsttransfer = lcd_rd_s1_begins_xfer ? lcd_rd_s1_unreg_firsttransfer : lcd_rd_s1_reg_firsttransfer;

  //lcd_rd_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign lcd_rd_s1_unreg_firsttransfer = ~(lcd_rd_s1_slavearbiterlockenable & lcd_rd_s1_any_continuerequest);

  //lcd_rd_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_rd_s1_reg_firsttransfer <= 1'b1;
      else if (lcd_rd_s1_begins_xfer)
          lcd_rd_s1_reg_firsttransfer <= lcd_rd_s1_unreg_firsttransfer;
    end


  //lcd_rd_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign lcd_rd_s1_beginbursttransfer_internal = lcd_rd_s1_begins_xfer;

  //~lcd_rd_s1_write_n assignment, which is an e_mux
  assign lcd_rd_s1_write_n = ~(cpu_data_master_granted_lcd_rd_s1 & cpu_data_master_write);

  assign shifted_address_to_lcd_rd_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //lcd_rd_s1_address mux, which is an e_mux
  assign lcd_rd_s1_address = shifted_address_to_lcd_rd_s1_from_cpu_data_master >> 2;

  //d1_lcd_rd_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_lcd_rd_s1_end_xfer <= 1;
      else 
        d1_lcd_rd_s1_end_xfer <= lcd_rd_s1_end_xfer;
    end


  //lcd_rd_s1_waits_for_read in a cycle, which is an e_mux
  assign lcd_rd_s1_waits_for_read = lcd_rd_s1_in_a_read_cycle & lcd_rd_s1_begins_xfer;

  //lcd_rd_s1_in_a_read_cycle assignment, which is an e_assign
  assign lcd_rd_s1_in_a_read_cycle = cpu_data_master_granted_lcd_rd_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = lcd_rd_s1_in_a_read_cycle;

  //lcd_rd_s1_waits_for_write in a cycle, which is an e_mux
  assign lcd_rd_s1_waits_for_write = lcd_rd_s1_in_a_write_cycle & 0;

  //lcd_rd_s1_in_a_write_cycle assignment, which is an e_assign
  assign lcd_rd_s1_in_a_write_cycle = cpu_data_master_granted_lcd_rd_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = lcd_rd_s1_in_a_write_cycle;

  assign wait_for_lcd_rd_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //lcd_rd/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module lcd_rs_s1_arbitrator (
                              // inputs:
                               clk,
                               cpu_data_master_address_to_slave,
                               cpu_data_master_read,
                               cpu_data_master_waitrequest,
                               cpu_data_master_write,
                               cpu_data_master_writedata,
                               lcd_rs_s1_readdata,
                               reset_n,

                              // outputs:
                               cpu_data_master_granted_lcd_rs_s1,
                               cpu_data_master_qualified_request_lcd_rs_s1,
                               cpu_data_master_read_data_valid_lcd_rs_s1,
                               cpu_data_master_requests_lcd_rs_s1,
                               d1_lcd_rs_s1_end_xfer,
                               lcd_rs_s1_address,
                               lcd_rs_s1_chipselect,
                               lcd_rs_s1_readdata_from_sa,
                               lcd_rs_s1_reset_n,
                               lcd_rs_s1_write_n,
                               lcd_rs_s1_writedata
                            )
;

  output           cpu_data_master_granted_lcd_rs_s1;
  output           cpu_data_master_qualified_request_lcd_rs_s1;
  output           cpu_data_master_read_data_valid_lcd_rs_s1;
  output           cpu_data_master_requests_lcd_rs_s1;
  output           d1_lcd_rs_s1_end_xfer;
  output  [  1: 0] lcd_rs_s1_address;
  output           lcd_rs_s1_chipselect;
  output  [ 31: 0] lcd_rs_s1_readdata_from_sa;
  output           lcd_rs_s1_reset_n;
  output           lcd_rs_s1_write_n;
  output  [ 31: 0] lcd_rs_s1_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] lcd_rs_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_lcd_rs_s1;
  wire             cpu_data_master_qualified_request_lcd_rs_s1;
  wire             cpu_data_master_read_data_valid_lcd_rs_s1;
  wire             cpu_data_master_requests_lcd_rs_s1;
  wire             cpu_data_master_saved_grant_lcd_rs_s1;
  reg              d1_lcd_rs_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_lcd_rs_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] lcd_rs_s1_address;
  wire             lcd_rs_s1_allgrants;
  wire             lcd_rs_s1_allow_new_arb_cycle;
  wire             lcd_rs_s1_any_bursting_master_saved_grant;
  wire             lcd_rs_s1_any_continuerequest;
  wire             lcd_rs_s1_arb_counter_enable;
  reg     [  1: 0] lcd_rs_s1_arb_share_counter;
  wire    [  1: 0] lcd_rs_s1_arb_share_counter_next_value;
  wire    [  1: 0] lcd_rs_s1_arb_share_set_values;
  wire             lcd_rs_s1_beginbursttransfer_internal;
  wire             lcd_rs_s1_begins_xfer;
  wire             lcd_rs_s1_chipselect;
  wire             lcd_rs_s1_end_xfer;
  wire             lcd_rs_s1_firsttransfer;
  wire             lcd_rs_s1_grant_vector;
  wire             lcd_rs_s1_in_a_read_cycle;
  wire             lcd_rs_s1_in_a_write_cycle;
  wire             lcd_rs_s1_master_qreq_vector;
  wire             lcd_rs_s1_non_bursting_master_requests;
  wire    [ 31: 0] lcd_rs_s1_readdata_from_sa;
  reg              lcd_rs_s1_reg_firsttransfer;
  wire             lcd_rs_s1_reset_n;
  reg              lcd_rs_s1_slavearbiterlockenable;
  wire             lcd_rs_s1_slavearbiterlockenable2;
  wire             lcd_rs_s1_unreg_firsttransfer;
  wire             lcd_rs_s1_waits_for_read;
  wire             lcd_rs_s1_waits_for_write;
  wire             lcd_rs_s1_write_n;
  wire    [ 31: 0] lcd_rs_s1_writedata;
  wire    [ 26: 0] shifted_address_to_lcd_rs_s1_from_cpu_data_master;
  wire             wait_for_lcd_rs_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~lcd_rs_s1_end_xfer;
    end


  assign lcd_rs_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_lcd_rs_s1));
  //assign lcd_rs_s1_readdata_from_sa = lcd_rs_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign lcd_rs_s1_readdata_from_sa = lcd_rs_s1_readdata;

  assign cpu_data_master_requests_lcd_rs_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1840) & (cpu_data_master_read | cpu_data_master_write);
  //lcd_rs_s1_arb_share_counter set values, which is an e_mux
  assign lcd_rs_s1_arb_share_set_values = 1;

  //lcd_rs_s1_non_bursting_master_requests mux, which is an e_mux
  assign lcd_rs_s1_non_bursting_master_requests = cpu_data_master_requests_lcd_rs_s1;

  //lcd_rs_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign lcd_rs_s1_any_bursting_master_saved_grant = 0;

  //lcd_rs_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign lcd_rs_s1_arb_share_counter_next_value = lcd_rs_s1_firsttransfer ? (lcd_rs_s1_arb_share_set_values - 1) : |lcd_rs_s1_arb_share_counter ? (lcd_rs_s1_arb_share_counter - 1) : 0;

  //lcd_rs_s1_allgrants all slave grants, which is an e_mux
  assign lcd_rs_s1_allgrants = |lcd_rs_s1_grant_vector;

  //lcd_rs_s1_end_xfer assignment, which is an e_assign
  assign lcd_rs_s1_end_xfer = ~(lcd_rs_s1_waits_for_read | lcd_rs_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_lcd_rs_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_lcd_rs_s1 = lcd_rs_s1_end_xfer & (~lcd_rs_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //lcd_rs_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign lcd_rs_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_lcd_rs_s1 & lcd_rs_s1_allgrants) | (end_xfer_arb_share_counter_term_lcd_rs_s1 & ~lcd_rs_s1_non_bursting_master_requests);

  //lcd_rs_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_rs_s1_arb_share_counter <= 0;
      else if (lcd_rs_s1_arb_counter_enable)
          lcd_rs_s1_arb_share_counter <= lcd_rs_s1_arb_share_counter_next_value;
    end


  //lcd_rs_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_rs_s1_slavearbiterlockenable <= 0;
      else if ((|lcd_rs_s1_master_qreq_vector & end_xfer_arb_share_counter_term_lcd_rs_s1) | (end_xfer_arb_share_counter_term_lcd_rs_s1 & ~lcd_rs_s1_non_bursting_master_requests))
          lcd_rs_s1_slavearbiterlockenable <= |lcd_rs_s1_arb_share_counter_next_value;
    end


  //cpu/data_master lcd_rs/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = lcd_rs_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //lcd_rs_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign lcd_rs_s1_slavearbiterlockenable2 = |lcd_rs_s1_arb_share_counter_next_value;

  //cpu/data_master lcd_rs/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = lcd_rs_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //lcd_rs_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign lcd_rs_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_lcd_rs_s1 = cpu_data_master_requests_lcd_rs_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //lcd_rs_s1_writedata mux, which is an e_mux
  assign lcd_rs_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_lcd_rs_s1 = cpu_data_master_qualified_request_lcd_rs_s1;

  //cpu/data_master saved-grant lcd_rs/s1, which is an e_assign
  assign cpu_data_master_saved_grant_lcd_rs_s1 = cpu_data_master_requests_lcd_rs_s1;

  //allow new arb cycle for lcd_rs/s1, which is an e_assign
  assign lcd_rs_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign lcd_rs_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign lcd_rs_s1_master_qreq_vector = 1;

  //lcd_rs_s1_reset_n assignment, which is an e_assign
  assign lcd_rs_s1_reset_n = reset_n;

  assign lcd_rs_s1_chipselect = cpu_data_master_granted_lcd_rs_s1;
  //lcd_rs_s1_firsttransfer first transaction, which is an e_assign
  assign lcd_rs_s1_firsttransfer = lcd_rs_s1_begins_xfer ? lcd_rs_s1_unreg_firsttransfer : lcd_rs_s1_reg_firsttransfer;

  //lcd_rs_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign lcd_rs_s1_unreg_firsttransfer = ~(lcd_rs_s1_slavearbiterlockenable & lcd_rs_s1_any_continuerequest);

  //lcd_rs_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_rs_s1_reg_firsttransfer <= 1'b1;
      else if (lcd_rs_s1_begins_xfer)
          lcd_rs_s1_reg_firsttransfer <= lcd_rs_s1_unreg_firsttransfer;
    end


  //lcd_rs_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign lcd_rs_s1_beginbursttransfer_internal = lcd_rs_s1_begins_xfer;

  //~lcd_rs_s1_write_n assignment, which is an e_mux
  assign lcd_rs_s1_write_n = ~(cpu_data_master_granted_lcd_rs_s1 & cpu_data_master_write);

  assign shifted_address_to_lcd_rs_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //lcd_rs_s1_address mux, which is an e_mux
  assign lcd_rs_s1_address = shifted_address_to_lcd_rs_s1_from_cpu_data_master >> 2;

  //d1_lcd_rs_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_lcd_rs_s1_end_xfer <= 1;
      else 
        d1_lcd_rs_s1_end_xfer <= lcd_rs_s1_end_xfer;
    end


  //lcd_rs_s1_waits_for_read in a cycle, which is an e_mux
  assign lcd_rs_s1_waits_for_read = lcd_rs_s1_in_a_read_cycle & lcd_rs_s1_begins_xfer;

  //lcd_rs_s1_in_a_read_cycle assignment, which is an e_assign
  assign lcd_rs_s1_in_a_read_cycle = cpu_data_master_granted_lcd_rs_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = lcd_rs_s1_in_a_read_cycle;

  //lcd_rs_s1_waits_for_write in a cycle, which is an e_mux
  assign lcd_rs_s1_waits_for_write = lcd_rs_s1_in_a_write_cycle & 0;

  //lcd_rs_s1_in_a_write_cycle assignment, which is an e_assign
  assign lcd_rs_s1_in_a_write_cycle = cpu_data_master_granted_lcd_rs_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = lcd_rs_s1_in_a_write_cycle;

  assign wait_for_lcd_rs_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //lcd_rs/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module lcd_wr_s1_arbitrator (
                              // inputs:
                               clk,
                               cpu_data_master_address_to_slave,
                               cpu_data_master_read,
                               cpu_data_master_waitrequest,
                               cpu_data_master_write,
                               cpu_data_master_writedata,
                               lcd_wr_s1_readdata,
                               reset_n,

                              // outputs:
                               cpu_data_master_granted_lcd_wr_s1,
                               cpu_data_master_qualified_request_lcd_wr_s1,
                               cpu_data_master_read_data_valid_lcd_wr_s1,
                               cpu_data_master_requests_lcd_wr_s1,
                               d1_lcd_wr_s1_end_xfer,
                               lcd_wr_s1_address,
                               lcd_wr_s1_chipselect,
                               lcd_wr_s1_readdata_from_sa,
                               lcd_wr_s1_reset_n,
                               lcd_wr_s1_write_n,
                               lcd_wr_s1_writedata
                            )
;

  output           cpu_data_master_granted_lcd_wr_s1;
  output           cpu_data_master_qualified_request_lcd_wr_s1;
  output           cpu_data_master_read_data_valid_lcd_wr_s1;
  output           cpu_data_master_requests_lcd_wr_s1;
  output           d1_lcd_wr_s1_end_xfer;
  output  [  1: 0] lcd_wr_s1_address;
  output           lcd_wr_s1_chipselect;
  output  [ 31: 0] lcd_wr_s1_readdata_from_sa;
  output           lcd_wr_s1_reset_n;
  output           lcd_wr_s1_write_n;
  output  [ 31: 0] lcd_wr_s1_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] lcd_wr_s1_readdata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_lcd_wr_s1;
  wire             cpu_data_master_qualified_request_lcd_wr_s1;
  wire             cpu_data_master_read_data_valid_lcd_wr_s1;
  wire             cpu_data_master_requests_lcd_wr_s1;
  wire             cpu_data_master_saved_grant_lcd_wr_s1;
  reg              d1_lcd_wr_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_lcd_wr_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] lcd_wr_s1_address;
  wire             lcd_wr_s1_allgrants;
  wire             lcd_wr_s1_allow_new_arb_cycle;
  wire             lcd_wr_s1_any_bursting_master_saved_grant;
  wire             lcd_wr_s1_any_continuerequest;
  wire             lcd_wr_s1_arb_counter_enable;
  reg     [  1: 0] lcd_wr_s1_arb_share_counter;
  wire    [  1: 0] lcd_wr_s1_arb_share_counter_next_value;
  wire    [  1: 0] lcd_wr_s1_arb_share_set_values;
  wire             lcd_wr_s1_beginbursttransfer_internal;
  wire             lcd_wr_s1_begins_xfer;
  wire             lcd_wr_s1_chipselect;
  wire             lcd_wr_s1_end_xfer;
  wire             lcd_wr_s1_firsttransfer;
  wire             lcd_wr_s1_grant_vector;
  wire             lcd_wr_s1_in_a_read_cycle;
  wire             lcd_wr_s1_in_a_write_cycle;
  wire             lcd_wr_s1_master_qreq_vector;
  wire             lcd_wr_s1_non_bursting_master_requests;
  wire    [ 31: 0] lcd_wr_s1_readdata_from_sa;
  reg              lcd_wr_s1_reg_firsttransfer;
  wire             lcd_wr_s1_reset_n;
  reg              lcd_wr_s1_slavearbiterlockenable;
  wire             lcd_wr_s1_slavearbiterlockenable2;
  wire             lcd_wr_s1_unreg_firsttransfer;
  wire             lcd_wr_s1_waits_for_read;
  wire             lcd_wr_s1_waits_for_write;
  wire             lcd_wr_s1_write_n;
  wire    [ 31: 0] lcd_wr_s1_writedata;
  wire    [ 26: 0] shifted_address_to_lcd_wr_s1_from_cpu_data_master;
  wire             wait_for_lcd_wr_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~lcd_wr_s1_end_xfer;
    end


  assign lcd_wr_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_lcd_wr_s1));
  //assign lcd_wr_s1_readdata_from_sa = lcd_wr_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign lcd_wr_s1_readdata_from_sa = lcd_wr_s1_readdata;

  assign cpu_data_master_requests_lcd_wr_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1870) & (cpu_data_master_read | cpu_data_master_write);
  //lcd_wr_s1_arb_share_counter set values, which is an e_mux
  assign lcd_wr_s1_arb_share_set_values = 1;

  //lcd_wr_s1_non_bursting_master_requests mux, which is an e_mux
  assign lcd_wr_s1_non_bursting_master_requests = cpu_data_master_requests_lcd_wr_s1;

  //lcd_wr_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign lcd_wr_s1_any_bursting_master_saved_grant = 0;

  //lcd_wr_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign lcd_wr_s1_arb_share_counter_next_value = lcd_wr_s1_firsttransfer ? (lcd_wr_s1_arb_share_set_values - 1) : |lcd_wr_s1_arb_share_counter ? (lcd_wr_s1_arb_share_counter - 1) : 0;

  //lcd_wr_s1_allgrants all slave grants, which is an e_mux
  assign lcd_wr_s1_allgrants = |lcd_wr_s1_grant_vector;

  //lcd_wr_s1_end_xfer assignment, which is an e_assign
  assign lcd_wr_s1_end_xfer = ~(lcd_wr_s1_waits_for_read | lcd_wr_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_lcd_wr_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_lcd_wr_s1 = lcd_wr_s1_end_xfer & (~lcd_wr_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //lcd_wr_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign lcd_wr_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_lcd_wr_s1 & lcd_wr_s1_allgrants) | (end_xfer_arb_share_counter_term_lcd_wr_s1 & ~lcd_wr_s1_non_bursting_master_requests);

  //lcd_wr_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_wr_s1_arb_share_counter <= 0;
      else if (lcd_wr_s1_arb_counter_enable)
          lcd_wr_s1_arb_share_counter <= lcd_wr_s1_arb_share_counter_next_value;
    end


  //lcd_wr_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_wr_s1_slavearbiterlockenable <= 0;
      else if ((|lcd_wr_s1_master_qreq_vector & end_xfer_arb_share_counter_term_lcd_wr_s1) | (end_xfer_arb_share_counter_term_lcd_wr_s1 & ~lcd_wr_s1_non_bursting_master_requests))
          lcd_wr_s1_slavearbiterlockenable <= |lcd_wr_s1_arb_share_counter_next_value;
    end


  //cpu/data_master lcd_wr/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = lcd_wr_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //lcd_wr_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign lcd_wr_s1_slavearbiterlockenable2 = |lcd_wr_s1_arb_share_counter_next_value;

  //cpu/data_master lcd_wr/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = lcd_wr_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //lcd_wr_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign lcd_wr_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_lcd_wr_s1 = cpu_data_master_requests_lcd_wr_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //lcd_wr_s1_writedata mux, which is an e_mux
  assign lcd_wr_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_lcd_wr_s1 = cpu_data_master_qualified_request_lcd_wr_s1;

  //cpu/data_master saved-grant lcd_wr/s1, which is an e_assign
  assign cpu_data_master_saved_grant_lcd_wr_s1 = cpu_data_master_requests_lcd_wr_s1;

  //allow new arb cycle for lcd_wr/s1, which is an e_assign
  assign lcd_wr_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign lcd_wr_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign lcd_wr_s1_master_qreq_vector = 1;

  //lcd_wr_s1_reset_n assignment, which is an e_assign
  assign lcd_wr_s1_reset_n = reset_n;

  assign lcd_wr_s1_chipselect = cpu_data_master_granted_lcd_wr_s1;
  //lcd_wr_s1_firsttransfer first transaction, which is an e_assign
  assign lcd_wr_s1_firsttransfer = lcd_wr_s1_begins_xfer ? lcd_wr_s1_unreg_firsttransfer : lcd_wr_s1_reg_firsttransfer;

  //lcd_wr_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign lcd_wr_s1_unreg_firsttransfer = ~(lcd_wr_s1_slavearbiterlockenable & lcd_wr_s1_any_continuerequest);

  //lcd_wr_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          lcd_wr_s1_reg_firsttransfer <= 1'b1;
      else if (lcd_wr_s1_begins_xfer)
          lcd_wr_s1_reg_firsttransfer <= lcd_wr_s1_unreg_firsttransfer;
    end


  //lcd_wr_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign lcd_wr_s1_beginbursttransfer_internal = lcd_wr_s1_begins_xfer;

  //~lcd_wr_s1_write_n assignment, which is an e_mux
  assign lcd_wr_s1_write_n = ~(cpu_data_master_granted_lcd_wr_s1 & cpu_data_master_write);

  assign shifted_address_to_lcd_wr_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //lcd_wr_s1_address mux, which is an e_mux
  assign lcd_wr_s1_address = shifted_address_to_lcd_wr_s1_from_cpu_data_master >> 2;

  //d1_lcd_wr_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_lcd_wr_s1_end_xfer <= 1;
      else 
        d1_lcd_wr_s1_end_xfer <= lcd_wr_s1_end_xfer;
    end


  //lcd_wr_s1_waits_for_read in a cycle, which is an e_mux
  assign lcd_wr_s1_waits_for_read = lcd_wr_s1_in_a_read_cycle & lcd_wr_s1_begins_xfer;

  //lcd_wr_s1_in_a_read_cycle assignment, which is an e_assign
  assign lcd_wr_s1_in_a_read_cycle = cpu_data_master_granted_lcd_wr_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = lcd_wr_s1_in_a_read_cycle;

  //lcd_wr_s1_waits_for_write in a cycle, which is an e_mux
  assign lcd_wr_s1_waits_for_write = lcd_wr_s1_in_a_write_cycle & 0;

  //lcd_wr_s1_in_a_write_cycle assignment, which is an e_assign
  assign lcd_wr_s1_in_a_write_cycle = cpu_data_master_granted_lcd_wr_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = lcd_wr_s1_in_a_write_cycle;

  assign wait_for_lcd_wr_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //lcd_wr/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module reset_s1_arbitrator (
                             // inputs:
                              clk,
                              cpu_data_master_address_to_slave,
                              cpu_data_master_read,
                              cpu_data_master_waitrequest,
                              cpu_data_master_write,
                              cpu_data_master_writedata,
                              reset_n,
                              reset_s1_readdata,

                             // outputs:
                              cpu_data_master_granted_reset_s1,
                              cpu_data_master_qualified_request_reset_s1,
                              cpu_data_master_read_data_valid_reset_s1,
                              cpu_data_master_requests_reset_s1,
                              d1_reset_s1_end_xfer,
                              reset_s1_address,
                              reset_s1_chipselect,
                              reset_s1_readdata_from_sa,
                              reset_s1_reset_n,
                              reset_s1_write_n,
                              reset_s1_writedata
                           )
;

  output           cpu_data_master_granted_reset_s1;
  output           cpu_data_master_qualified_request_reset_s1;
  output           cpu_data_master_read_data_valid_reset_s1;
  output           cpu_data_master_requests_reset_s1;
  output           d1_reset_s1_end_xfer;
  output  [  1: 0] reset_s1_address;
  output           reset_s1_chipselect;
  output  [ 31: 0] reset_s1_readdata_from_sa;
  output           reset_s1_reset_n;
  output           reset_s1_write_n;
  output  [ 31: 0] reset_s1_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] reset_s1_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_reset_s1;
  wire             cpu_data_master_qualified_request_reset_s1;
  wire             cpu_data_master_read_data_valid_reset_s1;
  wire             cpu_data_master_requests_reset_s1;
  wire             cpu_data_master_saved_grant_reset_s1;
  reg              d1_reasons_to_wait;
  reg              d1_reset_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_reset_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] reset_s1_address;
  wire             reset_s1_allgrants;
  wire             reset_s1_allow_new_arb_cycle;
  wire             reset_s1_any_bursting_master_saved_grant;
  wire             reset_s1_any_continuerequest;
  wire             reset_s1_arb_counter_enable;
  reg     [  1: 0] reset_s1_arb_share_counter;
  wire    [  1: 0] reset_s1_arb_share_counter_next_value;
  wire    [  1: 0] reset_s1_arb_share_set_values;
  wire             reset_s1_beginbursttransfer_internal;
  wire             reset_s1_begins_xfer;
  wire             reset_s1_chipselect;
  wire             reset_s1_end_xfer;
  wire             reset_s1_firsttransfer;
  wire             reset_s1_grant_vector;
  wire             reset_s1_in_a_read_cycle;
  wire             reset_s1_in_a_write_cycle;
  wire             reset_s1_master_qreq_vector;
  wire             reset_s1_non_bursting_master_requests;
  wire    [ 31: 0] reset_s1_readdata_from_sa;
  reg              reset_s1_reg_firsttransfer;
  wire             reset_s1_reset_n;
  reg              reset_s1_slavearbiterlockenable;
  wire             reset_s1_slavearbiterlockenable2;
  wire             reset_s1_unreg_firsttransfer;
  wire             reset_s1_waits_for_read;
  wire             reset_s1_waits_for_write;
  wire             reset_s1_write_n;
  wire    [ 31: 0] reset_s1_writedata;
  wire    [ 26: 0] shifted_address_to_reset_s1_from_cpu_data_master;
  wire             wait_for_reset_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~reset_s1_end_xfer;
    end


  assign reset_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_reset_s1));
  //assign reset_s1_readdata_from_sa = reset_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign reset_s1_readdata_from_sa = reset_s1_readdata;

  assign cpu_data_master_requests_reset_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1860) & (cpu_data_master_read | cpu_data_master_write);
  //reset_s1_arb_share_counter set values, which is an e_mux
  assign reset_s1_arb_share_set_values = 1;

  //reset_s1_non_bursting_master_requests mux, which is an e_mux
  assign reset_s1_non_bursting_master_requests = cpu_data_master_requests_reset_s1;

  //reset_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign reset_s1_any_bursting_master_saved_grant = 0;

  //reset_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign reset_s1_arb_share_counter_next_value = reset_s1_firsttransfer ? (reset_s1_arb_share_set_values - 1) : |reset_s1_arb_share_counter ? (reset_s1_arb_share_counter - 1) : 0;

  //reset_s1_allgrants all slave grants, which is an e_mux
  assign reset_s1_allgrants = |reset_s1_grant_vector;

  //reset_s1_end_xfer assignment, which is an e_assign
  assign reset_s1_end_xfer = ~(reset_s1_waits_for_read | reset_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_reset_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_reset_s1 = reset_s1_end_xfer & (~reset_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //reset_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign reset_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_reset_s1 & reset_s1_allgrants) | (end_xfer_arb_share_counter_term_reset_s1 & ~reset_s1_non_bursting_master_requests);

  //reset_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          reset_s1_arb_share_counter <= 0;
      else if (reset_s1_arb_counter_enable)
          reset_s1_arb_share_counter <= reset_s1_arb_share_counter_next_value;
    end


  //reset_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          reset_s1_slavearbiterlockenable <= 0;
      else if ((|reset_s1_master_qreq_vector & end_xfer_arb_share_counter_term_reset_s1) | (end_xfer_arb_share_counter_term_reset_s1 & ~reset_s1_non_bursting_master_requests))
          reset_s1_slavearbiterlockenable <= |reset_s1_arb_share_counter_next_value;
    end


  //cpu/data_master reset/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = reset_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //reset_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign reset_s1_slavearbiterlockenable2 = |reset_s1_arb_share_counter_next_value;

  //cpu/data_master reset/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = reset_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //reset_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign reset_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_reset_s1 = cpu_data_master_requests_reset_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //reset_s1_writedata mux, which is an e_mux
  assign reset_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_reset_s1 = cpu_data_master_qualified_request_reset_s1;

  //cpu/data_master saved-grant reset/s1, which is an e_assign
  assign cpu_data_master_saved_grant_reset_s1 = cpu_data_master_requests_reset_s1;

  //allow new arb cycle for reset/s1, which is an e_assign
  assign reset_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign reset_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign reset_s1_master_qreq_vector = 1;

  //reset_s1_reset_n assignment, which is an e_assign
  assign reset_s1_reset_n = reset_n;

  assign reset_s1_chipselect = cpu_data_master_granted_reset_s1;
  //reset_s1_firsttransfer first transaction, which is an e_assign
  assign reset_s1_firsttransfer = reset_s1_begins_xfer ? reset_s1_unreg_firsttransfer : reset_s1_reg_firsttransfer;

  //reset_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign reset_s1_unreg_firsttransfer = ~(reset_s1_slavearbiterlockenable & reset_s1_any_continuerequest);

  //reset_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          reset_s1_reg_firsttransfer <= 1'b1;
      else if (reset_s1_begins_xfer)
          reset_s1_reg_firsttransfer <= reset_s1_unreg_firsttransfer;
    end


  //reset_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign reset_s1_beginbursttransfer_internal = reset_s1_begins_xfer;

  //~reset_s1_write_n assignment, which is an e_mux
  assign reset_s1_write_n = ~(cpu_data_master_granted_reset_s1 & cpu_data_master_write);

  assign shifted_address_to_reset_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //reset_s1_address mux, which is an e_mux
  assign reset_s1_address = shifted_address_to_reset_s1_from_cpu_data_master >> 2;

  //d1_reset_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reset_s1_end_xfer <= 1;
      else 
        d1_reset_s1_end_xfer <= reset_s1_end_xfer;
    end


  //reset_s1_waits_for_read in a cycle, which is an e_mux
  assign reset_s1_waits_for_read = reset_s1_in_a_read_cycle & reset_s1_begins_xfer;

  //reset_s1_in_a_read_cycle assignment, which is an e_assign
  assign reset_s1_in_a_read_cycle = cpu_data_master_granted_reset_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = reset_s1_in_a_read_cycle;

  //reset_s1_waits_for_write in a cycle, which is an e_mux
  assign reset_s1_waits_for_write = reset_s1_in_a_write_cycle & 0;

  //reset_s1_in_a_write_cycle assignment, which is an e_assign
  assign reset_s1_in_a_write_cycle = cpu_data_master_granted_reset_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = reset_s1_in_a_write_cycle;

  assign wait_for_reset_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //reset/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_data_master_to_sdram_s1_module (
                                                         // inputs:
                                                          clear_fifo,
                                                          clk,
                                                          data_in,
                                                          read,
                                                          reset_n,
                                                          sync_reset,
                                                          write,

                                                         // outputs:
                                                          data_out,
                                                          empty,
                                                          fifo_contains_ones_n,
                                                          full
                                                       )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  wire             full_7;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  wire             p4_full_4;
  wire             p4_stage_4;
  wire             p5_full_5;
  wire             p5_stage_5;
  wire             p6_full_6;
  wire             p6_stage_6;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  reg              stage_4;
  reg              stage_5;
  reg              stage_6;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_6;
  assign empty = !full_0;
  assign full_7 = 0;
  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    0;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module (
                                                                // inputs:
                                                                 clear_fifo,
                                                                 clk,
                                                                 data_in,
                                                                 read,
                                                                 reset_n,
                                                                 sync_reset,
                                                                 write,

                                                                // outputs:
                                                                 data_out,
                                                                 empty,
                                                                 fifo_contains_ones_n,
                                                                 full
                                                              )
;

  output           data_out;
  output           empty;
  output           fifo_contains_ones_n;
  output           full;
  input            clear_fifo;
  input            clk;
  input            data_in;
  input            read;
  input            reset_n;
  input            sync_reset;
  input            write;

  wire             data_out;
  wire             empty;
  reg              fifo_contains_ones_n;
  wire             full;
  reg              full_0;
  reg              full_1;
  reg              full_2;
  reg              full_3;
  reg              full_4;
  reg              full_5;
  reg              full_6;
  wire             full_7;
  reg     [  3: 0] how_many_ones;
  wire    [  3: 0] one_count_minus_one;
  wire    [  3: 0] one_count_plus_one;
  wire             p0_full_0;
  wire             p0_stage_0;
  wire             p1_full_1;
  wire             p1_stage_1;
  wire             p2_full_2;
  wire             p2_stage_2;
  wire             p3_full_3;
  wire             p3_stage_3;
  wire             p4_full_4;
  wire             p4_stage_4;
  wire             p5_full_5;
  wire             p5_stage_5;
  wire             p6_full_6;
  wire             p6_stage_6;
  reg              stage_0;
  reg              stage_1;
  reg              stage_2;
  reg              stage_3;
  reg              stage_4;
  reg              stage_5;
  reg              stage_6;
  wire    [  3: 0] updated_one_count;
  assign data_out = stage_0;
  assign full = full_6;
  assign empty = !full_0;
  assign full_7 = 0;
  //data_6, which is an e_mux
  assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
    data_in;

  //data_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_6 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_6))
          if (sync_reset & full_6 & !((full_7 == 0) & read & write))
              stage_6 <= 0;
          else 
            stage_6 <= p6_stage_6;
    end


  //control_6, which is an e_mux
  assign p6_full_6 = ((read & !write) == 0)? full_5 :
    0;

  //control_reg_6, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_6 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_6 <= 0;
          else 
            full_6 <= p6_full_6;
    end


  //data_5, which is an e_mux
  assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
    stage_6;

  //data_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_5 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_5))
          if (sync_reset & full_5 & !((full_6 == 0) & read & write))
              stage_5 <= 0;
          else 
            stage_5 <= p5_stage_5;
    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sdram_s1_arbitrator (
                             // inputs:
                              clk,
                              cpu_data_master_address_to_slave,
                              cpu_data_master_byteenable,
                              cpu_data_master_dbs_address,
                              cpu_data_master_dbs_write_16,
                              cpu_data_master_no_byte_enables_and_last_term,
                              cpu_data_master_read,
                              cpu_data_master_waitrequest,
                              cpu_data_master_write,
                              cpu_instruction_master_address_to_slave,
                              cpu_instruction_master_dbs_address,
                              cpu_instruction_master_latency_counter,
                              cpu_instruction_master_read,
                              reset_n,
                              sdram_s1_readdata,
                              sdram_s1_readdatavalid,
                              sdram_s1_waitrequest,

                             // outputs:
                              cpu_data_master_byteenable_sdram_s1,
                              cpu_data_master_granted_sdram_s1,
                              cpu_data_master_qualified_request_sdram_s1,
                              cpu_data_master_read_data_valid_sdram_s1,
                              cpu_data_master_read_data_valid_sdram_s1_shift_register,
                              cpu_data_master_requests_sdram_s1,
                              cpu_instruction_master_granted_sdram_s1,
                              cpu_instruction_master_qualified_request_sdram_s1,
                              cpu_instruction_master_read_data_valid_sdram_s1,
                              cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                              cpu_instruction_master_requests_sdram_s1,
                              d1_sdram_s1_end_xfer,
                              sdram_s1_address,
                              sdram_s1_byteenable_n,
                              sdram_s1_chipselect,
                              sdram_s1_read_n,
                              sdram_s1_readdata_from_sa,
                              sdram_s1_reset_n,
                              sdram_s1_waitrequest_from_sa,
                              sdram_s1_write_n,
                              sdram_s1_writedata
                           )
;

  output  [  1: 0] cpu_data_master_byteenable_sdram_s1;
  output           cpu_data_master_granted_sdram_s1;
  output           cpu_data_master_qualified_request_sdram_s1;
  output           cpu_data_master_read_data_valid_sdram_s1;
  output           cpu_data_master_read_data_valid_sdram_s1_shift_register;
  output           cpu_data_master_requests_sdram_s1;
  output           cpu_instruction_master_granted_sdram_s1;
  output           cpu_instruction_master_qualified_request_sdram_s1;
  output           cpu_instruction_master_read_data_valid_sdram_s1;
  output           cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  output           cpu_instruction_master_requests_sdram_s1;
  output           d1_sdram_s1_end_xfer;
  output  [ 23: 0] sdram_s1_address;
  output  [  1: 0] sdram_s1_byteenable_n;
  output           sdram_s1_chipselect;
  output           sdram_s1_read_n;
  output  [ 15: 0] sdram_s1_readdata_from_sa;
  output           sdram_s1_reset_n;
  output           sdram_s1_waitrequest_from_sa;
  output           sdram_s1_write_n;
  output  [ 15: 0] sdram_s1_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_dbs_address;
  input   [ 15: 0] cpu_data_master_dbs_write_16;
  input            cpu_data_master_no_byte_enables_and_last_term;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 26: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_dbs_address;
  input            cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            reset_n;
  input   [ 15: 0] sdram_s1_readdata;
  input            sdram_s1_readdatavalid;
  input            sdram_s1_waitrequest;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire    [  1: 0] cpu_data_master_byteenable_sdram_s1;
  wire    [  1: 0] cpu_data_master_byteenable_sdram_s1_segment_0;
  wire    [  1: 0] cpu_data_master_byteenable_sdram_s1_segment_1;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sdram_s1;
  wire             cpu_data_master_qualified_request_sdram_s1;
  wire             cpu_data_master_rdv_fifo_empty_sdram_s1;
  wire             cpu_data_master_rdv_fifo_output_from_sdram_s1;
  wire             cpu_data_master_read_data_valid_sdram_s1;
  wire             cpu_data_master_read_data_valid_sdram_s1_shift_register;
  wire             cpu_data_master_requests_sdram_s1;
  wire             cpu_data_master_saved_grant_sdram_s1;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_sdram_s1;
  wire             cpu_instruction_master_qualified_request_sdram_s1;
  wire             cpu_instruction_master_rdv_fifo_empty_sdram_s1;
  wire             cpu_instruction_master_rdv_fifo_output_from_sdram_s1;
  wire             cpu_instruction_master_read_data_valid_sdram_s1;
  wire             cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  wire             cpu_instruction_master_requests_sdram_s1;
  wire             cpu_instruction_master_saved_grant_sdram_s1;
  reg              d1_reasons_to_wait;
  reg              d1_sdram_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sdram_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_sdram_s1;
  reg              last_cycle_cpu_instruction_master_granted_slave_sdram_s1;
  wire    [ 23: 0] sdram_s1_address;
  wire             sdram_s1_allgrants;
  wire             sdram_s1_allow_new_arb_cycle;
  wire             sdram_s1_any_bursting_master_saved_grant;
  wire             sdram_s1_any_continuerequest;
  reg     [  1: 0] sdram_s1_arb_addend;
  wire             sdram_s1_arb_counter_enable;
  reg     [  1: 0] sdram_s1_arb_share_counter;
  wire    [  1: 0] sdram_s1_arb_share_counter_next_value;
  wire    [  1: 0] sdram_s1_arb_share_set_values;
  wire    [  1: 0] sdram_s1_arb_winner;
  wire             sdram_s1_arbitration_holdoff_internal;
  wire             sdram_s1_beginbursttransfer_internal;
  wire             sdram_s1_begins_xfer;
  wire    [  1: 0] sdram_s1_byteenable_n;
  wire             sdram_s1_chipselect;
  wire    [  3: 0] sdram_s1_chosen_master_double_vector;
  wire    [  1: 0] sdram_s1_chosen_master_rot_left;
  wire             sdram_s1_end_xfer;
  wire             sdram_s1_firsttransfer;
  wire    [  1: 0] sdram_s1_grant_vector;
  wire             sdram_s1_in_a_read_cycle;
  wire             sdram_s1_in_a_write_cycle;
  wire    [  1: 0] sdram_s1_master_qreq_vector;
  wire             sdram_s1_move_on_to_next_transaction;
  wire             sdram_s1_non_bursting_master_requests;
  wire             sdram_s1_read_n;
  wire    [ 15: 0] sdram_s1_readdata_from_sa;
  wire             sdram_s1_readdatavalid_from_sa;
  reg              sdram_s1_reg_firsttransfer;
  wire             sdram_s1_reset_n;
  reg     [  1: 0] sdram_s1_saved_chosen_master_vector;
  reg              sdram_s1_slavearbiterlockenable;
  wire             sdram_s1_slavearbiterlockenable2;
  wire             sdram_s1_unreg_firsttransfer;
  wire             sdram_s1_waitrequest_from_sa;
  wire             sdram_s1_waits_for_read;
  wire             sdram_s1_waits_for_write;
  wire             sdram_s1_write_n;
  wire    [ 15: 0] sdram_s1_writedata;
  wire    [ 26: 0] shifted_address_to_sdram_s1_from_cpu_data_master;
  wire    [ 26: 0] shifted_address_to_sdram_s1_from_cpu_instruction_master;
  wire             wait_for_sdram_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sdram_s1_end_xfer;
    end


  assign sdram_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sdram_s1 | cpu_instruction_master_qualified_request_sdram_s1));
  //assign sdram_s1_readdatavalid_from_sa = sdram_s1_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_s1_readdatavalid_from_sa = sdram_s1_readdatavalid;

  //assign sdram_s1_readdata_from_sa = sdram_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_s1_readdata_from_sa = sdram_s1_readdata;

  assign cpu_data_master_requests_sdram_s1 = ({cpu_data_master_address_to_slave[26 : 25] , 25'b0} == 27'h4000000) & (cpu_data_master_read | cpu_data_master_write);
  //assign sdram_s1_waitrequest_from_sa = sdram_s1_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sdram_s1_waitrequest_from_sa = sdram_s1_waitrequest;

  //sdram_s1_arb_share_counter set values, which is an e_mux
  assign sdram_s1_arb_share_set_values = (cpu_data_master_granted_sdram_s1)? 2 :
    (cpu_instruction_master_granted_sdram_s1)? 2 :
    (cpu_data_master_granted_sdram_s1)? 2 :
    (cpu_instruction_master_granted_sdram_s1)? 2 :
    1;

  //sdram_s1_non_bursting_master_requests mux, which is an e_mux
  assign sdram_s1_non_bursting_master_requests = cpu_data_master_requests_sdram_s1 |
    cpu_instruction_master_requests_sdram_s1 |
    cpu_data_master_requests_sdram_s1 |
    cpu_instruction_master_requests_sdram_s1;

  //sdram_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign sdram_s1_any_bursting_master_saved_grant = 0;

  //sdram_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign sdram_s1_arb_share_counter_next_value = sdram_s1_firsttransfer ? (sdram_s1_arb_share_set_values - 1) : |sdram_s1_arb_share_counter ? (sdram_s1_arb_share_counter - 1) : 0;

  //sdram_s1_allgrants all slave grants, which is an e_mux
  assign sdram_s1_allgrants = (|sdram_s1_grant_vector) |
    (|sdram_s1_grant_vector) |
    (|sdram_s1_grant_vector) |
    (|sdram_s1_grant_vector);

  //sdram_s1_end_xfer assignment, which is an e_assign
  assign sdram_s1_end_xfer = ~(sdram_s1_waits_for_read | sdram_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_sdram_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sdram_s1 = sdram_s1_end_xfer & (~sdram_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sdram_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign sdram_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_sdram_s1 & sdram_s1_allgrants) | (end_xfer_arb_share_counter_term_sdram_s1 & ~sdram_s1_non_bursting_master_requests);

  //sdram_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_arb_share_counter <= 0;
      else if (sdram_s1_arb_counter_enable)
          sdram_s1_arb_share_counter <= sdram_s1_arb_share_counter_next_value;
    end


  //sdram_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_slavearbiterlockenable <= 0;
      else if ((|sdram_s1_master_qreq_vector & end_xfer_arb_share_counter_term_sdram_s1) | (end_xfer_arb_share_counter_term_sdram_s1 & ~sdram_s1_non_bursting_master_requests))
          sdram_s1_slavearbiterlockenable <= |sdram_s1_arb_share_counter_next_value;
    end


  //cpu/data_master sdram/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sdram_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sdram_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sdram_s1_slavearbiterlockenable2 = |sdram_s1_arb_share_counter_next_value;

  //cpu/data_master sdram/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sdram_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master sdram/s1 arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = sdram_s1_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master sdram/s1 arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = sdram_s1_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted sdram/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_sdram_s1 <= 0;
      else 
        last_cycle_cpu_instruction_master_granted_slave_sdram_s1 <= cpu_instruction_master_saved_grant_sdram_s1 ? 1 : (sdram_s1_arbitration_holdoff_internal | ~cpu_instruction_master_requests_sdram_s1) ? 0 : last_cycle_cpu_instruction_master_granted_slave_sdram_s1;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & cpu_instruction_master_requests_sdram_s1;

  //sdram_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  assign sdram_s1_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_sdram_s1 = cpu_data_master_requests_sdram_s1 & ~((cpu_data_master_read & (~cpu_data_master_waitrequest | (|cpu_data_master_read_data_valid_sdram_s1_shift_register))) | ((~cpu_data_master_waitrequest | cpu_data_master_no_byte_enables_and_last_term | !cpu_data_master_byteenable_sdram_s1) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //unique name for sdram_s1_move_on_to_next_transaction, which is an e_assign
  assign sdram_s1_move_on_to_next_transaction = sdram_s1_readdatavalid_from_sa;

  //rdv_fifo_for_cpu_data_master_to_sdram_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_data_master_to_sdram_s1_module rdv_fifo_for_cpu_data_master_to_sdram_s1
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_data_master_granted_sdram_s1),
      .data_out             (cpu_data_master_rdv_fifo_output_from_sdram_s1),
      .empty                (),
      .fifo_contains_ones_n (cpu_data_master_rdv_fifo_empty_sdram_s1),
      .full                 (),
      .read                 (sdram_s1_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~sdram_s1_waits_for_read)
    );

  assign cpu_data_master_read_data_valid_sdram_s1_shift_register = ~cpu_data_master_rdv_fifo_empty_sdram_s1;
  //local readdatavalid cpu_data_master_read_data_valid_sdram_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_sdram_s1 = (sdram_s1_readdatavalid_from_sa & cpu_data_master_rdv_fifo_output_from_sdram_s1) & ~ cpu_data_master_rdv_fifo_empty_sdram_s1;

  //sdram_s1_writedata mux, which is an e_mux
  assign sdram_s1_writedata = cpu_data_master_dbs_write_16;

  assign cpu_instruction_master_requests_sdram_s1 = (({cpu_instruction_master_address_to_slave[26 : 25] , 25'b0} == 27'h4000000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted sdram/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_sdram_s1 <= 0;
      else 
        last_cycle_cpu_data_master_granted_slave_sdram_s1 <= cpu_data_master_saved_grant_sdram_s1 ? 1 : (sdram_s1_arbitration_holdoff_internal | ~cpu_data_master_requests_sdram_s1) ? 0 : last_cycle_cpu_data_master_granted_slave_sdram_s1;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_sdram_s1 & cpu_data_master_requests_sdram_s1;

  assign cpu_instruction_master_qualified_request_sdram_s1 = cpu_instruction_master_requests_sdram_s1 & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0) | (1 < cpu_instruction_master_latency_counter))) | cpu_data_master_arbiterlock);
  //rdv_fifo_for_cpu_instruction_master_to_sdram_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module rdv_fifo_for_cpu_instruction_master_to_sdram_s1
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (cpu_instruction_master_granted_sdram_s1),
      .data_out             (cpu_instruction_master_rdv_fifo_output_from_sdram_s1),
      .empty                (),
      .fifo_contains_ones_n (cpu_instruction_master_rdv_fifo_empty_sdram_s1),
      .full                 (),
      .read                 (sdram_s1_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~sdram_s1_waits_for_read)
    );

  assign cpu_instruction_master_read_data_valid_sdram_s1_shift_register = ~cpu_instruction_master_rdv_fifo_empty_sdram_s1;
  //local readdatavalid cpu_instruction_master_read_data_valid_sdram_s1, which is an e_mux
  assign cpu_instruction_master_read_data_valid_sdram_s1 = (sdram_s1_readdatavalid_from_sa & cpu_instruction_master_rdv_fifo_output_from_sdram_s1) & ~ cpu_instruction_master_rdv_fifo_empty_sdram_s1;

  //allow new arb cycle for sdram/s1, which is an e_assign
  assign sdram_s1_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for sdram/s1, which is an e_assign
  assign sdram_s1_master_qreq_vector[0] = cpu_instruction_master_qualified_request_sdram_s1;

  //cpu/instruction_master grant sdram/s1, which is an e_assign
  assign cpu_instruction_master_granted_sdram_s1 = sdram_s1_grant_vector[0];

  //cpu/instruction_master saved-grant sdram/s1, which is an e_assign
  assign cpu_instruction_master_saved_grant_sdram_s1 = sdram_s1_arb_winner[0] && cpu_instruction_master_requests_sdram_s1;

  //cpu/data_master assignment into master qualified-requests vector for sdram/s1, which is an e_assign
  assign sdram_s1_master_qreq_vector[1] = cpu_data_master_qualified_request_sdram_s1;

  //cpu/data_master grant sdram/s1, which is an e_assign
  assign cpu_data_master_granted_sdram_s1 = sdram_s1_grant_vector[1];

  //cpu/data_master saved-grant sdram/s1, which is an e_assign
  assign cpu_data_master_saved_grant_sdram_s1 = sdram_s1_arb_winner[1] && cpu_data_master_requests_sdram_s1;

  //sdram/s1 chosen-master double-vector, which is an e_assign
  assign sdram_s1_chosen_master_double_vector = {sdram_s1_master_qreq_vector, sdram_s1_master_qreq_vector} & ({~sdram_s1_master_qreq_vector, ~sdram_s1_master_qreq_vector} + sdram_s1_arb_addend);

  //stable onehot encoding of arb winner
  assign sdram_s1_arb_winner = (sdram_s1_allow_new_arb_cycle & | sdram_s1_grant_vector) ? sdram_s1_grant_vector : sdram_s1_saved_chosen_master_vector;

  //saved sdram_s1_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_saved_chosen_master_vector <= 0;
      else if (sdram_s1_allow_new_arb_cycle)
          sdram_s1_saved_chosen_master_vector <= |sdram_s1_grant_vector ? sdram_s1_grant_vector : sdram_s1_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign sdram_s1_grant_vector = {(sdram_s1_chosen_master_double_vector[1] | sdram_s1_chosen_master_double_vector[3]),
    (sdram_s1_chosen_master_double_vector[0] | sdram_s1_chosen_master_double_vector[2])};

  //sdram/s1 chosen master rotated left, which is an e_assign
  assign sdram_s1_chosen_master_rot_left = (sdram_s1_arb_winner << 1) ? (sdram_s1_arb_winner << 1) : 1;

  //sdram/s1's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_arb_addend <= 1;
      else if (|sdram_s1_grant_vector)
          sdram_s1_arb_addend <= sdram_s1_end_xfer? sdram_s1_chosen_master_rot_left : sdram_s1_grant_vector;
    end


  //sdram_s1_reset_n assignment, which is an e_assign
  assign sdram_s1_reset_n = reset_n;

  assign sdram_s1_chipselect = cpu_data_master_granted_sdram_s1 | cpu_instruction_master_granted_sdram_s1;
  //sdram_s1_firsttransfer first transaction, which is an e_assign
  assign sdram_s1_firsttransfer = sdram_s1_begins_xfer ? sdram_s1_unreg_firsttransfer : sdram_s1_reg_firsttransfer;

  //sdram_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign sdram_s1_unreg_firsttransfer = ~(sdram_s1_slavearbiterlockenable & sdram_s1_any_continuerequest);

  //sdram_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sdram_s1_reg_firsttransfer <= 1'b1;
      else if (sdram_s1_begins_xfer)
          sdram_s1_reg_firsttransfer <= sdram_s1_unreg_firsttransfer;
    end


  //sdram_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sdram_s1_beginbursttransfer_internal = sdram_s1_begins_xfer;

  //sdram_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign sdram_s1_arbitration_holdoff_internal = sdram_s1_begins_xfer & sdram_s1_firsttransfer;

  //~sdram_s1_read_n assignment, which is an e_mux
  assign sdram_s1_read_n = ~((cpu_data_master_granted_sdram_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_sdram_s1 & cpu_instruction_master_read));

  //~sdram_s1_write_n assignment, which is an e_mux
  assign sdram_s1_write_n = ~(cpu_data_master_granted_sdram_s1 & cpu_data_master_write);

  assign shifted_address_to_sdram_s1_from_cpu_data_master = {cpu_data_master_address_to_slave >> 2,
    cpu_data_master_dbs_address[1],
    {1 {1'b0}}};

  //sdram_s1_address mux, which is an e_mux
  assign sdram_s1_address = (cpu_data_master_granted_sdram_s1)? (shifted_address_to_sdram_s1_from_cpu_data_master >> 1) :
    (shifted_address_to_sdram_s1_from_cpu_instruction_master >> 1);

  assign shifted_address_to_sdram_s1_from_cpu_instruction_master = {cpu_instruction_master_address_to_slave >> 2,
    cpu_instruction_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_sdram_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sdram_s1_end_xfer <= 1;
      else 
        d1_sdram_s1_end_xfer <= sdram_s1_end_xfer;
    end


  //sdram_s1_waits_for_read in a cycle, which is an e_mux
  assign sdram_s1_waits_for_read = sdram_s1_in_a_read_cycle & sdram_s1_waitrequest_from_sa;

  //sdram_s1_in_a_read_cycle assignment, which is an e_assign
  assign sdram_s1_in_a_read_cycle = (cpu_data_master_granted_sdram_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_sdram_s1 & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sdram_s1_in_a_read_cycle;

  //sdram_s1_waits_for_write in a cycle, which is an e_mux
  assign sdram_s1_waits_for_write = sdram_s1_in_a_write_cycle & sdram_s1_waitrequest_from_sa;

  //sdram_s1_in_a_write_cycle assignment, which is an e_assign
  assign sdram_s1_in_a_write_cycle = cpu_data_master_granted_sdram_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sdram_s1_in_a_write_cycle;

  assign wait_for_sdram_s1_counter = 0;
  //~sdram_s1_byteenable_n byte enable port mux, which is an e_mux
  assign sdram_s1_byteenable_n = ~((cpu_data_master_granted_sdram_s1)? cpu_data_master_byteenable_sdram_s1 :
    -1);

  assign {cpu_data_master_byteenable_sdram_s1_segment_1,
cpu_data_master_byteenable_sdram_s1_segment_0} = cpu_data_master_byteenable;
  assign cpu_data_master_byteenable_sdram_s1 = ((cpu_data_master_dbs_address[1] == 0))? cpu_data_master_byteenable_sdram_s1_segment_0 :
    cpu_data_master_byteenable_sdram_s1_segment_1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sdram/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_sdram_s1 + cpu_instruction_master_granted_sdram_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_sdram_s1 + cpu_instruction_master_saved_grant_sdram_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module spi_touch_spi_control_port_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_data_master_address_to_slave,
                                                cpu_data_master_read,
                                                cpu_data_master_write,
                                                cpu_data_master_writedata,
                                                reset_n,
                                                spi_touch_spi_control_port_dataavailable,
                                                spi_touch_spi_control_port_endofpacket,
                                                spi_touch_spi_control_port_irq,
                                                spi_touch_spi_control_port_readdata,
                                                spi_touch_spi_control_port_readyfordata,

                                               // outputs:
                                                cpu_data_master_granted_spi_touch_spi_control_port,
                                                cpu_data_master_qualified_request_spi_touch_spi_control_port,
                                                cpu_data_master_read_data_valid_spi_touch_spi_control_port,
                                                cpu_data_master_requests_spi_touch_spi_control_port,
                                                d1_spi_touch_spi_control_port_end_xfer,
                                                spi_touch_spi_control_port_address,
                                                spi_touch_spi_control_port_chipselect,
                                                spi_touch_spi_control_port_dataavailable_from_sa,
                                                spi_touch_spi_control_port_endofpacket_from_sa,
                                                spi_touch_spi_control_port_irq_from_sa,
                                                spi_touch_spi_control_port_read_n,
                                                spi_touch_spi_control_port_readdata_from_sa,
                                                spi_touch_spi_control_port_readyfordata_from_sa,
                                                spi_touch_spi_control_port_reset_n,
                                                spi_touch_spi_control_port_write_n,
                                                spi_touch_spi_control_port_writedata
                                             )
;

  output           cpu_data_master_granted_spi_touch_spi_control_port;
  output           cpu_data_master_qualified_request_spi_touch_spi_control_port;
  output           cpu_data_master_read_data_valid_spi_touch_spi_control_port;
  output           cpu_data_master_requests_spi_touch_spi_control_port;
  output           d1_spi_touch_spi_control_port_end_xfer;
  output  [  2: 0] spi_touch_spi_control_port_address;
  output           spi_touch_spi_control_port_chipselect;
  output           spi_touch_spi_control_port_dataavailable_from_sa;
  output           spi_touch_spi_control_port_endofpacket_from_sa;
  output           spi_touch_spi_control_port_irq_from_sa;
  output           spi_touch_spi_control_port_read_n;
  output  [ 15: 0] spi_touch_spi_control_port_readdata_from_sa;
  output           spi_touch_spi_control_port_readyfordata_from_sa;
  output           spi_touch_spi_control_port_reset_n;
  output           spi_touch_spi_control_port_write_n;
  output  [ 15: 0] spi_touch_spi_control_port_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;
  input            spi_touch_spi_control_port_dataavailable;
  input            spi_touch_spi_control_port_endofpacket;
  input            spi_touch_spi_control_port_irq;
  input   [ 15: 0] spi_touch_spi_control_port_readdata;
  input            spi_touch_spi_control_port_readyfordata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_spi_touch_spi_control_port;
  wire             cpu_data_master_qualified_request_spi_touch_spi_control_port;
  wire             cpu_data_master_read_data_valid_spi_touch_spi_control_port;
  wire             cpu_data_master_requests_spi_touch_spi_control_port;
  wire             cpu_data_master_saved_grant_spi_touch_spi_control_port;
  reg              d1_reasons_to_wait;
  reg              d1_spi_touch_spi_control_port_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_spi_touch_spi_control_port;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 26: 0] shifted_address_to_spi_touch_spi_control_port_from_cpu_data_master;
  wire    [  2: 0] spi_touch_spi_control_port_address;
  wire             spi_touch_spi_control_port_allgrants;
  wire             spi_touch_spi_control_port_allow_new_arb_cycle;
  wire             spi_touch_spi_control_port_any_bursting_master_saved_grant;
  wire             spi_touch_spi_control_port_any_continuerequest;
  wire             spi_touch_spi_control_port_arb_counter_enable;
  reg     [  1: 0] spi_touch_spi_control_port_arb_share_counter;
  wire    [  1: 0] spi_touch_spi_control_port_arb_share_counter_next_value;
  wire    [  1: 0] spi_touch_spi_control_port_arb_share_set_values;
  wire             spi_touch_spi_control_port_beginbursttransfer_internal;
  wire             spi_touch_spi_control_port_begins_xfer;
  wire             spi_touch_spi_control_port_chipselect;
  wire             spi_touch_spi_control_port_dataavailable_from_sa;
  wire             spi_touch_spi_control_port_end_xfer;
  wire             spi_touch_spi_control_port_endofpacket_from_sa;
  wire             spi_touch_spi_control_port_firsttransfer;
  wire             spi_touch_spi_control_port_grant_vector;
  wire             spi_touch_spi_control_port_in_a_read_cycle;
  wire             spi_touch_spi_control_port_in_a_write_cycle;
  wire             spi_touch_spi_control_port_irq_from_sa;
  wire             spi_touch_spi_control_port_master_qreq_vector;
  wire             spi_touch_spi_control_port_non_bursting_master_requests;
  wire             spi_touch_spi_control_port_read_n;
  wire    [ 15: 0] spi_touch_spi_control_port_readdata_from_sa;
  wire             spi_touch_spi_control_port_readyfordata_from_sa;
  reg              spi_touch_spi_control_port_reg_firsttransfer;
  wire             spi_touch_spi_control_port_reset_n;
  reg              spi_touch_spi_control_port_slavearbiterlockenable;
  wire             spi_touch_spi_control_port_slavearbiterlockenable2;
  wire             spi_touch_spi_control_port_unreg_firsttransfer;
  wire             spi_touch_spi_control_port_waits_for_read;
  wire             spi_touch_spi_control_port_waits_for_write;
  wire             spi_touch_spi_control_port_write_n;
  wire    [ 15: 0] spi_touch_spi_control_port_writedata;
  wire             wait_for_spi_touch_spi_control_port_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~spi_touch_spi_control_port_end_xfer;
    end


  assign spi_touch_spi_control_port_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_spi_touch_spi_control_port));
  //assign spi_touch_spi_control_port_readdata_from_sa = spi_touch_spi_control_port_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign spi_touch_spi_control_port_readdata_from_sa = spi_touch_spi_control_port_readdata;

  assign cpu_data_master_requests_spi_touch_spi_control_port = ({cpu_data_master_address_to_slave[26 : 5] , 5'b0} == 27'h1800) & (cpu_data_master_read | cpu_data_master_write);
  //assign spi_touch_spi_control_port_dataavailable_from_sa = spi_touch_spi_control_port_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign spi_touch_spi_control_port_dataavailable_from_sa = spi_touch_spi_control_port_dataavailable;

  //assign spi_touch_spi_control_port_readyfordata_from_sa = spi_touch_spi_control_port_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign spi_touch_spi_control_port_readyfordata_from_sa = spi_touch_spi_control_port_readyfordata;

  //spi_touch_spi_control_port_arb_share_counter set values, which is an e_mux
  assign spi_touch_spi_control_port_arb_share_set_values = 1;

  //spi_touch_spi_control_port_non_bursting_master_requests mux, which is an e_mux
  assign spi_touch_spi_control_port_non_bursting_master_requests = cpu_data_master_requests_spi_touch_spi_control_port;

  //spi_touch_spi_control_port_any_bursting_master_saved_grant mux, which is an e_mux
  assign spi_touch_spi_control_port_any_bursting_master_saved_grant = 0;

  //spi_touch_spi_control_port_arb_share_counter_next_value assignment, which is an e_assign
  assign spi_touch_spi_control_port_arb_share_counter_next_value = spi_touch_spi_control_port_firsttransfer ? (spi_touch_spi_control_port_arb_share_set_values - 1) : |spi_touch_spi_control_port_arb_share_counter ? (spi_touch_spi_control_port_arb_share_counter - 1) : 0;

  //spi_touch_spi_control_port_allgrants all slave grants, which is an e_mux
  assign spi_touch_spi_control_port_allgrants = |spi_touch_spi_control_port_grant_vector;

  //spi_touch_spi_control_port_end_xfer assignment, which is an e_assign
  assign spi_touch_spi_control_port_end_xfer = ~(spi_touch_spi_control_port_waits_for_read | spi_touch_spi_control_port_waits_for_write);

  //end_xfer_arb_share_counter_term_spi_touch_spi_control_port arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_spi_touch_spi_control_port = spi_touch_spi_control_port_end_xfer & (~spi_touch_spi_control_port_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //spi_touch_spi_control_port_arb_share_counter arbitration counter enable, which is an e_assign
  assign spi_touch_spi_control_port_arb_counter_enable = (end_xfer_arb_share_counter_term_spi_touch_spi_control_port & spi_touch_spi_control_port_allgrants) | (end_xfer_arb_share_counter_term_spi_touch_spi_control_port & ~spi_touch_spi_control_port_non_bursting_master_requests);

  //spi_touch_spi_control_port_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          spi_touch_spi_control_port_arb_share_counter <= 0;
      else if (spi_touch_spi_control_port_arb_counter_enable)
          spi_touch_spi_control_port_arb_share_counter <= spi_touch_spi_control_port_arb_share_counter_next_value;
    end


  //spi_touch_spi_control_port_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          spi_touch_spi_control_port_slavearbiterlockenable <= 0;
      else if ((|spi_touch_spi_control_port_master_qreq_vector & end_xfer_arb_share_counter_term_spi_touch_spi_control_port) | (end_xfer_arb_share_counter_term_spi_touch_spi_control_port & ~spi_touch_spi_control_port_non_bursting_master_requests))
          spi_touch_spi_control_port_slavearbiterlockenable <= |spi_touch_spi_control_port_arb_share_counter_next_value;
    end


  //cpu/data_master spi_touch/spi_control_port arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = spi_touch_spi_control_port_slavearbiterlockenable & cpu_data_master_continuerequest;

  //spi_touch_spi_control_port_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign spi_touch_spi_control_port_slavearbiterlockenable2 = |spi_touch_spi_control_port_arb_share_counter_next_value;

  //cpu/data_master spi_touch/spi_control_port arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = spi_touch_spi_control_port_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //spi_touch_spi_control_port_any_continuerequest at least one master continues requesting, which is an e_assign
  assign spi_touch_spi_control_port_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_spi_touch_spi_control_port = cpu_data_master_requests_spi_touch_spi_control_port;
  //spi_touch_spi_control_port_writedata mux, which is an e_mux
  assign spi_touch_spi_control_port_writedata = cpu_data_master_writedata;

  //assign spi_touch_spi_control_port_endofpacket_from_sa = spi_touch_spi_control_port_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign spi_touch_spi_control_port_endofpacket_from_sa = spi_touch_spi_control_port_endofpacket;

  //master is always granted when requested
  assign cpu_data_master_granted_spi_touch_spi_control_port = cpu_data_master_qualified_request_spi_touch_spi_control_port;

  //cpu/data_master saved-grant spi_touch/spi_control_port, which is an e_assign
  assign cpu_data_master_saved_grant_spi_touch_spi_control_port = cpu_data_master_requests_spi_touch_spi_control_port;

  //allow new arb cycle for spi_touch/spi_control_port, which is an e_assign
  assign spi_touch_spi_control_port_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign spi_touch_spi_control_port_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign spi_touch_spi_control_port_master_qreq_vector = 1;

  //spi_touch_spi_control_port_reset_n assignment, which is an e_assign
  assign spi_touch_spi_control_port_reset_n = reset_n;

  assign spi_touch_spi_control_port_chipselect = cpu_data_master_granted_spi_touch_spi_control_port;
  //spi_touch_spi_control_port_firsttransfer first transaction, which is an e_assign
  assign spi_touch_spi_control_port_firsttransfer = spi_touch_spi_control_port_begins_xfer ? spi_touch_spi_control_port_unreg_firsttransfer : spi_touch_spi_control_port_reg_firsttransfer;

  //spi_touch_spi_control_port_unreg_firsttransfer first transaction, which is an e_assign
  assign spi_touch_spi_control_port_unreg_firsttransfer = ~(spi_touch_spi_control_port_slavearbiterlockenable & spi_touch_spi_control_port_any_continuerequest);

  //spi_touch_spi_control_port_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          spi_touch_spi_control_port_reg_firsttransfer <= 1'b1;
      else if (spi_touch_spi_control_port_begins_xfer)
          spi_touch_spi_control_port_reg_firsttransfer <= spi_touch_spi_control_port_unreg_firsttransfer;
    end


  //spi_touch_spi_control_port_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign spi_touch_spi_control_port_beginbursttransfer_internal = spi_touch_spi_control_port_begins_xfer;

  //~spi_touch_spi_control_port_read_n assignment, which is an e_mux
  assign spi_touch_spi_control_port_read_n = ~(cpu_data_master_granted_spi_touch_spi_control_port & cpu_data_master_read);

  //~spi_touch_spi_control_port_write_n assignment, which is an e_mux
  assign spi_touch_spi_control_port_write_n = ~(cpu_data_master_granted_spi_touch_spi_control_port & cpu_data_master_write);

  assign shifted_address_to_spi_touch_spi_control_port_from_cpu_data_master = cpu_data_master_address_to_slave;
  //spi_touch_spi_control_port_address mux, which is an e_mux
  assign spi_touch_spi_control_port_address = shifted_address_to_spi_touch_spi_control_port_from_cpu_data_master >> 2;

  //d1_spi_touch_spi_control_port_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_spi_touch_spi_control_port_end_xfer <= 1;
      else 
        d1_spi_touch_spi_control_port_end_xfer <= spi_touch_spi_control_port_end_xfer;
    end


  //spi_touch_spi_control_port_waits_for_read in a cycle, which is an e_mux
  assign spi_touch_spi_control_port_waits_for_read = spi_touch_spi_control_port_in_a_read_cycle & spi_touch_spi_control_port_begins_xfer;

  //spi_touch_spi_control_port_in_a_read_cycle assignment, which is an e_assign
  assign spi_touch_spi_control_port_in_a_read_cycle = cpu_data_master_granted_spi_touch_spi_control_port & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = spi_touch_spi_control_port_in_a_read_cycle;

  //spi_touch_spi_control_port_waits_for_write in a cycle, which is an e_mux
  assign spi_touch_spi_control_port_waits_for_write = spi_touch_spi_control_port_in_a_write_cycle & spi_touch_spi_control_port_begins_xfer;

  //spi_touch_spi_control_port_in_a_write_cycle assignment, which is an e_assign
  assign spi_touch_spi_control_port_in_a_write_cycle = cpu_data_master_granted_spi_touch_spi_control_port & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = spi_touch_spi_control_port_in_a_write_cycle;

  assign wait_for_spi_touch_spi_control_port_counter = 0;
  //assign spi_touch_spi_control_port_irq_from_sa = spi_touch_spi_control_port_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign spi_touch_spi_control_port_irq_from_sa = spi_touch_spi_control_port_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //spi_touch/spi_control_port enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sysid_control_slave_arbitrator (
                                        // inputs:
                                         clk,
                                         cpu_data_master_address_to_slave,
                                         cpu_data_master_read,
                                         cpu_data_master_write,
                                         reset_n,
                                         sysid_control_slave_readdata,

                                        // outputs:
                                         cpu_data_master_granted_sysid_control_slave,
                                         cpu_data_master_qualified_request_sysid_control_slave,
                                         cpu_data_master_read_data_valid_sysid_control_slave,
                                         cpu_data_master_requests_sysid_control_slave,
                                         d1_sysid_control_slave_end_xfer,
                                         sysid_control_slave_address,
                                         sysid_control_slave_readdata_from_sa,
                                         sysid_control_slave_reset_n
                                      )
;

  output           cpu_data_master_granted_sysid_control_slave;
  output           cpu_data_master_qualified_request_sysid_control_slave;
  output           cpu_data_master_read_data_valid_sysid_control_slave;
  output           cpu_data_master_requests_sysid_control_slave;
  output           d1_sysid_control_slave_end_xfer;
  output           sysid_control_slave_address;
  output  [ 31: 0] sysid_control_slave_readdata_from_sa;
  output           sysid_control_slave_reset_n;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            reset_n;
  input   [ 31: 0] sysid_control_slave_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sysid_control_slave;
  wire             cpu_data_master_qualified_request_sysid_control_slave;
  wire             cpu_data_master_read_data_valid_sysid_control_slave;
  wire             cpu_data_master_requests_sysid_control_slave;
  wire             cpu_data_master_saved_grant_sysid_control_slave;
  reg              d1_reasons_to_wait;
  reg              d1_sysid_control_slave_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sysid_control_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 26: 0] shifted_address_to_sysid_control_slave_from_cpu_data_master;
  wire             sysid_control_slave_address;
  wire             sysid_control_slave_allgrants;
  wire             sysid_control_slave_allow_new_arb_cycle;
  wire             sysid_control_slave_any_bursting_master_saved_grant;
  wire             sysid_control_slave_any_continuerequest;
  wire             sysid_control_slave_arb_counter_enable;
  reg     [  1: 0] sysid_control_slave_arb_share_counter;
  wire    [  1: 0] sysid_control_slave_arb_share_counter_next_value;
  wire    [  1: 0] sysid_control_slave_arb_share_set_values;
  wire             sysid_control_slave_beginbursttransfer_internal;
  wire             sysid_control_slave_begins_xfer;
  wire             sysid_control_slave_end_xfer;
  wire             sysid_control_slave_firsttransfer;
  wire             sysid_control_slave_grant_vector;
  wire             sysid_control_slave_in_a_read_cycle;
  wire             sysid_control_slave_in_a_write_cycle;
  wire             sysid_control_slave_master_qreq_vector;
  wire             sysid_control_slave_non_bursting_master_requests;
  wire    [ 31: 0] sysid_control_slave_readdata_from_sa;
  reg              sysid_control_slave_reg_firsttransfer;
  wire             sysid_control_slave_reset_n;
  reg              sysid_control_slave_slavearbiterlockenable;
  wire             sysid_control_slave_slavearbiterlockenable2;
  wire             sysid_control_slave_unreg_firsttransfer;
  wire             sysid_control_slave_waits_for_read;
  wire             sysid_control_slave_waits_for_write;
  wire             wait_for_sysid_control_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~sysid_control_slave_end_xfer;
    end


  assign sysid_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sysid_control_slave));
  //assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata;

  assign cpu_data_master_requests_sysid_control_slave = (({cpu_data_master_address_to_slave[26 : 3] , 3'b0} == 27'h18c0) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //sysid_control_slave_arb_share_counter set values, which is an e_mux
  assign sysid_control_slave_arb_share_set_values = 1;

  //sysid_control_slave_non_bursting_master_requests mux, which is an e_mux
  assign sysid_control_slave_non_bursting_master_requests = cpu_data_master_requests_sysid_control_slave;

  //sysid_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign sysid_control_slave_any_bursting_master_saved_grant = 0;

  //sysid_control_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign sysid_control_slave_arb_share_counter_next_value = sysid_control_slave_firsttransfer ? (sysid_control_slave_arb_share_set_values - 1) : |sysid_control_slave_arb_share_counter ? (sysid_control_slave_arb_share_counter - 1) : 0;

  //sysid_control_slave_allgrants all slave grants, which is an e_mux
  assign sysid_control_slave_allgrants = |sysid_control_slave_grant_vector;

  //sysid_control_slave_end_xfer assignment, which is an e_assign
  assign sysid_control_slave_end_xfer = ~(sysid_control_slave_waits_for_read | sysid_control_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_sysid_control_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sysid_control_slave = sysid_control_slave_end_xfer & (~sysid_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sysid_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign sysid_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_sysid_control_slave & sysid_control_slave_allgrants) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests);

  //sysid_control_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_arb_share_counter <= 0;
      else if (sysid_control_slave_arb_counter_enable)
          sysid_control_slave_arb_share_counter <= sysid_control_slave_arb_share_counter_next_value;
    end


  //sysid_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_slavearbiterlockenable <= 0;
      else if ((|sysid_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_sysid_control_slave) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests))
          sysid_control_slave_slavearbiterlockenable <= |sysid_control_slave_arb_share_counter_next_value;
    end


  //cpu/data_master sysid/control_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sysid_control_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sysid_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sysid_control_slave_slavearbiterlockenable2 = |sysid_control_slave_arb_share_counter_next_value;

  //cpu/data_master sysid/control_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sysid_control_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //sysid_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign sysid_control_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_sysid_control_slave = cpu_data_master_requests_sysid_control_slave;
  //master is always granted when requested
  assign cpu_data_master_granted_sysid_control_slave = cpu_data_master_qualified_request_sysid_control_slave;

  //cpu/data_master saved-grant sysid/control_slave, which is an e_assign
  assign cpu_data_master_saved_grant_sysid_control_slave = cpu_data_master_requests_sysid_control_slave;

  //allow new arb cycle for sysid/control_slave, which is an e_assign
  assign sysid_control_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign sysid_control_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign sysid_control_slave_master_qreq_vector = 1;

  //sysid_control_slave_reset_n assignment, which is an e_assign
  assign sysid_control_slave_reset_n = reset_n;

  //sysid_control_slave_firsttransfer first transaction, which is an e_assign
  assign sysid_control_slave_firsttransfer = sysid_control_slave_begins_xfer ? sysid_control_slave_unreg_firsttransfer : sysid_control_slave_reg_firsttransfer;

  //sysid_control_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign sysid_control_slave_unreg_firsttransfer = ~(sysid_control_slave_slavearbiterlockenable & sysid_control_slave_any_continuerequest);

  //sysid_control_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_reg_firsttransfer <= 1'b1;
      else if (sysid_control_slave_begins_xfer)
          sysid_control_slave_reg_firsttransfer <= sysid_control_slave_unreg_firsttransfer;
    end


  //sysid_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sysid_control_slave_beginbursttransfer_internal = sysid_control_slave_begins_xfer;

  assign shifted_address_to_sysid_control_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //sysid_control_slave_address mux, which is an e_mux
  assign sysid_control_slave_address = shifted_address_to_sysid_control_slave_from_cpu_data_master >> 2;

  //d1_sysid_control_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sysid_control_slave_end_xfer <= 1;
      else 
        d1_sysid_control_slave_end_xfer <= sysid_control_slave_end_xfer;
    end


  //sysid_control_slave_waits_for_read in a cycle, which is an e_mux
  assign sysid_control_slave_waits_for_read = sysid_control_slave_in_a_read_cycle & sysid_control_slave_begins_xfer;

  //sysid_control_slave_in_a_read_cycle assignment, which is an e_assign
  assign sysid_control_slave_in_a_read_cycle = cpu_data_master_granted_sysid_control_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sysid_control_slave_in_a_read_cycle;

  //sysid_control_slave_waits_for_write in a cycle, which is an e_mux
  assign sysid_control_slave_waits_for_write = sysid_control_slave_in_a_write_cycle & 0;

  //sysid_control_slave_in_a_write_cycle assignment, which is an e_assign
  assign sysid_control_slave_in_a_write_cycle = cpu_data_master_granted_sysid_control_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sysid_control_slave_in_a_write_cycle;

  assign wait_for_sysid_control_slave_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sysid/control_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module touch_cs_s1_arbitrator (
                                // inputs:
                                 clk,
                                 cpu_data_master_address_to_slave,
                                 cpu_data_master_read,
                                 cpu_data_master_waitrequest,
                                 cpu_data_master_write,
                                 cpu_data_master_writedata,
                                 reset_n,
                                 touch_cs_s1_readdata,

                                // outputs:
                                 cpu_data_master_granted_touch_cs_s1,
                                 cpu_data_master_qualified_request_touch_cs_s1,
                                 cpu_data_master_read_data_valid_touch_cs_s1,
                                 cpu_data_master_requests_touch_cs_s1,
                                 d1_touch_cs_s1_end_xfer,
                                 touch_cs_s1_address,
                                 touch_cs_s1_chipselect,
                                 touch_cs_s1_readdata_from_sa,
                                 touch_cs_s1_reset_n,
                                 touch_cs_s1_write_n,
                                 touch_cs_s1_writedata
                              )
;

  output           cpu_data_master_granted_touch_cs_s1;
  output           cpu_data_master_qualified_request_touch_cs_s1;
  output           cpu_data_master_read_data_valid_touch_cs_s1;
  output           cpu_data_master_requests_touch_cs_s1;
  output           d1_touch_cs_s1_end_xfer;
  output  [  1: 0] touch_cs_s1_address;
  output           touch_cs_s1_chipselect;
  output  [ 31: 0] touch_cs_s1_readdata_from_sa;
  output           touch_cs_s1_reset_n;
  output           touch_cs_s1_write_n;
  output  [ 31: 0] touch_cs_s1_writedata;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;
  input   [ 31: 0] touch_cs_s1_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_touch_cs_s1;
  wire             cpu_data_master_qualified_request_touch_cs_s1;
  wire             cpu_data_master_read_data_valid_touch_cs_s1;
  wire             cpu_data_master_requests_touch_cs_s1;
  wire             cpu_data_master_saved_grant_touch_cs_s1;
  reg              d1_reasons_to_wait;
  reg              d1_touch_cs_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_touch_cs_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 26: 0] shifted_address_to_touch_cs_s1_from_cpu_data_master;
  wire    [  1: 0] touch_cs_s1_address;
  wire             touch_cs_s1_allgrants;
  wire             touch_cs_s1_allow_new_arb_cycle;
  wire             touch_cs_s1_any_bursting_master_saved_grant;
  wire             touch_cs_s1_any_continuerequest;
  wire             touch_cs_s1_arb_counter_enable;
  reg     [  1: 0] touch_cs_s1_arb_share_counter;
  wire    [  1: 0] touch_cs_s1_arb_share_counter_next_value;
  wire    [  1: 0] touch_cs_s1_arb_share_set_values;
  wire             touch_cs_s1_beginbursttransfer_internal;
  wire             touch_cs_s1_begins_xfer;
  wire             touch_cs_s1_chipselect;
  wire             touch_cs_s1_end_xfer;
  wire             touch_cs_s1_firsttransfer;
  wire             touch_cs_s1_grant_vector;
  wire             touch_cs_s1_in_a_read_cycle;
  wire             touch_cs_s1_in_a_write_cycle;
  wire             touch_cs_s1_master_qreq_vector;
  wire             touch_cs_s1_non_bursting_master_requests;
  wire    [ 31: 0] touch_cs_s1_readdata_from_sa;
  reg              touch_cs_s1_reg_firsttransfer;
  wire             touch_cs_s1_reset_n;
  reg              touch_cs_s1_slavearbiterlockenable;
  wire             touch_cs_s1_slavearbiterlockenable2;
  wire             touch_cs_s1_unreg_firsttransfer;
  wire             touch_cs_s1_waits_for_read;
  wire             touch_cs_s1_waits_for_write;
  wire             touch_cs_s1_write_n;
  wire    [ 31: 0] touch_cs_s1_writedata;
  wire             wait_for_touch_cs_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~touch_cs_s1_end_xfer;
    end


  assign touch_cs_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_touch_cs_s1));
  //assign touch_cs_s1_readdata_from_sa = touch_cs_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign touch_cs_s1_readdata_from_sa = touch_cs_s1_readdata;

  assign cpu_data_master_requests_touch_cs_s1 = ({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1830) & (cpu_data_master_read | cpu_data_master_write);
  //touch_cs_s1_arb_share_counter set values, which is an e_mux
  assign touch_cs_s1_arb_share_set_values = 1;

  //touch_cs_s1_non_bursting_master_requests mux, which is an e_mux
  assign touch_cs_s1_non_bursting_master_requests = cpu_data_master_requests_touch_cs_s1;

  //touch_cs_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign touch_cs_s1_any_bursting_master_saved_grant = 0;

  //touch_cs_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign touch_cs_s1_arb_share_counter_next_value = touch_cs_s1_firsttransfer ? (touch_cs_s1_arb_share_set_values - 1) : |touch_cs_s1_arb_share_counter ? (touch_cs_s1_arb_share_counter - 1) : 0;

  //touch_cs_s1_allgrants all slave grants, which is an e_mux
  assign touch_cs_s1_allgrants = |touch_cs_s1_grant_vector;

  //touch_cs_s1_end_xfer assignment, which is an e_assign
  assign touch_cs_s1_end_xfer = ~(touch_cs_s1_waits_for_read | touch_cs_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_touch_cs_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_touch_cs_s1 = touch_cs_s1_end_xfer & (~touch_cs_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //touch_cs_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign touch_cs_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_touch_cs_s1 & touch_cs_s1_allgrants) | (end_xfer_arb_share_counter_term_touch_cs_s1 & ~touch_cs_s1_non_bursting_master_requests);

  //touch_cs_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          touch_cs_s1_arb_share_counter <= 0;
      else if (touch_cs_s1_arb_counter_enable)
          touch_cs_s1_arb_share_counter <= touch_cs_s1_arb_share_counter_next_value;
    end


  //touch_cs_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          touch_cs_s1_slavearbiterlockenable <= 0;
      else if ((|touch_cs_s1_master_qreq_vector & end_xfer_arb_share_counter_term_touch_cs_s1) | (end_xfer_arb_share_counter_term_touch_cs_s1 & ~touch_cs_s1_non_bursting_master_requests))
          touch_cs_s1_slavearbiterlockenable <= |touch_cs_s1_arb_share_counter_next_value;
    end


  //cpu/data_master touch_cs/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = touch_cs_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //touch_cs_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign touch_cs_s1_slavearbiterlockenable2 = |touch_cs_s1_arb_share_counter_next_value;

  //cpu/data_master touch_cs/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = touch_cs_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //touch_cs_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign touch_cs_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_touch_cs_s1 = cpu_data_master_requests_touch_cs_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //touch_cs_s1_writedata mux, which is an e_mux
  assign touch_cs_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_touch_cs_s1 = cpu_data_master_qualified_request_touch_cs_s1;

  //cpu/data_master saved-grant touch_cs/s1, which is an e_assign
  assign cpu_data_master_saved_grant_touch_cs_s1 = cpu_data_master_requests_touch_cs_s1;

  //allow new arb cycle for touch_cs/s1, which is an e_assign
  assign touch_cs_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign touch_cs_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign touch_cs_s1_master_qreq_vector = 1;

  //touch_cs_s1_reset_n assignment, which is an e_assign
  assign touch_cs_s1_reset_n = reset_n;

  assign touch_cs_s1_chipselect = cpu_data_master_granted_touch_cs_s1;
  //touch_cs_s1_firsttransfer first transaction, which is an e_assign
  assign touch_cs_s1_firsttransfer = touch_cs_s1_begins_xfer ? touch_cs_s1_unreg_firsttransfer : touch_cs_s1_reg_firsttransfer;

  //touch_cs_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign touch_cs_s1_unreg_firsttransfer = ~(touch_cs_s1_slavearbiterlockenable & touch_cs_s1_any_continuerequest);

  //touch_cs_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          touch_cs_s1_reg_firsttransfer <= 1'b1;
      else if (touch_cs_s1_begins_xfer)
          touch_cs_s1_reg_firsttransfer <= touch_cs_s1_unreg_firsttransfer;
    end


  //touch_cs_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign touch_cs_s1_beginbursttransfer_internal = touch_cs_s1_begins_xfer;

  //~touch_cs_s1_write_n assignment, which is an e_mux
  assign touch_cs_s1_write_n = ~(cpu_data_master_granted_touch_cs_s1 & cpu_data_master_write);

  assign shifted_address_to_touch_cs_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //touch_cs_s1_address mux, which is an e_mux
  assign touch_cs_s1_address = shifted_address_to_touch_cs_s1_from_cpu_data_master >> 2;

  //d1_touch_cs_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_touch_cs_s1_end_xfer <= 1;
      else 
        d1_touch_cs_s1_end_xfer <= touch_cs_s1_end_xfer;
    end


  //touch_cs_s1_waits_for_read in a cycle, which is an e_mux
  assign touch_cs_s1_waits_for_read = touch_cs_s1_in_a_read_cycle & touch_cs_s1_begins_xfer;

  //touch_cs_s1_in_a_read_cycle assignment, which is an e_assign
  assign touch_cs_s1_in_a_read_cycle = cpu_data_master_granted_touch_cs_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = touch_cs_s1_in_a_read_cycle;

  //touch_cs_s1_waits_for_write in a cycle, which is an e_mux
  assign touch_cs_s1_waits_for_write = touch_cs_s1_in_a_write_cycle & 0;

  //touch_cs_s1_in_a_write_cycle assignment, which is an e_assign
  assign touch_cs_s1_in_a_write_cycle = cpu_data_master_granted_touch_cs_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = touch_cs_s1_in_a_write_cycle;

  assign wait_for_touch_cs_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //touch_cs/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module touch_irq_s1_arbitrator (
                                 // inputs:
                                  clk,
                                  cpu_data_master_address_to_slave,
                                  cpu_data_master_read,
                                  cpu_data_master_write,
                                  reset_n,
                                  touch_irq_s1_readdata,

                                 // outputs:
                                  cpu_data_master_granted_touch_irq_s1,
                                  cpu_data_master_qualified_request_touch_irq_s1,
                                  cpu_data_master_read_data_valid_touch_irq_s1,
                                  cpu_data_master_requests_touch_irq_s1,
                                  d1_touch_irq_s1_end_xfer,
                                  touch_irq_s1_address,
                                  touch_irq_s1_readdata_from_sa,
                                  touch_irq_s1_reset_n
                               )
;

  output           cpu_data_master_granted_touch_irq_s1;
  output           cpu_data_master_qualified_request_touch_irq_s1;
  output           cpu_data_master_read_data_valid_touch_irq_s1;
  output           cpu_data_master_requests_touch_irq_s1;
  output           d1_touch_irq_s1_end_xfer;
  output  [  1: 0] touch_irq_s1_address;
  output  [ 31: 0] touch_irq_s1_readdata_from_sa;
  output           touch_irq_s1_reset_n;
  input            clk;
  input   [ 26: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            reset_n;
  input   [ 31: 0] touch_irq_s1_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_touch_irq_s1;
  wire             cpu_data_master_qualified_request_touch_irq_s1;
  wire             cpu_data_master_read_data_valid_touch_irq_s1;
  wire             cpu_data_master_requests_touch_irq_s1;
  wire             cpu_data_master_saved_grant_touch_irq_s1;
  reg              d1_reasons_to_wait;
  reg              d1_touch_irq_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_touch_irq_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 26: 0] shifted_address_to_touch_irq_s1_from_cpu_data_master;
  wire    [  1: 0] touch_irq_s1_address;
  wire             touch_irq_s1_allgrants;
  wire             touch_irq_s1_allow_new_arb_cycle;
  wire             touch_irq_s1_any_bursting_master_saved_grant;
  wire             touch_irq_s1_any_continuerequest;
  wire             touch_irq_s1_arb_counter_enable;
  reg     [  1: 0] touch_irq_s1_arb_share_counter;
  wire    [  1: 0] touch_irq_s1_arb_share_counter_next_value;
  wire    [  1: 0] touch_irq_s1_arb_share_set_values;
  wire             touch_irq_s1_beginbursttransfer_internal;
  wire             touch_irq_s1_begins_xfer;
  wire             touch_irq_s1_end_xfer;
  wire             touch_irq_s1_firsttransfer;
  wire             touch_irq_s1_grant_vector;
  wire             touch_irq_s1_in_a_read_cycle;
  wire             touch_irq_s1_in_a_write_cycle;
  wire             touch_irq_s1_master_qreq_vector;
  wire             touch_irq_s1_non_bursting_master_requests;
  wire    [ 31: 0] touch_irq_s1_readdata_from_sa;
  reg              touch_irq_s1_reg_firsttransfer;
  wire             touch_irq_s1_reset_n;
  reg              touch_irq_s1_slavearbiterlockenable;
  wire             touch_irq_s1_slavearbiterlockenable2;
  wire             touch_irq_s1_unreg_firsttransfer;
  wire             touch_irq_s1_waits_for_read;
  wire             touch_irq_s1_waits_for_write;
  wire             wait_for_touch_irq_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~touch_irq_s1_end_xfer;
    end


  assign touch_irq_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_touch_irq_s1));
  //assign touch_irq_s1_readdata_from_sa = touch_irq_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign touch_irq_s1_readdata_from_sa = touch_irq_s1_readdata;

  assign cpu_data_master_requests_touch_irq_s1 = (({cpu_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h1850) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //touch_irq_s1_arb_share_counter set values, which is an e_mux
  assign touch_irq_s1_arb_share_set_values = 1;

  //touch_irq_s1_non_bursting_master_requests mux, which is an e_mux
  assign touch_irq_s1_non_bursting_master_requests = cpu_data_master_requests_touch_irq_s1;

  //touch_irq_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign touch_irq_s1_any_bursting_master_saved_grant = 0;

  //touch_irq_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign touch_irq_s1_arb_share_counter_next_value = touch_irq_s1_firsttransfer ? (touch_irq_s1_arb_share_set_values - 1) : |touch_irq_s1_arb_share_counter ? (touch_irq_s1_arb_share_counter - 1) : 0;

  //touch_irq_s1_allgrants all slave grants, which is an e_mux
  assign touch_irq_s1_allgrants = |touch_irq_s1_grant_vector;

  //touch_irq_s1_end_xfer assignment, which is an e_assign
  assign touch_irq_s1_end_xfer = ~(touch_irq_s1_waits_for_read | touch_irq_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_touch_irq_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_touch_irq_s1 = touch_irq_s1_end_xfer & (~touch_irq_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //touch_irq_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign touch_irq_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_touch_irq_s1 & touch_irq_s1_allgrants) | (end_xfer_arb_share_counter_term_touch_irq_s1 & ~touch_irq_s1_non_bursting_master_requests);

  //touch_irq_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          touch_irq_s1_arb_share_counter <= 0;
      else if (touch_irq_s1_arb_counter_enable)
          touch_irq_s1_arb_share_counter <= touch_irq_s1_arb_share_counter_next_value;
    end


  //touch_irq_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          touch_irq_s1_slavearbiterlockenable <= 0;
      else if ((|touch_irq_s1_master_qreq_vector & end_xfer_arb_share_counter_term_touch_irq_s1) | (end_xfer_arb_share_counter_term_touch_irq_s1 & ~touch_irq_s1_non_bursting_master_requests))
          touch_irq_s1_slavearbiterlockenable <= |touch_irq_s1_arb_share_counter_next_value;
    end


  //cpu/data_master touch_irq/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = touch_irq_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //touch_irq_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign touch_irq_s1_slavearbiterlockenable2 = |touch_irq_s1_arb_share_counter_next_value;

  //cpu/data_master touch_irq/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = touch_irq_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //touch_irq_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign touch_irq_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_touch_irq_s1 = cpu_data_master_requests_touch_irq_s1;
  //master is always granted when requested
  assign cpu_data_master_granted_touch_irq_s1 = cpu_data_master_qualified_request_touch_irq_s1;

  //cpu/data_master saved-grant touch_irq/s1, which is an e_assign
  assign cpu_data_master_saved_grant_touch_irq_s1 = cpu_data_master_requests_touch_irq_s1;

  //allow new arb cycle for touch_irq/s1, which is an e_assign
  assign touch_irq_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign touch_irq_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign touch_irq_s1_master_qreq_vector = 1;

  //touch_irq_s1_reset_n assignment, which is an e_assign
  assign touch_irq_s1_reset_n = reset_n;

  //touch_irq_s1_firsttransfer first transaction, which is an e_assign
  assign touch_irq_s1_firsttransfer = touch_irq_s1_begins_xfer ? touch_irq_s1_unreg_firsttransfer : touch_irq_s1_reg_firsttransfer;

  //touch_irq_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign touch_irq_s1_unreg_firsttransfer = ~(touch_irq_s1_slavearbiterlockenable & touch_irq_s1_any_continuerequest);

  //touch_irq_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          touch_irq_s1_reg_firsttransfer <= 1'b1;
      else if (touch_irq_s1_begins_xfer)
          touch_irq_s1_reg_firsttransfer <= touch_irq_s1_unreg_firsttransfer;
    end


  //touch_irq_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign touch_irq_s1_beginbursttransfer_internal = touch_irq_s1_begins_xfer;

  assign shifted_address_to_touch_irq_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //touch_irq_s1_address mux, which is an e_mux
  assign touch_irq_s1_address = shifted_address_to_touch_irq_s1_from_cpu_data_master >> 2;

  //d1_touch_irq_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_touch_irq_s1_end_xfer <= 1;
      else 
        d1_touch_irq_s1_end_xfer <= touch_irq_s1_end_xfer;
    end


  //touch_irq_s1_waits_for_read in a cycle, which is an e_mux
  assign touch_irq_s1_waits_for_read = touch_irq_s1_in_a_read_cycle & touch_irq_s1_begins_xfer;

  //touch_irq_s1_in_a_read_cycle assignment, which is an e_assign
  assign touch_irq_s1_in_a_read_cycle = cpu_data_master_granted_touch_irq_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = touch_irq_s1_in_a_read_cycle;

  //touch_irq_s1_waits_for_write in a cycle, which is an e_mux
  assign touch_irq_s1_waits_for_write = touch_irq_s1_in_a_write_cycle & 0;

  //touch_irq_s1_in_a_write_cycle assignment, which is an e_assign
  assign touch_irq_s1_in_a_write_cycle = cpu_data_master_granted_touch_irq_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = touch_irq_s1_in_a_write_cycle;

  assign wait_for_touch_irq_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //touch_irq/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module CORE_SOPC_reset_clk_domain_synch_module (
                                                 // inputs:
                                                  clk,
                                                  data_in,
                                                  reset_n,

                                                 // outputs:
                                                  data_out
                                               )
;

  output           data_out;
  input            clk;
  input            data_in;
  input            reset_n;

  reg              data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  reg              data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_in_d1 <= 0;
      else 
        data_in_d1 <= data_in;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else 
        data_out <= data_in_d1;
    end



endmodule


// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module CORE_SOPC (
                   // 1) global signals:
                    clk,
                    reset_n,

                   // the_bl_n
                    out_port_from_the_bl_n,

                   // the_bl_p
                    out_port_from_the_bl_p,

                   // the_epcs
                    data0_to_the_epcs,
                    dclk_from_the_epcs,
                    sce_from_the_epcs,
                    sdo_from_the_epcs,

                   // the_lcd32_data
                    bidir_port_to_and_from_the_lcd32_data,

                   // the_lcd_cs
                    out_port_from_the_lcd_cs,

                   // the_lcd_rd
                    out_port_from_the_lcd_rd,

                   // the_lcd_rs
                    out_port_from_the_lcd_rs,

                   // the_lcd_wr
                    out_port_from_the_lcd_wr,

                   // the_reset
                    out_port_from_the_reset,

                   // the_sdram
                    zs_addr_from_the_sdram,
                    zs_ba_from_the_sdram,
                    zs_cas_n_from_the_sdram,
                    zs_cke_from_the_sdram,
                    zs_cs_n_from_the_sdram,
                    zs_dq_to_and_from_the_sdram,
                    zs_dqm_from_the_sdram,
                    zs_ras_n_from_the_sdram,
                    zs_we_n_from_the_sdram,

                   // the_spi_touch
                    MISO_to_the_spi_touch,
                    MOSI_from_the_spi_touch,
                    SCLK_from_the_spi_touch,
                    SS_n_from_the_spi_touch,

                   // the_touch_cs
                    out_port_from_the_touch_cs,

                   // the_touch_irq
                    in_port_to_the_touch_irq
                 )
;

  output           MOSI_from_the_spi_touch;
  output           SCLK_from_the_spi_touch;
  output           SS_n_from_the_spi_touch;
  inout   [ 15: 0] bidir_port_to_and_from_the_lcd32_data;
  output           dclk_from_the_epcs;
  output           out_port_from_the_bl_n;
  output           out_port_from_the_bl_p;
  output           out_port_from_the_lcd_cs;
  output           out_port_from_the_lcd_rd;
  output           out_port_from_the_lcd_rs;
  output           out_port_from_the_lcd_wr;
  output           out_port_from_the_reset;
  output           out_port_from_the_touch_cs;
  output           sce_from_the_epcs;
  output           sdo_from_the_epcs;
  output  [ 12: 0] zs_addr_from_the_sdram;
  output  [  1: 0] zs_ba_from_the_sdram;
  output           zs_cas_n_from_the_sdram;
  output           zs_cke_from_the_sdram;
  output           zs_cs_n_from_the_sdram;
  inout   [ 15: 0] zs_dq_to_and_from_the_sdram;
  output  [  1: 0] zs_dqm_from_the_sdram;
  output           zs_ras_n_from_the_sdram;
  output           zs_we_n_from_the_sdram;
  input            MISO_to_the_spi_touch;
  input            clk;
  input            data0_to_the_epcs;
  input            in_port_to_the_touch_irq;
  input            reset_n;

  wire             MOSI_from_the_spi_touch;
  wire             SCLK_from_the_spi_touch;
  wire             SS_n_from_the_spi_touch;
  wire    [ 15: 0] bidir_port_to_and_from_the_lcd32_data;
  wire    [  1: 0] bl_n_s1_address;
  wire             bl_n_s1_chipselect;
  wire    [ 31: 0] bl_n_s1_readdata;
  wire    [ 31: 0] bl_n_s1_readdata_from_sa;
  wire             bl_n_s1_reset_n;
  wire             bl_n_s1_write_n;
  wire    [ 31: 0] bl_n_s1_writedata;
  wire    [  1: 0] bl_p_s1_address;
  wire             bl_p_s1_chipselect;
  wire    [ 31: 0] bl_p_s1_readdata;
  wire    [ 31: 0] bl_p_s1_readdata_from_sa;
  wire             bl_p_s1_reset_n;
  wire             bl_p_s1_write_n;
  wire    [ 31: 0] bl_p_s1_writedata;
  wire             clk_reset_n;
  wire    [ 26: 0] cpu_data_master_address;
  wire    [ 26: 0] cpu_data_master_address_to_slave;
  wire    [  3: 0] cpu_data_master_byteenable;
  wire    [  1: 0] cpu_data_master_byteenable_sdram_s1;
  wire    [  1: 0] cpu_data_master_dbs_address;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire             cpu_data_master_debugaccess;
  wire             cpu_data_master_granted_bl_n_s1;
  wire             cpu_data_master_granted_bl_p_s1;
  wire             cpu_data_master_granted_cpu_jtag_debug_module;
  wire             cpu_data_master_granted_epcs_epcs_control_port;
  wire             cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_granted_lcd32_data_s1;
  wire             cpu_data_master_granted_lcd_cs_s1;
  wire             cpu_data_master_granted_lcd_rd_s1;
  wire             cpu_data_master_granted_lcd_rs_s1;
  wire             cpu_data_master_granted_lcd_wr_s1;
  wire             cpu_data_master_granted_reset_s1;
  wire             cpu_data_master_granted_sdram_s1;
  wire             cpu_data_master_granted_spi_touch_spi_control_port;
  wire             cpu_data_master_granted_sysid_control_slave;
  wire             cpu_data_master_granted_touch_cs_s1;
  wire             cpu_data_master_granted_touch_irq_s1;
  wire    [ 31: 0] cpu_data_master_irq;
  wire             cpu_data_master_no_byte_enables_and_last_term;
  wire             cpu_data_master_qualified_request_bl_n_s1;
  wire             cpu_data_master_qualified_request_bl_p_s1;
  wire             cpu_data_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_data_master_qualified_request_epcs_epcs_control_port;
  wire             cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_qualified_request_lcd32_data_s1;
  wire             cpu_data_master_qualified_request_lcd_cs_s1;
  wire             cpu_data_master_qualified_request_lcd_rd_s1;
  wire             cpu_data_master_qualified_request_lcd_rs_s1;
  wire             cpu_data_master_qualified_request_lcd_wr_s1;
  wire             cpu_data_master_qualified_request_reset_s1;
  wire             cpu_data_master_qualified_request_sdram_s1;
  wire             cpu_data_master_qualified_request_spi_touch_spi_control_port;
  wire             cpu_data_master_qualified_request_sysid_control_slave;
  wire             cpu_data_master_qualified_request_touch_cs_s1;
  wire             cpu_data_master_qualified_request_touch_irq_s1;
  wire             cpu_data_master_read;
  wire             cpu_data_master_read_data_valid_bl_n_s1;
  wire             cpu_data_master_read_data_valid_bl_p_s1;
  wire             cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_data_master_read_data_valid_epcs_epcs_control_port;
  wire             cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_read_data_valid_lcd32_data_s1;
  wire             cpu_data_master_read_data_valid_lcd_cs_s1;
  wire             cpu_data_master_read_data_valid_lcd_rd_s1;
  wire             cpu_data_master_read_data_valid_lcd_rs_s1;
  wire             cpu_data_master_read_data_valid_lcd_wr_s1;
  wire             cpu_data_master_read_data_valid_reset_s1;
  wire             cpu_data_master_read_data_valid_sdram_s1;
  wire             cpu_data_master_read_data_valid_sdram_s1_shift_register;
  wire             cpu_data_master_read_data_valid_spi_touch_spi_control_port;
  wire             cpu_data_master_read_data_valid_sysid_control_slave;
  wire             cpu_data_master_read_data_valid_touch_cs_s1;
  wire             cpu_data_master_read_data_valid_touch_irq_s1;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_requests_bl_n_s1;
  wire             cpu_data_master_requests_bl_p_s1;
  wire             cpu_data_master_requests_cpu_jtag_debug_module;
  wire             cpu_data_master_requests_epcs_epcs_control_port;
  wire             cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_requests_lcd32_data_s1;
  wire             cpu_data_master_requests_lcd_cs_s1;
  wire             cpu_data_master_requests_lcd_rd_s1;
  wire             cpu_data_master_requests_lcd_rs_s1;
  wire             cpu_data_master_requests_lcd_wr_s1;
  wire             cpu_data_master_requests_reset_s1;
  wire             cpu_data_master_requests_sdram_s1;
  wire             cpu_data_master_requests_spi_touch_spi_control_port;
  wire             cpu_data_master_requests_sysid_control_slave;
  wire             cpu_data_master_requests_touch_cs_s1;
  wire             cpu_data_master_requests_touch_irq_s1;
  wire             cpu_data_master_waitrequest;
  wire             cpu_data_master_write;
  wire    [ 31: 0] cpu_data_master_writedata;
  wire    [ 26: 0] cpu_instruction_master_address;
  wire    [ 26: 0] cpu_instruction_master_address_to_slave;
  wire    [  1: 0] cpu_instruction_master_dbs_address;
  wire             cpu_instruction_master_granted_cpu_jtag_debug_module;
  wire             cpu_instruction_master_granted_epcs_epcs_control_port;
  wire             cpu_instruction_master_granted_sdram_s1;
  wire             cpu_instruction_master_latency_counter;
  wire             cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_instruction_master_qualified_request_epcs_epcs_control_port;
  wire             cpu_instruction_master_qualified_request_sdram_s1;
  wire             cpu_instruction_master_read;
  wire             cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_instruction_master_read_data_valid_epcs_epcs_control_port;
  wire             cpu_instruction_master_read_data_valid_sdram_s1;
  wire             cpu_instruction_master_read_data_valid_sdram_s1_shift_register;
  wire    [ 31: 0] cpu_instruction_master_readdata;
  wire             cpu_instruction_master_readdatavalid;
  wire             cpu_instruction_master_requests_cpu_jtag_debug_module;
  wire             cpu_instruction_master_requests_epcs_epcs_control_port;
  wire             cpu_instruction_master_requests_sdram_s1;
  wire             cpu_instruction_master_waitrequest;
  wire    [  8: 0] cpu_jtag_debug_module_address;
  wire             cpu_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_jtag_debug_module_byteenable;
  wire             cpu_jtag_debug_module_chipselect;
  wire             cpu_jtag_debug_module_debugaccess;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  wire             cpu_jtag_debug_module_reset_n;
  wire             cpu_jtag_debug_module_resetrequest;
  wire             cpu_jtag_debug_module_resetrequest_from_sa;
  wire             cpu_jtag_debug_module_write;
  wire    [ 31: 0] cpu_jtag_debug_module_writedata;
  wire             d1_bl_n_s1_end_xfer;
  wire             d1_bl_p_s1_end_xfer;
  wire             d1_cpu_jtag_debug_module_end_xfer;
  wire             d1_epcs_epcs_control_port_end_xfer;
  wire             d1_jtag_uart_avalon_jtag_slave_end_xfer;
  wire             d1_lcd32_data_s1_end_xfer;
  wire             d1_lcd_cs_s1_end_xfer;
  wire             d1_lcd_rd_s1_end_xfer;
  wire             d1_lcd_rs_s1_end_xfer;
  wire             d1_lcd_wr_s1_end_xfer;
  wire             d1_reset_s1_end_xfer;
  wire             d1_sdram_s1_end_xfer;
  wire             d1_spi_touch_spi_control_port_end_xfer;
  wire             d1_sysid_control_slave_end_xfer;
  wire             d1_touch_cs_s1_end_xfer;
  wire             d1_touch_irq_s1_end_xfer;
  wire             dclk_from_the_epcs;
  wire    [  8: 0] epcs_epcs_control_port_address;
  wire             epcs_epcs_control_port_chipselect;
  wire             epcs_epcs_control_port_dataavailable;
  wire             epcs_epcs_control_port_dataavailable_from_sa;
  wire             epcs_epcs_control_port_endofpacket;
  wire             epcs_epcs_control_port_endofpacket_from_sa;
  wire             epcs_epcs_control_port_irq;
  wire             epcs_epcs_control_port_irq_from_sa;
  wire             epcs_epcs_control_port_read_n;
  wire    [ 31: 0] epcs_epcs_control_port_readdata;
  wire    [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
  wire             epcs_epcs_control_port_readyfordata;
  wire             epcs_epcs_control_port_readyfordata_from_sa;
  wire             epcs_epcs_control_port_reset_n;
  wire             epcs_epcs_control_port_write_n;
  wire    [ 31: 0] epcs_epcs_control_port_writedata;
  wire             jtag_uart_avalon_jtag_slave_address;
  wire             jtag_uart_avalon_jtag_slave_chipselect;
  wire             jtag_uart_avalon_jtag_slave_dataavailable;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_irq;
  wire             jtag_uart_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_reset_n;
  wire             jtag_uart_avalon_jtag_slave_waitrequest;
  wire             jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  wire    [  1: 0] lcd32_data_s1_address;
  wire             lcd32_data_s1_chipselect;
  wire    [ 31: 0] lcd32_data_s1_readdata;
  wire    [ 31: 0] lcd32_data_s1_readdata_from_sa;
  wire             lcd32_data_s1_reset_n;
  wire             lcd32_data_s1_write_n;
  wire    [ 31: 0] lcd32_data_s1_writedata;
  wire    [  1: 0] lcd_cs_s1_address;
  wire             lcd_cs_s1_chipselect;
  wire    [ 31: 0] lcd_cs_s1_readdata;
  wire    [ 31: 0] lcd_cs_s1_readdata_from_sa;
  wire             lcd_cs_s1_reset_n;
  wire             lcd_cs_s1_write_n;
  wire    [ 31: 0] lcd_cs_s1_writedata;
  wire    [  1: 0] lcd_rd_s1_address;
  wire             lcd_rd_s1_chipselect;
  wire    [ 31: 0] lcd_rd_s1_readdata;
  wire    [ 31: 0] lcd_rd_s1_readdata_from_sa;
  wire             lcd_rd_s1_reset_n;
  wire             lcd_rd_s1_write_n;
  wire    [ 31: 0] lcd_rd_s1_writedata;
  wire    [  1: 0] lcd_rs_s1_address;
  wire             lcd_rs_s1_chipselect;
  wire    [ 31: 0] lcd_rs_s1_readdata;
  wire    [ 31: 0] lcd_rs_s1_readdata_from_sa;
  wire             lcd_rs_s1_reset_n;
  wire             lcd_rs_s1_write_n;
  wire    [ 31: 0] lcd_rs_s1_writedata;
  wire    [  1: 0] lcd_wr_s1_address;
  wire             lcd_wr_s1_chipselect;
  wire    [ 31: 0] lcd_wr_s1_readdata;
  wire    [ 31: 0] lcd_wr_s1_readdata_from_sa;
  wire             lcd_wr_s1_reset_n;
  wire             lcd_wr_s1_write_n;
  wire    [ 31: 0] lcd_wr_s1_writedata;
  wire             out_port_from_the_bl_n;
  wire             out_port_from_the_bl_p;
  wire             out_port_from_the_lcd_cs;
  wire             out_port_from_the_lcd_rd;
  wire             out_port_from_the_lcd_rs;
  wire             out_port_from_the_lcd_wr;
  wire             out_port_from_the_reset;
  wire             out_port_from_the_touch_cs;
  wire             reset_n_sources;
  wire    [  1: 0] reset_s1_address;
  wire             reset_s1_chipselect;
  wire    [ 31: 0] reset_s1_readdata;
  wire    [ 31: 0] reset_s1_readdata_from_sa;
  wire             reset_s1_reset_n;
  wire             reset_s1_write_n;
  wire    [ 31: 0] reset_s1_writedata;
  wire             sce_from_the_epcs;
  wire             sdo_from_the_epcs;
  wire    [ 23: 0] sdram_s1_address;
  wire    [  1: 0] sdram_s1_byteenable_n;
  wire             sdram_s1_chipselect;
  wire             sdram_s1_read_n;
  wire    [ 15: 0] sdram_s1_readdata;
  wire    [ 15: 0] sdram_s1_readdata_from_sa;
  wire             sdram_s1_readdatavalid;
  wire             sdram_s1_reset_n;
  wire             sdram_s1_waitrequest;
  wire             sdram_s1_waitrequest_from_sa;
  wire             sdram_s1_write_n;
  wire    [ 15: 0] sdram_s1_writedata;
  wire    [  2: 0] spi_touch_spi_control_port_address;
  wire             spi_touch_spi_control_port_chipselect;
  wire             spi_touch_spi_control_port_dataavailable;
  wire             spi_touch_spi_control_port_dataavailable_from_sa;
  wire             spi_touch_spi_control_port_endofpacket;
  wire             spi_touch_spi_control_port_endofpacket_from_sa;
  wire             spi_touch_spi_control_port_irq;
  wire             spi_touch_spi_control_port_irq_from_sa;
  wire             spi_touch_spi_control_port_read_n;
  wire    [ 15: 0] spi_touch_spi_control_port_readdata;
  wire    [ 15: 0] spi_touch_spi_control_port_readdata_from_sa;
  wire             spi_touch_spi_control_port_readyfordata;
  wire             spi_touch_spi_control_port_readyfordata_from_sa;
  wire             spi_touch_spi_control_port_reset_n;
  wire             spi_touch_spi_control_port_write_n;
  wire    [ 15: 0] spi_touch_spi_control_port_writedata;
  wire             sysid_control_slave_address;
  wire             sysid_control_slave_clock;
  wire    [ 31: 0] sysid_control_slave_readdata;
  wire    [ 31: 0] sysid_control_slave_readdata_from_sa;
  wire             sysid_control_slave_reset_n;
  wire    [  1: 0] touch_cs_s1_address;
  wire             touch_cs_s1_chipselect;
  wire    [ 31: 0] touch_cs_s1_readdata;
  wire    [ 31: 0] touch_cs_s1_readdata_from_sa;
  wire             touch_cs_s1_reset_n;
  wire             touch_cs_s1_write_n;
  wire    [ 31: 0] touch_cs_s1_writedata;
  wire    [  1: 0] touch_irq_s1_address;
  wire    [ 31: 0] touch_irq_s1_readdata;
  wire    [ 31: 0] touch_irq_s1_readdata_from_sa;
  wire             touch_irq_s1_reset_n;
  wire    [ 12: 0] zs_addr_from_the_sdram;
  wire    [  1: 0] zs_ba_from_the_sdram;
  wire             zs_cas_n_from_the_sdram;
  wire             zs_cke_from_the_sdram;
  wire             zs_cs_n_from_the_sdram;
  wire    [ 15: 0] zs_dq_to_and_from_the_sdram;
  wire    [  1: 0] zs_dqm_from_the_sdram;
  wire             zs_ras_n_from_the_sdram;
  wire             zs_we_n_from_the_sdram;
  bl_n_s1_arbitrator the_bl_n_s1
    (
      .bl_n_s1_address                           (bl_n_s1_address),
      .bl_n_s1_chipselect                        (bl_n_s1_chipselect),
      .bl_n_s1_readdata                          (bl_n_s1_readdata),
      .bl_n_s1_readdata_from_sa                  (bl_n_s1_readdata_from_sa),
      .bl_n_s1_reset_n                           (bl_n_s1_reset_n),
      .bl_n_s1_write_n                           (bl_n_s1_write_n),
      .bl_n_s1_writedata                         (bl_n_s1_writedata),
      .clk                                       (clk),
      .cpu_data_master_address_to_slave          (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_bl_n_s1           (cpu_data_master_granted_bl_n_s1),
      .cpu_data_master_qualified_request_bl_n_s1 (cpu_data_master_qualified_request_bl_n_s1),
      .cpu_data_master_read                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_bl_n_s1   (cpu_data_master_read_data_valid_bl_n_s1),
      .cpu_data_master_requests_bl_n_s1          (cpu_data_master_requests_bl_n_s1),
      .cpu_data_master_waitrequest               (cpu_data_master_waitrequest),
      .cpu_data_master_write                     (cpu_data_master_write),
      .cpu_data_master_writedata                 (cpu_data_master_writedata),
      .d1_bl_n_s1_end_xfer                       (d1_bl_n_s1_end_xfer),
      .reset_n                                   (clk_reset_n)
    );

  bl_n the_bl_n
    (
      .address    (bl_n_s1_address),
      .chipselect (bl_n_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_bl_n),
      .readdata   (bl_n_s1_readdata),
      .reset_n    (bl_n_s1_reset_n),
      .write_n    (bl_n_s1_write_n),
      .writedata  (bl_n_s1_writedata)
    );

  bl_p_s1_arbitrator the_bl_p_s1
    (
      .bl_p_s1_address                           (bl_p_s1_address),
      .bl_p_s1_chipselect                        (bl_p_s1_chipselect),
      .bl_p_s1_readdata                          (bl_p_s1_readdata),
      .bl_p_s1_readdata_from_sa                  (bl_p_s1_readdata_from_sa),
      .bl_p_s1_reset_n                           (bl_p_s1_reset_n),
      .bl_p_s1_write_n                           (bl_p_s1_write_n),
      .bl_p_s1_writedata                         (bl_p_s1_writedata),
      .clk                                       (clk),
      .cpu_data_master_address_to_slave          (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_bl_p_s1           (cpu_data_master_granted_bl_p_s1),
      .cpu_data_master_qualified_request_bl_p_s1 (cpu_data_master_qualified_request_bl_p_s1),
      .cpu_data_master_read                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_bl_p_s1   (cpu_data_master_read_data_valid_bl_p_s1),
      .cpu_data_master_requests_bl_p_s1          (cpu_data_master_requests_bl_p_s1),
      .cpu_data_master_waitrequest               (cpu_data_master_waitrequest),
      .cpu_data_master_write                     (cpu_data_master_write),
      .cpu_data_master_writedata                 (cpu_data_master_writedata),
      .d1_bl_p_s1_end_xfer                       (d1_bl_p_s1_end_xfer),
      .reset_n                                   (clk_reset_n)
    );

  bl_p the_bl_p
    (
      .address    (bl_p_s1_address),
      .chipselect (bl_p_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_bl_p),
      .readdata   (bl_p_s1_readdata),
      .reset_n    (bl_p_s1_reset_n),
      .write_n    (bl_p_s1_write_n),
      .writedata  (bl_p_s1_writedata)
    );

  cpu_jtag_debug_module_arbitrator the_cpu_jtag_debug_module
    (
      .clk                                                            (clk),
      .cpu_data_master_address_to_slave                               (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                     (cpu_data_master_byteenable),
      .cpu_data_master_debugaccess                                    (cpu_data_master_debugaccess),
      .cpu_data_master_granted_cpu_jtag_debug_module                  (cpu_data_master_granted_cpu_jtag_debug_module),
      .cpu_data_master_qualified_request_cpu_jtag_debug_module        (cpu_data_master_qualified_request_cpu_jtag_debug_module),
      .cpu_data_master_read                                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_cpu_jtag_debug_module          (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_data_master_requests_cpu_jtag_debug_module                 (cpu_data_master_requests_cpu_jtag_debug_module),
      .cpu_data_master_waitrequest                                    (cpu_data_master_waitrequest),
      .cpu_data_master_write                                          (cpu_data_master_write),
      .cpu_data_master_writedata                                      (cpu_data_master_writedata),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_granted_cpu_jtag_debug_module           (cpu_instruction_master_granted_cpu_jtag_debug_module),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module   (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_requests_cpu_jtag_debug_module          (cpu_instruction_master_requests_cpu_jtag_debug_module),
      .cpu_jtag_debug_module_address                                  (cpu_jtag_debug_module_address),
      .cpu_jtag_debug_module_begintransfer                            (cpu_jtag_debug_module_begintransfer),
      .cpu_jtag_debug_module_byteenable                               (cpu_jtag_debug_module_byteenable),
      .cpu_jtag_debug_module_chipselect                               (cpu_jtag_debug_module_chipselect),
      .cpu_jtag_debug_module_debugaccess                              (cpu_jtag_debug_module_debugaccess),
      .cpu_jtag_debug_module_readdata                                 (cpu_jtag_debug_module_readdata),
      .cpu_jtag_debug_module_readdata_from_sa                         (cpu_jtag_debug_module_readdata_from_sa),
      .cpu_jtag_debug_module_reset_n                                  (cpu_jtag_debug_module_reset_n),
      .cpu_jtag_debug_module_resetrequest                             (cpu_jtag_debug_module_resetrequest),
      .cpu_jtag_debug_module_resetrequest_from_sa                     (cpu_jtag_debug_module_resetrequest_from_sa),
      .cpu_jtag_debug_module_write                                    (cpu_jtag_debug_module_write),
      .cpu_jtag_debug_module_writedata                                (cpu_jtag_debug_module_writedata),
      .d1_cpu_jtag_debug_module_end_xfer                              (d1_cpu_jtag_debug_module_end_xfer),
      .reset_n                                                        (clk_reset_n)
    );

  cpu_data_master_arbitrator the_cpu_data_master
    (
      .bl_n_s1_readdata_from_sa                                      (bl_n_s1_readdata_from_sa),
      .bl_p_s1_readdata_from_sa                                      (bl_p_s1_readdata_from_sa),
      .clk                                                           (clk),
      .cpu_data_master_address                                       (cpu_data_master_address),
      .cpu_data_master_address_to_slave                              (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable_sdram_s1                           (cpu_data_master_byteenable_sdram_s1),
      .cpu_data_master_dbs_address                                   (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                                  (cpu_data_master_dbs_write_16),
      .cpu_data_master_granted_bl_n_s1                               (cpu_data_master_granted_bl_n_s1),
      .cpu_data_master_granted_bl_p_s1                               (cpu_data_master_granted_bl_p_s1),
      .cpu_data_master_granted_cpu_jtag_debug_module                 (cpu_data_master_granted_cpu_jtag_debug_module),
      .cpu_data_master_granted_epcs_epcs_control_port                (cpu_data_master_granted_epcs_epcs_control_port),
      .cpu_data_master_granted_jtag_uart_avalon_jtag_slave           (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_granted_lcd32_data_s1                         (cpu_data_master_granted_lcd32_data_s1),
      .cpu_data_master_granted_lcd_cs_s1                             (cpu_data_master_granted_lcd_cs_s1),
      .cpu_data_master_granted_lcd_rd_s1                             (cpu_data_master_granted_lcd_rd_s1),
      .cpu_data_master_granted_lcd_rs_s1                             (cpu_data_master_granted_lcd_rs_s1),
      .cpu_data_master_granted_lcd_wr_s1                             (cpu_data_master_granted_lcd_wr_s1),
      .cpu_data_master_granted_reset_s1                              (cpu_data_master_granted_reset_s1),
      .cpu_data_master_granted_sdram_s1                              (cpu_data_master_granted_sdram_s1),
      .cpu_data_master_granted_spi_touch_spi_control_port            (cpu_data_master_granted_spi_touch_spi_control_port),
      .cpu_data_master_granted_sysid_control_slave                   (cpu_data_master_granted_sysid_control_slave),
      .cpu_data_master_granted_touch_cs_s1                           (cpu_data_master_granted_touch_cs_s1),
      .cpu_data_master_granted_touch_irq_s1                          (cpu_data_master_granted_touch_irq_s1),
      .cpu_data_master_irq                                           (cpu_data_master_irq),
      .cpu_data_master_no_byte_enables_and_last_term                 (cpu_data_master_no_byte_enables_and_last_term),
      .cpu_data_master_qualified_request_bl_n_s1                     (cpu_data_master_qualified_request_bl_n_s1),
      .cpu_data_master_qualified_request_bl_p_s1                     (cpu_data_master_qualified_request_bl_p_s1),
      .cpu_data_master_qualified_request_cpu_jtag_debug_module       (cpu_data_master_qualified_request_cpu_jtag_debug_module),
      .cpu_data_master_qualified_request_epcs_epcs_control_port      (cpu_data_master_qualified_request_epcs_epcs_control_port),
      .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_qualified_request_lcd32_data_s1               (cpu_data_master_qualified_request_lcd32_data_s1),
      .cpu_data_master_qualified_request_lcd_cs_s1                   (cpu_data_master_qualified_request_lcd_cs_s1),
      .cpu_data_master_qualified_request_lcd_rd_s1                   (cpu_data_master_qualified_request_lcd_rd_s1),
      .cpu_data_master_qualified_request_lcd_rs_s1                   (cpu_data_master_qualified_request_lcd_rs_s1),
      .cpu_data_master_qualified_request_lcd_wr_s1                   (cpu_data_master_qualified_request_lcd_wr_s1),
      .cpu_data_master_qualified_request_reset_s1                    (cpu_data_master_qualified_request_reset_s1),
      .cpu_data_master_qualified_request_sdram_s1                    (cpu_data_master_qualified_request_sdram_s1),
      .cpu_data_master_qualified_request_spi_touch_spi_control_port  (cpu_data_master_qualified_request_spi_touch_spi_control_port),
      .cpu_data_master_qualified_request_sysid_control_slave         (cpu_data_master_qualified_request_sysid_control_slave),
      .cpu_data_master_qualified_request_touch_cs_s1                 (cpu_data_master_qualified_request_touch_cs_s1),
      .cpu_data_master_qualified_request_touch_irq_s1                (cpu_data_master_qualified_request_touch_irq_s1),
      .cpu_data_master_read                                          (cpu_data_master_read),
      .cpu_data_master_read_data_valid_bl_n_s1                       (cpu_data_master_read_data_valid_bl_n_s1),
      .cpu_data_master_read_data_valid_bl_p_s1                       (cpu_data_master_read_data_valid_bl_p_s1),
      .cpu_data_master_read_data_valid_cpu_jtag_debug_module         (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_data_master_read_data_valid_epcs_epcs_control_port        (cpu_data_master_read_data_valid_epcs_epcs_control_port),
      .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave   (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read_data_valid_lcd32_data_s1                 (cpu_data_master_read_data_valid_lcd32_data_s1),
      .cpu_data_master_read_data_valid_lcd_cs_s1                     (cpu_data_master_read_data_valid_lcd_cs_s1),
      .cpu_data_master_read_data_valid_lcd_rd_s1                     (cpu_data_master_read_data_valid_lcd_rd_s1),
      .cpu_data_master_read_data_valid_lcd_rs_s1                     (cpu_data_master_read_data_valid_lcd_rs_s1),
      .cpu_data_master_read_data_valid_lcd_wr_s1                     (cpu_data_master_read_data_valid_lcd_wr_s1),
      .cpu_data_master_read_data_valid_reset_s1                      (cpu_data_master_read_data_valid_reset_s1),
      .cpu_data_master_read_data_valid_sdram_s1                      (cpu_data_master_read_data_valid_sdram_s1),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register       (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_read_data_valid_spi_touch_spi_control_port    (cpu_data_master_read_data_valid_spi_touch_spi_control_port),
      .cpu_data_master_read_data_valid_sysid_control_slave           (cpu_data_master_read_data_valid_sysid_control_slave),
      .cpu_data_master_read_data_valid_touch_cs_s1                   (cpu_data_master_read_data_valid_touch_cs_s1),
      .cpu_data_master_read_data_valid_touch_irq_s1                  (cpu_data_master_read_data_valid_touch_irq_s1),
      .cpu_data_master_readdata                                      (cpu_data_master_readdata),
      .cpu_data_master_requests_bl_n_s1                              (cpu_data_master_requests_bl_n_s1),
      .cpu_data_master_requests_bl_p_s1                              (cpu_data_master_requests_bl_p_s1),
      .cpu_data_master_requests_cpu_jtag_debug_module                (cpu_data_master_requests_cpu_jtag_debug_module),
      .cpu_data_master_requests_epcs_epcs_control_port               (cpu_data_master_requests_epcs_epcs_control_port),
      .cpu_data_master_requests_jtag_uart_avalon_jtag_slave          (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_requests_lcd32_data_s1                        (cpu_data_master_requests_lcd32_data_s1),
      .cpu_data_master_requests_lcd_cs_s1                            (cpu_data_master_requests_lcd_cs_s1),
      .cpu_data_master_requests_lcd_rd_s1                            (cpu_data_master_requests_lcd_rd_s1),
      .cpu_data_master_requests_lcd_rs_s1                            (cpu_data_master_requests_lcd_rs_s1),
      .cpu_data_master_requests_lcd_wr_s1                            (cpu_data_master_requests_lcd_wr_s1),
      .cpu_data_master_requests_reset_s1                             (cpu_data_master_requests_reset_s1),
      .cpu_data_master_requests_sdram_s1                             (cpu_data_master_requests_sdram_s1),
      .cpu_data_master_requests_spi_touch_spi_control_port           (cpu_data_master_requests_spi_touch_spi_control_port),
      .cpu_data_master_requests_sysid_control_slave                  (cpu_data_master_requests_sysid_control_slave),
      .cpu_data_master_requests_touch_cs_s1                          (cpu_data_master_requests_touch_cs_s1),
      .cpu_data_master_requests_touch_irq_s1                         (cpu_data_master_requests_touch_irq_s1),
      .cpu_data_master_waitrequest                                   (cpu_data_master_waitrequest),
      .cpu_data_master_write                                         (cpu_data_master_write),
      .cpu_data_master_writedata                                     (cpu_data_master_writedata),
      .cpu_jtag_debug_module_readdata_from_sa                        (cpu_jtag_debug_module_readdata_from_sa),
      .d1_bl_n_s1_end_xfer                                           (d1_bl_n_s1_end_xfer),
      .d1_bl_p_s1_end_xfer                                           (d1_bl_p_s1_end_xfer),
      .d1_cpu_jtag_debug_module_end_xfer                             (d1_cpu_jtag_debug_module_end_xfer),
      .d1_epcs_epcs_control_port_end_xfer                            (d1_epcs_epcs_control_port_end_xfer),
      .d1_jtag_uart_avalon_jtag_slave_end_xfer                       (d1_jtag_uart_avalon_jtag_slave_end_xfer),
      .d1_lcd32_data_s1_end_xfer                                     (d1_lcd32_data_s1_end_xfer),
      .d1_lcd_cs_s1_end_xfer                                         (d1_lcd_cs_s1_end_xfer),
      .d1_lcd_rd_s1_end_xfer                                         (d1_lcd_rd_s1_end_xfer),
      .d1_lcd_rs_s1_end_xfer                                         (d1_lcd_rs_s1_end_xfer),
      .d1_lcd_wr_s1_end_xfer                                         (d1_lcd_wr_s1_end_xfer),
      .d1_reset_s1_end_xfer                                          (d1_reset_s1_end_xfer),
      .d1_sdram_s1_end_xfer                                          (d1_sdram_s1_end_xfer),
      .d1_spi_touch_spi_control_port_end_xfer                        (d1_spi_touch_spi_control_port_end_xfer),
      .d1_sysid_control_slave_end_xfer                               (d1_sysid_control_slave_end_xfer),
      .d1_touch_cs_s1_end_xfer                                       (d1_touch_cs_s1_end_xfer),
      .d1_touch_irq_s1_end_xfer                                      (d1_touch_irq_s1_end_xfer),
      .epcs_epcs_control_port_irq_from_sa                            (epcs_epcs_control_port_irq_from_sa),
      .epcs_epcs_control_port_readdata_from_sa                       (epcs_epcs_control_port_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_irq_from_sa                       (jtag_uart_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_avalon_jtag_slave_readdata_from_sa                  (jtag_uart_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_waitrequest_from_sa               (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
      .lcd32_data_s1_readdata_from_sa                                (lcd32_data_s1_readdata_from_sa),
      .lcd_cs_s1_readdata_from_sa                                    (lcd_cs_s1_readdata_from_sa),
      .lcd_rd_s1_readdata_from_sa                                    (lcd_rd_s1_readdata_from_sa),
      .lcd_rs_s1_readdata_from_sa                                    (lcd_rs_s1_readdata_from_sa),
      .lcd_wr_s1_readdata_from_sa                                    (lcd_wr_s1_readdata_from_sa),
      .reset_n                                                       (clk_reset_n),
      .reset_s1_readdata_from_sa                                     (reset_s1_readdata_from_sa),
      .sdram_s1_readdata_from_sa                                     (sdram_s1_readdata_from_sa),
      .sdram_s1_waitrequest_from_sa                                  (sdram_s1_waitrequest_from_sa),
      .spi_touch_spi_control_port_irq_from_sa                        (spi_touch_spi_control_port_irq_from_sa),
      .spi_touch_spi_control_port_readdata_from_sa                   (spi_touch_spi_control_port_readdata_from_sa),
      .sysid_control_slave_readdata_from_sa                          (sysid_control_slave_readdata_from_sa),
      .touch_cs_s1_readdata_from_sa                                  (touch_cs_s1_readdata_from_sa),
      .touch_irq_s1_readdata_from_sa                                 (touch_irq_s1_readdata_from_sa)
    );

  cpu_instruction_master_arbitrator the_cpu_instruction_master
    (
      .clk                                                             (clk),
      .cpu_instruction_master_address                                  (cpu_instruction_master_address),
      .cpu_instruction_master_address_to_slave                         (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                              (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_cpu_jtag_debug_module            (cpu_instruction_master_granted_cpu_jtag_debug_module),
      .cpu_instruction_master_granted_epcs_epcs_control_port           (cpu_instruction_master_granted_epcs_epcs_control_port),
      .cpu_instruction_master_granted_sdram_s1                         (cpu_instruction_master_granted_sdram_s1),
      .cpu_instruction_master_latency_counter                          (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_cpu_jtag_debug_module  (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
      .cpu_instruction_master_qualified_request_epcs_epcs_control_port (cpu_instruction_master_qualified_request_epcs_epcs_control_port),
      .cpu_instruction_master_qualified_request_sdram_s1               (cpu_instruction_master_qualified_request_sdram_s1),
      .cpu_instruction_master_read                                     (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module    (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_instruction_master_read_data_valid_epcs_epcs_control_port   (cpu_instruction_master_read_data_valid_epcs_epcs_control_port),
      .cpu_instruction_master_read_data_valid_sdram_s1                 (cpu_instruction_master_read_data_valid_sdram_s1),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register  (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_readdata                                 (cpu_instruction_master_readdata),
      .cpu_instruction_master_readdatavalid                            (cpu_instruction_master_readdatavalid),
      .cpu_instruction_master_requests_cpu_jtag_debug_module           (cpu_instruction_master_requests_cpu_jtag_debug_module),
      .cpu_instruction_master_requests_epcs_epcs_control_port          (cpu_instruction_master_requests_epcs_epcs_control_port),
      .cpu_instruction_master_requests_sdram_s1                        (cpu_instruction_master_requests_sdram_s1),
      .cpu_instruction_master_waitrequest                              (cpu_instruction_master_waitrequest),
      .cpu_jtag_debug_module_readdata_from_sa                          (cpu_jtag_debug_module_readdata_from_sa),
      .d1_cpu_jtag_debug_module_end_xfer                               (d1_cpu_jtag_debug_module_end_xfer),
      .d1_epcs_epcs_control_port_end_xfer                              (d1_epcs_epcs_control_port_end_xfer),
      .d1_sdram_s1_end_xfer                                            (d1_sdram_s1_end_xfer),
      .epcs_epcs_control_port_readdata_from_sa                         (epcs_epcs_control_port_readdata_from_sa),
      .reset_n                                                         (clk_reset_n),
      .sdram_s1_readdata_from_sa                                       (sdram_s1_readdata_from_sa),
      .sdram_s1_waitrequest_from_sa                                    (sdram_s1_waitrequest_from_sa)
    );

  cpu the_cpu
    (
      .clk                                   (clk),
      .d_address                             (cpu_data_master_address),
      .d_byteenable                          (cpu_data_master_byteenable),
      .d_irq                                 (cpu_data_master_irq),
      .d_read                                (cpu_data_master_read),
      .d_readdata                            (cpu_data_master_readdata),
      .d_waitrequest                         (cpu_data_master_waitrequest),
      .d_write                               (cpu_data_master_write),
      .d_writedata                           (cpu_data_master_writedata),
      .i_address                             (cpu_instruction_master_address),
      .i_read                                (cpu_instruction_master_read),
      .i_readdata                            (cpu_instruction_master_readdata),
      .i_readdatavalid                       (cpu_instruction_master_readdatavalid),
      .i_waitrequest                         (cpu_instruction_master_waitrequest),
      .jtag_debug_module_address             (cpu_jtag_debug_module_address),
      .jtag_debug_module_begintransfer       (cpu_jtag_debug_module_begintransfer),
      .jtag_debug_module_byteenable          (cpu_jtag_debug_module_byteenable),
      .jtag_debug_module_debugaccess         (cpu_jtag_debug_module_debugaccess),
      .jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess),
      .jtag_debug_module_readdata            (cpu_jtag_debug_module_readdata),
      .jtag_debug_module_resetrequest        (cpu_jtag_debug_module_resetrequest),
      .jtag_debug_module_select              (cpu_jtag_debug_module_chipselect),
      .jtag_debug_module_write               (cpu_jtag_debug_module_write),
      .jtag_debug_module_writedata           (cpu_jtag_debug_module_writedata),
      .reset_n                               (cpu_jtag_debug_module_reset_n)
    );

  epcs_epcs_control_port_arbitrator the_epcs_epcs_control_port
    (
      .clk                                                             (clk),
      .cpu_data_master_address_to_slave                                (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_epcs_epcs_control_port                  (cpu_data_master_granted_epcs_epcs_control_port),
      .cpu_data_master_qualified_request_epcs_epcs_control_port        (cpu_data_master_qualified_request_epcs_epcs_control_port),
      .cpu_data_master_read                                            (cpu_data_master_read),
      .cpu_data_master_read_data_valid_epcs_epcs_control_port          (cpu_data_master_read_data_valid_epcs_epcs_control_port),
      .cpu_data_master_requests_epcs_epcs_control_port                 (cpu_data_master_requests_epcs_epcs_control_port),
      .cpu_data_master_write                                           (cpu_data_master_write),
      .cpu_data_master_writedata                                       (cpu_data_master_writedata),
      .cpu_instruction_master_address_to_slave                         (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_granted_epcs_epcs_control_port           (cpu_instruction_master_granted_epcs_epcs_control_port),
      .cpu_instruction_master_latency_counter                          (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_epcs_epcs_control_port (cpu_instruction_master_qualified_request_epcs_epcs_control_port),
      .cpu_instruction_master_read                                     (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_epcs_epcs_control_port   (cpu_instruction_master_read_data_valid_epcs_epcs_control_port),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register  (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_requests_epcs_epcs_control_port          (cpu_instruction_master_requests_epcs_epcs_control_port),
      .d1_epcs_epcs_control_port_end_xfer                              (d1_epcs_epcs_control_port_end_xfer),
      .epcs_epcs_control_port_address                                  (epcs_epcs_control_port_address),
      .epcs_epcs_control_port_chipselect                               (epcs_epcs_control_port_chipselect),
      .epcs_epcs_control_port_dataavailable                            (epcs_epcs_control_port_dataavailable),
      .epcs_epcs_control_port_dataavailable_from_sa                    (epcs_epcs_control_port_dataavailable_from_sa),
      .epcs_epcs_control_port_endofpacket                              (epcs_epcs_control_port_endofpacket),
      .epcs_epcs_control_port_endofpacket_from_sa                      (epcs_epcs_control_port_endofpacket_from_sa),
      .epcs_epcs_control_port_irq                                      (epcs_epcs_control_port_irq),
      .epcs_epcs_control_port_irq_from_sa                              (epcs_epcs_control_port_irq_from_sa),
      .epcs_epcs_control_port_read_n                                   (epcs_epcs_control_port_read_n),
      .epcs_epcs_control_port_readdata                                 (epcs_epcs_control_port_readdata),
      .epcs_epcs_control_port_readdata_from_sa                         (epcs_epcs_control_port_readdata_from_sa),
      .epcs_epcs_control_port_readyfordata                             (epcs_epcs_control_port_readyfordata),
      .epcs_epcs_control_port_readyfordata_from_sa                     (epcs_epcs_control_port_readyfordata_from_sa),
      .epcs_epcs_control_port_reset_n                                  (epcs_epcs_control_port_reset_n),
      .epcs_epcs_control_port_write_n                                  (epcs_epcs_control_port_write_n),
      .epcs_epcs_control_port_writedata                                (epcs_epcs_control_port_writedata),
      .reset_n                                                         (clk_reset_n)
    );

  epcs the_epcs
    (
      .address       (epcs_epcs_control_port_address),
      .chipselect    (epcs_epcs_control_port_chipselect),
      .clk           (clk),
      .data0         (data0_to_the_epcs),
      .dataavailable (epcs_epcs_control_port_dataavailable),
      .dclk          (dclk_from_the_epcs),
      .endofpacket   (epcs_epcs_control_port_endofpacket),
      .irq           (epcs_epcs_control_port_irq),
      .read_n        (epcs_epcs_control_port_read_n),
      .readdata      (epcs_epcs_control_port_readdata),
      .readyfordata  (epcs_epcs_control_port_readyfordata),
      .reset_n       (epcs_epcs_control_port_reset_n),
      .sce           (sce_from_the_epcs),
      .sdo           (sdo_from_the_epcs),
      .write_n       (epcs_epcs_control_port_write_n),
      .writedata     (epcs_epcs_control_port_writedata)
    );

  jtag_uart_avalon_jtag_slave_arbitrator the_jtag_uart_avalon_jtag_slave
    (
      .clk                                                           (clk),
      .cpu_data_master_address_to_slave                              (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_jtag_uart_avalon_jtag_slave           (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read                                          (cpu_data_master_read),
      .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave   (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_requests_jtag_uart_avalon_jtag_slave          (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_waitrequest                                   (cpu_data_master_waitrequest),
      .cpu_data_master_write                                         (cpu_data_master_write),
      .cpu_data_master_writedata                                     (cpu_data_master_writedata),
      .d1_jtag_uart_avalon_jtag_slave_end_xfer                       (d1_jtag_uart_avalon_jtag_slave_end_xfer),
      .jtag_uart_avalon_jtag_slave_address                           (jtag_uart_avalon_jtag_slave_address),
      .jtag_uart_avalon_jtag_slave_chipselect                        (jtag_uart_avalon_jtag_slave_chipselect),
      .jtag_uart_avalon_jtag_slave_dataavailable                     (jtag_uart_avalon_jtag_slave_dataavailable),
      .jtag_uart_avalon_jtag_slave_dataavailable_from_sa             (jtag_uart_avalon_jtag_slave_dataavailable_from_sa),
      .jtag_uart_avalon_jtag_slave_irq                               (jtag_uart_avalon_jtag_slave_irq),
      .jtag_uart_avalon_jtag_slave_irq_from_sa                       (jtag_uart_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_avalon_jtag_slave_read_n                            (jtag_uart_avalon_jtag_slave_read_n),
      .jtag_uart_avalon_jtag_slave_readdata                          (jtag_uart_avalon_jtag_slave_readdata),
      .jtag_uart_avalon_jtag_slave_readdata_from_sa                  (jtag_uart_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_readyfordata                      (jtag_uart_avalon_jtag_slave_readyfordata),
      .jtag_uart_avalon_jtag_slave_readyfordata_from_sa              (jtag_uart_avalon_jtag_slave_readyfordata_from_sa),
      .jtag_uart_avalon_jtag_slave_reset_n                           (jtag_uart_avalon_jtag_slave_reset_n),
      .jtag_uart_avalon_jtag_slave_waitrequest                       (jtag_uart_avalon_jtag_slave_waitrequest),
      .jtag_uart_avalon_jtag_slave_waitrequest_from_sa               (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
      .jtag_uart_avalon_jtag_slave_write_n                           (jtag_uart_avalon_jtag_slave_write_n),
      .jtag_uart_avalon_jtag_slave_writedata                         (jtag_uart_avalon_jtag_slave_writedata),
      .reset_n                                                       (clk_reset_n)
    );

  jtag_uart the_jtag_uart
    (
      .av_address     (jtag_uart_avalon_jtag_slave_address),
      .av_chipselect  (jtag_uart_avalon_jtag_slave_chipselect),
      .av_irq         (jtag_uart_avalon_jtag_slave_irq),
      .av_read_n      (jtag_uart_avalon_jtag_slave_read_n),
      .av_readdata    (jtag_uart_avalon_jtag_slave_readdata),
      .av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest),
      .av_write_n     (jtag_uart_avalon_jtag_slave_write_n),
      .av_writedata   (jtag_uart_avalon_jtag_slave_writedata),
      .clk            (clk),
      .dataavailable  (jtag_uart_avalon_jtag_slave_dataavailable),
      .readyfordata   (jtag_uart_avalon_jtag_slave_readyfordata),
      .rst_n          (jtag_uart_avalon_jtag_slave_reset_n)
    );

  lcd32_data_s1_arbitrator the_lcd32_data_s1
    (
      .clk                                             (clk),
      .cpu_data_master_address_to_slave                (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_lcd32_data_s1           (cpu_data_master_granted_lcd32_data_s1),
      .cpu_data_master_qualified_request_lcd32_data_s1 (cpu_data_master_qualified_request_lcd32_data_s1),
      .cpu_data_master_read                            (cpu_data_master_read),
      .cpu_data_master_read_data_valid_lcd32_data_s1   (cpu_data_master_read_data_valid_lcd32_data_s1),
      .cpu_data_master_requests_lcd32_data_s1          (cpu_data_master_requests_lcd32_data_s1),
      .cpu_data_master_waitrequest                     (cpu_data_master_waitrequest),
      .cpu_data_master_write                           (cpu_data_master_write),
      .cpu_data_master_writedata                       (cpu_data_master_writedata),
      .d1_lcd32_data_s1_end_xfer                       (d1_lcd32_data_s1_end_xfer),
      .lcd32_data_s1_address                           (lcd32_data_s1_address),
      .lcd32_data_s1_chipselect                        (lcd32_data_s1_chipselect),
      .lcd32_data_s1_readdata                          (lcd32_data_s1_readdata),
      .lcd32_data_s1_readdata_from_sa                  (lcd32_data_s1_readdata_from_sa),
      .lcd32_data_s1_reset_n                           (lcd32_data_s1_reset_n),
      .lcd32_data_s1_write_n                           (lcd32_data_s1_write_n),
      .lcd32_data_s1_writedata                         (lcd32_data_s1_writedata),
      .reset_n                                         (clk_reset_n)
    );

  lcd32_data the_lcd32_data
    (
      .address    (lcd32_data_s1_address),
      .bidir_port (bidir_port_to_and_from_the_lcd32_data),
      .chipselect (lcd32_data_s1_chipselect),
      .clk        (clk),
      .readdata   (lcd32_data_s1_readdata),
      .reset_n    (lcd32_data_s1_reset_n),
      .write_n    (lcd32_data_s1_write_n),
      .writedata  (lcd32_data_s1_writedata)
    );

  lcd_cs_s1_arbitrator the_lcd_cs_s1
    (
      .clk                                         (clk),
      .cpu_data_master_address_to_slave            (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_lcd_cs_s1           (cpu_data_master_granted_lcd_cs_s1),
      .cpu_data_master_qualified_request_lcd_cs_s1 (cpu_data_master_qualified_request_lcd_cs_s1),
      .cpu_data_master_read                        (cpu_data_master_read),
      .cpu_data_master_read_data_valid_lcd_cs_s1   (cpu_data_master_read_data_valid_lcd_cs_s1),
      .cpu_data_master_requests_lcd_cs_s1          (cpu_data_master_requests_lcd_cs_s1),
      .cpu_data_master_waitrequest                 (cpu_data_master_waitrequest),
      .cpu_data_master_write                       (cpu_data_master_write),
      .cpu_data_master_writedata                   (cpu_data_master_writedata),
      .d1_lcd_cs_s1_end_xfer                       (d1_lcd_cs_s1_end_xfer),
      .lcd_cs_s1_address                           (lcd_cs_s1_address),
      .lcd_cs_s1_chipselect                        (lcd_cs_s1_chipselect),
      .lcd_cs_s1_readdata                          (lcd_cs_s1_readdata),
      .lcd_cs_s1_readdata_from_sa                  (lcd_cs_s1_readdata_from_sa),
      .lcd_cs_s1_reset_n                           (lcd_cs_s1_reset_n),
      .lcd_cs_s1_write_n                           (lcd_cs_s1_write_n),
      .lcd_cs_s1_writedata                         (lcd_cs_s1_writedata),
      .reset_n                                     (clk_reset_n)
    );

  lcd_cs the_lcd_cs
    (
      .address    (lcd_cs_s1_address),
      .chipselect (lcd_cs_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_lcd_cs),
      .readdata   (lcd_cs_s1_readdata),
      .reset_n    (lcd_cs_s1_reset_n),
      .write_n    (lcd_cs_s1_write_n),
      .writedata  (lcd_cs_s1_writedata)
    );

  lcd_rd_s1_arbitrator the_lcd_rd_s1
    (
      .clk                                         (clk),
      .cpu_data_master_address_to_slave            (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_lcd_rd_s1           (cpu_data_master_granted_lcd_rd_s1),
      .cpu_data_master_qualified_request_lcd_rd_s1 (cpu_data_master_qualified_request_lcd_rd_s1),
      .cpu_data_master_read                        (cpu_data_master_read),
      .cpu_data_master_read_data_valid_lcd_rd_s1   (cpu_data_master_read_data_valid_lcd_rd_s1),
      .cpu_data_master_requests_lcd_rd_s1          (cpu_data_master_requests_lcd_rd_s1),
      .cpu_data_master_waitrequest                 (cpu_data_master_waitrequest),
      .cpu_data_master_write                       (cpu_data_master_write),
      .cpu_data_master_writedata                   (cpu_data_master_writedata),
      .d1_lcd_rd_s1_end_xfer                       (d1_lcd_rd_s1_end_xfer),
      .lcd_rd_s1_address                           (lcd_rd_s1_address),
      .lcd_rd_s1_chipselect                        (lcd_rd_s1_chipselect),
      .lcd_rd_s1_readdata                          (lcd_rd_s1_readdata),
      .lcd_rd_s1_readdata_from_sa                  (lcd_rd_s1_readdata_from_sa),
      .lcd_rd_s1_reset_n                           (lcd_rd_s1_reset_n),
      .lcd_rd_s1_write_n                           (lcd_rd_s1_write_n),
      .lcd_rd_s1_writedata                         (lcd_rd_s1_writedata),
      .reset_n                                     (clk_reset_n)
    );

  lcd_rd the_lcd_rd
    (
      .address    (lcd_rd_s1_address),
      .chipselect (lcd_rd_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_lcd_rd),
      .readdata   (lcd_rd_s1_readdata),
      .reset_n    (lcd_rd_s1_reset_n),
      .write_n    (lcd_rd_s1_write_n),
      .writedata  (lcd_rd_s1_writedata)
    );

  lcd_rs_s1_arbitrator the_lcd_rs_s1
    (
      .clk                                         (clk),
      .cpu_data_master_address_to_slave            (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_lcd_rs_s1           (cpu_data_master_granted_lcd_rs_s1),
      .cpu_data_master_qualified_request_lcd_rs_s1 (cpu_data_master_qualified_request_lcd_rs_s1),
      .cpu_data_master_read                        (cpu_data_master_read),
      .cpu_data_master_read_data_valid_lcd_rs_s1   (cpu_data_master_read_data_valid_lcd_rs_s1),
      .cpu_data_master_requests_lcd_rs_s1          (cpu_data_master_requests_lcd_rs_s1),
      .cpu_data_master_waitrequest                 (cpu_data_master_waitrequest),
      .cpu_data_master_write                       (cpu_data_master_write),
      .cpu_data_master_writedata                   (cpu_data_master_writedata),
      .d1_lcd_rs_s1_end_xfer                       (d1_lcd_rs_s1_end_xfer),
      .lcd_rs_s1_address                           (lcd_rs_s1_address),
      .lcd_rs_s1_chipselect                        (lcd_rs_s1_chipselect),
      .lcd_rs_s1_readdata                          (lcd_rs_s1_readdata),
      .lcd_rs_s1_readdata_from_sa                  (lcd_rs_s1_readdata_from_sa),
      .lcd_rs_s1_reset_n                           (lcd_rs_s1_reset_n),
      .lcd_rs_s1_write_n                           (lcd_rs_s1_write_n),
      .lcd_rs_s1_writedata                         (lcd_rs_s1_writedata),
      .reset_n                                     (clk_reset_n)
    );

  lcd_rs the_lcd_rs
    (
      .address    (lcd_rs_s1_address),
      .chipselect (lcd_rs_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_lcd_rs),
      .readdata   (lcd_rs_s1_readdata),
      .reset_n    (lcd_rs_s1_reset_n),
      .write_n    (lcd_rs_s1_write_n),
      .writedata  (lcd_rs_s1_writedata)
    );

  lcd_wr_s1_arbitrator the_lcd_wr_s1
    (
      .clk                                         (clk),
      .cpu_data_master_address_to_slave            (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_lcd_wr_s1           (cpu_data_master_granted_lcd_wr_s1),
      .cpu_data_master_qualified_request_lcd_wr_s1 (cpu_data_master_qualified_request_lcd_wr_s1),
      .cpu_data_master_read                        (cpu_data_master_read),
      .cpu_data_master_read_data_valid_lcd_wr_s1   (cpu_data_master_read_data_valid_lcd_wr_s1),
      .cpu_data_master_requests_lcd_wr_s1          (cpu_data_master_requests_lcd_wr_s1),
      .cpu_data_master_waitrequest                 (cpu_data_master_waitrequest),
      .cpu_data_master_write                       (cpu_data_master_write),
      .cpu_data_master_writedata                   (cpu_data_master_writedata),
      .d1_lcd_wr_s1_end_xfer                       (d1_lcd_wr_s1_end_xfer),
      .lcd_wr_s1_address                           (lcd_wr_s1_address),
      .lcd_wr_s1_chipselect                        (lcd_wr_s1_chipselect),
      .lcd_wr_s1_readdata                          (lcd_wr_s1_readdata),
      .lcd_wr_s1_readdata_from_sa                  (lcd_wr_s1_readdata_from_sa),
      .lcd_wr_s1_reset_n                           (lcd_wr_s1_reset_n),
      .lcd_wr_s1_write_n                           (lcd_wr_s1_write_n),
      .lcd_wr_s1_writedata                         (lcd_wr_s1_writedata),
      .reset_n                                     (clk_reset_n)
    );

  lcd_wr the_lcd_wr
    (
      .address    (lcd_wr_s1_address),
      .chipselect (lcd_wr_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_lcd_wr),
      .readdata   (lcd_wr_s1_readdata),
      .reset_n    (lcd_wr_s1_reset_n),
      .write_n    (lcd_wr_s1_write_n),
      .writedata  (lcd_wr_s1_writedata)
    );

  reset_s1_arbitrator the_reset_s1
    (
      .clk                                        (clk),
      .cpu_data_master_address_to_slave           (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_reset_s1           (cpu_data_master_granted_reset_s1),
      .cpu_data_master_qualified_request_reset_s1 (cpu_data_master_qualified_request_reset_s1),
      .cpu_data_master_read                       (cpu_data_master_read),
      .cpu_data_master_read_data_valid_reset_s1   (cpu_data_master_read_data_valid_reset_s1),
      .cpu_data_master_requests_reset_s1          (cpu_data_master_requests_reset_s1),
      .cpu_data_master_waitrequest                (cpu_data_master_waitrequest),
      .cpu_data_master_write                      (cpu_data_master_write),
      .cpu_data_master_writedata                  (cpu_data_master_writedata),
      .d1_reset_s1_end_xfer                       (d1_reset_s1_end_xfer),
      .reset_n                                    (clk_reset_n),
      .reset_s1_address                           (reset_s1_address),
      .reset_s1_chipselect                        (reset_s1_chipselect),
      .reset_s1_readdata                          (reset_s1_readdata),
      .reset_s1_readdata_from_sa                  (reset_s1_readdata_from_sa),
      .reset_s1_reset_n                           (reset_s1_reset_n),
      .reset_s1_write_n                           (reset_s1_write_n),
      .reset_s1_writedata                         (reset_s1_writedata)
    );

  reset the_reset
    (
      .address    (reset_s1_address),
      .chipselect (reset_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_reset),
      .readdata   (reset_s1_readdata),
      .reset_n    (reset_s1_reset_n),
      .write_n    (reset_s1_write_n),
      .writedata  (reset_s1_writedata)
    );

  sdram_s1_arbitrator the_sdram_s1
    (
      .clk                                                            (clk),
      .cpu_data_master_address_to_slave                               (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                     (cpu_data_master_byteenable),
      .cpu_data_master_byteenable_sdram_s1                            (cpu_data_master_byteenable_sdram_s1),
      .cpu_data_master_dbs_address                                    (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                                   (cpu_data_master_dbs_write_16),
      .cpu_data_master_granted_sdram_s1                               (cpu_data_master_granted_sdram_s1),
      .cpu_data_master_no_byte_enables_and_last_term                  (cpu_data_master_no_byte_enables_and_last_term),
      .cpu_data_master_qualified_request_sdram_s1                     (cpu_data_master_qualified_request_sdram_s1),
      .cpu_data_master_read                                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sdram_s1                       (cpu_data_master_read_data_valid_sdram_s1),
      .cpu_data_master_read_data_valid_sdram_s1_shift_register        (cpu_data_master_read_data_valid_sdram_s1_shift_register),
      .cpu_data_master_requests_sdram_s1                              (cpu_data_master_requests_sdram_s1),
      .cpu_data_master_waitrequest                                    (cpu_data_master_waitrequest),
      .cpu_data_master_write                                          (cpu_data_master_write),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                             (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_sdram_s1                        (cpu_instruction_master_granted_sdram_s1),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_sdram_s1              (cpu_instruction_master_qualified_request_sdram_s1),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_sdram_s1                (cpu_instruction_master_read_data_valid_sdram_s1),
      .cpu_instruction_master_read_data_valid_sdram_s1_shift_register (cpu_instruction_master_read_data_valid_sdram_s1_shift_register),
      .cpu_instruction_master_requests_sdram_s1                       (cpu_instruction_master_requests_sdram_s1),
      .d1_sdram_s1_end_xfer                                           (d1_sdram_s1_end_xfer),
      .reset_n                                                        (clk_reset_n),
      .sdram_s1_address                                               (sdram_s1_address),
      .sdram_s1_byteenable_n                                          (sdram_s1_byteenable_n),
      .sdram_s1_chipselect                                            (sdram_s1_chipselect),
      .sdram_s1_read_n                                                (sdram_s1_read_n),
      .sdram_s1_readdata                                              (sdram_s1_readdata),
      .sdram_s1_readdata_from_sa                                      (sdram_s1_readdata_from_sa),
      .sdram_s1_readdatavalid                                         (sdram_s1_readdatavalid),
      .sdram_s1_reset_n                                               (sdram_s1_reset_n),
      .sdram_s1_waitrequest                                           (sdram_s1_waitrequest),
      .sdram_s1_waitrequest_from_sa                                   (sdram_s1_waitrequest_from_sa),
      .sdram_s1_write_n                                               (sdram_s1_write_n),
      .sdram_s1_writedata                                             (sdram_s1_writedata)
    );

  sdram the_sdram
    (
      .az_addr        (sdram_s1_address),
      .az_be_n        (sdram_s1_byteenable_n),
      .az_cs          (sdram_s1_chipselect),
      .az_data        (sdram_s1_writedata),
      .az_rd_n        (sdram_s1_read_n),
      .az_wr_n        (sdram_s1_write_n),
      .clk            (clk),
      .reset_n        (sdram_s1_reset_n),
      .za_data        (sdram_s1_readdata),
      .za_valid       (sdram_s1_readdatavalid),
      .za_waitrequest (sdram_s1_waitrequest),
      .zs_addr        (zs_addr_from_the_sdram),
      .zs_ba          (zs_ba_from_the_sdram),
      .zs_cas_n       (zs_cas_n_from_the_sdram),
      .zs_cke         (zs_cke_from_the_sdram),
      .zs_cs_n        (zs_cs_n_from_the_sdram),
      .zs_dq          (zs_dq_to_and_from_the_sdram),
      .zs_dqm         (zs_dqm_from_the_sdram),
      .zs_ras_n       (zs_ras_n_from_the_sdram),
      .zs_we_n        (zs_we_n_from_the_sdram)
    );

  spi_touch_spi_control_port_arbitrator the_spi_touch_spi_control_port
    (
      .clk                                                          (clk),
      .cpu_data_master_address_to_slave                             (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_spi_touch_spi_control_port           (cpu_data_master_granted_spi_touch_spi_control_port),
      .cpu_data_master_qualified_request_spi_touch_spi_control_port (cpu_data_master_qualified_request_spi_touch_spi_control_port),
      .cpu_data_master_read                                         (cpu_data_master_read),
      .cpu_data_master_read_data_valid_spi_touch_spi_control_port   (cpu_data_master_read_data_valid_spi_touch_spi_control_port),
      .cpu_data_master_requests_spi_touch_spi_control_port          (cpu_data_master_requests_spi_touch_spi_control_port),
      .cpu_data_master_write                                        (cpu_data_master_write),
      .cpu_data_master_writedata                                    (cpu_data_master_writedata),
      .d1_spi_touch_spi_control_port_end_xfer                       (d1_spi_touch_spi_control_port_end_xfer),
      .reset_n                                                      (clk_reset_n),
      .spi_touch_spi_control_port_address                           (spi_touch_spi_control_port_address),
      .spi_touch_spi_control_port_chipselect                        (spi_touch_spi_control_port_chipselect),
      .spi_touch_spi_control_port_dataavailable                     (spi_touch_spi_control_port_dataavailable),
      .spi_touch_spi_control_port_dataavailable_from_sa             (spi_touch_spi_control_port_dataavailable_from_sa),
      .spi_touch_spi_control_port_endofpacket                       (spi_touch_spi_control_port_endofpacket),
      .spi_touch_spi_control_port_endofpacket_from_sa               (spi_touch_spi_control_port_endofpacket_from_sa),
      .spi_touch_spi_control_port_irq                               (spi_touch_spi_control_port_irq),
      .spi_touch_spi_control_port_irq_from_sa                       (spi_touch_spi_control_port_irq_from_sa),
      .spi_touch_spi_control_port_read_n                            (spi_touch_spi_control_port_read_n),
      .spi_touch_spi_control_port_readdata                          (spi_touch_spi_control_port_readdata),
      .spi_touch_spi_control_port_readdata_from_sa                  (spi_touch_spi_control_port_readdata_from_sa),
      .spi_touch_spi_control_port_readyfordata                      (spi_touch_spi_control_port_readyfordata),
      .spi_touch_spi_control_port_readyfordata_from_sa              (spi_touch_spi_control_port_readyfordata_from_sa),
      .spi_touch_spi_control_port_reset_n                           (spi_touch_spi_control_port_reset_n),
      .spi_touch_spi_control_port_write_n                           (spi_touch_spi_control_port_write_n),
      .spi_touch_spi_control_port_writedata                         (spi_touch_spi_control_port_writedata)
    );

  spi_touch the_spi_touch
    (
      .MISO          (MISO_to_the_spi_touch),
      .MOSI          (MOSI_from_the_spi_touch),
      .SCLK          (SCLK_from_the_spi_touch),
      .SS_n          (SS_n_from_the_spi_touch),
      .clk           (clk),
      .data_from_cpu (spi_touch_spi_control_port_writedata),
      .data_to_cpu   (spi_touch_spi_control_port_readdata),
      .dataavailable (spi_touch_spi_control_port_dataavailable),
      .endofpacket   (spi_touch_spi_control_port_endofpacket),
      .irq           (spi_touch_spi_control_port_irq),
      .mem_addr      (spi_touch_spi_control_port_address),
      .read_n        (spi_touch_spi_control_port_read_n),
      .readyfordata  (spi_touch_spi_control_port_readyfordata),
      .reset_n       (spi_touch_spi_control_port_reset_n),
      .spi_select    (spi_touch_spi_control_port_chipselect),
      .write_n       (spi_touch_spi_control_port_write_n)
    );

  sysid_control_slave_arbitrator the_sysid_control_slave
    (
      .clk                                                   (clk),
      .cpu_data_master_address_to_slave                      (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_sysid_control_slave           (cpu_data_master_granted_sysid_control_slave),
      .cpu_data_master_qualified_request_sysid_control_slave (cpu_data_master_qualified_request_sysid_control_slave),
      .cpu_data_master_read                                  (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sysid_control_slave   (cpu_data_master_read_data_valid_sysid_control_slave),
      .cpu_data_master_requests_sysid_control_slave          (cpu_data_master_requests_sysid_control_slave),
      .cpu_data_master_write                                 (cpu_data_master_write),
      .d1_sysid_control_slave_end_xfer                       (d1_sysid_control_slave_end_xfer),
      .reset_n                                               (clk_reset_n),
      .sysid_control_slave_address                           (sysid_control_slave_address),
      .sysid_control_slave_readdata                          (sysid_control_slave_readdata),
      .sysid_control_slave_readdata_from_sa                  (sysid_control_slave_readdata_from_sa),
      .sysid_control_slave_reset_n                           (sysid_control_slave_reset_n)
    );

  sysid the_sysid
    (
      .address  (sysid_control_slave_address),
      .clock    (sysid_control_slave_clock),
      .readdata (sysid_control_slave_readdata),
      .reset_n  (sysid_control_slave_reset_n)
    );

  touch_cs_s1_arbitrator the_touch_cs_s1
    (
      .clk                                           (clk),
      .cpu_data_master_address_to_slave              (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_touch_cs_s1           (cpu_data_master_granted_touch_cs_s1),
      .cpu_data_master_qualified_request_touch_cs_s1 (cpu_data_master_qualified_request_touch_cs_s1),
      .cpu_data_master_read                          (cpu_data_master_read),
      .cpu_data_master_read_data_valid_touch_cs_s1   (cpu_data_master_read_data_valid_touch_cs_s1),
      .cpu_data_master_requests_touch_cs_s1          (cpu_data_master_requests_touch_cs_s1),
      .cpu_data_master_waitrequest                   (cpu_data_master_waitrequest),
      .cpu_data_master_write                         (cpu_data_master_write),
      .cpu_data_master_writedata                     (cpu_data_master_writedata),
      .d1_touch_cs_s1_end_xfer                       (d1_touch_cs_s1_end_xfer),
      .reset_n                                       (clk_reset_n),
      .touch_cs_s1_address                           (touch_cs_s1_address),
      .touch_cs_s1_chipselect                        (touch_cs_s1_chipselect),
      .touch_cs_s1_readdata                          (touch_cs_s1_readdata),
      .touch_cs_s1_readdata_from_sa                  (touch_cs_s1_readdata_from_sa),
      .touch_cs_s1_reset_n                           (touch_cs_s1_reset_n),
      .touch_cs_s1_write_n                           (touch_cs_s1_write_n),
      .touch_cs_s1_writedata                         (touch_cs_s1_writedata)
    );

  touch_cs the_touch_cs
    (
      .address    (touch_cs_s1_address),
      .chipselect (touch_cs_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_touch_cs),
      .readdata   (touch_cs_s1_readdata),
      .reset_n    (touch_cs_s1_reset_n),
      .write_n    (touch_cs_s1_write_n),
      .writedata  (touch_cs_s1_writedata)
    );

  touch_irq_s1_arbitrator the_touch_irq_s1
    (
      .clk                                            (clk),
      .cpu_data_master_address_to_slave               (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_touch_irq_s1           (cpu_data_master_granted_touch_irq_s1),
      .cpu_data_master_qualified_request_touch_irq_s1 (cpu_data_master_qualified_request_touch_irq_s1),
      .cpu_data_master_read                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_touch_irq_s1   (cpu_data_master_read_data_valid_touch_irq_s1),
      .cpu_data_master_requests_touch_irq_s1          (cpu_data_master_requests_touch_irq_s1),
      .cpu_data_master_write                          (cpu_data_master_write),
      .d1_touch_irq_s1_end_xfer                       (d1_touch_irq_s1_end_xfer),
      .reset_n                                        (clk_reset_n),
      .touch_irq_s1_address                           (touch_irq_s1_address),
      .touch_irq_s1_readdata                          (touch_irq_s1_readdata),
      .touch_irq_s1_readdata_from_sa                  (touch_irq_s1_readdata_from_sa),
      .touch_irq_s1_reset_n                           (touch_irq_s1_reset_n)
    );

  touch_irq the_touch_irq
    (
      .address  (touch_irq_s1_address),
      .clk      (clk),
      .in_port  (in_port_to_the_touch_irq),
      .readdata (touch_irq_s1_readdata),
      .reset_n  (touch_irq_s1_reset_n)
    );

  //reset is asserted asynchronously and deasserted synchronously
  CORE_SOPC_reset_clk_domain_synch_module CORE_SOPC_reset_clk_domain_synch
    (
      .clk      (clk),
      .data_in  (1'b1),
      .data_out (clk_reset_n),
      .reset_n  (reset_n_sources)
    );

  //reset sources mux, which is an e_mux
  assign reset_n_sources = ~(~reset_n |
    0 |
    cpu_jtag_debug_module_resetrequest_from_sa |
    cpu_jtag_debug_module_resetrequest_from_sa);

  //sysid_control_slave_clock of type clock does not connect to anything so wire it to default (0)
  assign sysid_control_slave_clock = 0;


endmodule


//synthesis translate_off



// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

// AND HERE WILL BE PRESERVED </ALTERA_NOTE>


// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above

// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif

`include "c:/altera/11.0/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/11.0/quartus/eda/sim_lib/220model.v"
`include "c:/altera/11.0/quartus/eda/sim_lib/sgate.v"
`include "lcd_rd.v"
`include "lcd32_data.v"
`include "sdram.v"
`include "sysid.v"
`include "spi_touch.v"
`include "reset.v"
`include "epcs.v"
`include "jtag_uart.v"
`include "cpu_test_bench.v"
`include "cpu_mult_cell.v"
`include "cpu_oci_test_bench.v"
`include "cpu_jtag_debug_module_tck.v"
`include "cpu_jtag_debug_module_sysclk.v"
`include "cpu_jtag_debug_module_wrapper.v"
`include "cpu.v"
`include "touch_cs.v"
`include "bl_n.v"
`include "lcd_cs.v"
`include "lcd_wr.v"
`include "lcd_rs.v"
`include "touch_irq.v"
`include "bl_p.v"

`timescale 1ns / 1ps

module test_bench 
;


  wire             MISO_to_the_spi_touch;
  wire             MOSI_from_the_spi_touch;
  wire             SCLK_from_the_spi_touch;
  wire             SS_n_from_the_spi_touch;
  wire    [ 15: 0] bidir_port_to_and_from_the_lcd32_data;
  reg              clk;
  wire             data0_to_the_epcs;
  wire             dclk_from_the_epcs;
  wire             epcs_epcs_control_port_dataavailable_from_sa;
  wire             epcs_epcs_control_port_endofpacket_from_sa;
  wire             epcs_epcs_control_port_readyfordata_from_sa;
  wire             in_port_to_the_touch_irq;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  wire             out_port_from_the_bl_n;
  wire             out_port_from_the_bl_p;
  wire             out_port_from_the_lcd_cs;
  wire             out_port_from_the_lcd_rd;
  wire             out_port_from_the_lcd_rs;
  wire             out_port_from_the_lcd_wr;
  wire             out_port_from_the_reset;
  wire             out_port_from_the_touch_cs;
  reg              reset_n;
  wire             sce_from_the_epcs;
  wire             sdo_from_the_epcs;
  wire             spi_touch_spi_control_port_dataavailable_from_sa;
  wire             spi_touch_spi_control_port_endofpacket_from_sa;
  wire             spi_touch_spi_control_port_readyfordata_from_sa;
  wire             sysid_control_slave_clock;
  wire    [ 12: 0] zs_addr_from_the_sdram;
  wire    [  1: 0] zs_ba_from_the_sdram;
  wire             zs_cas_n_from_the_sdram;
  wire             zs_cke_from_the_sdram;
  wire             zs_cs_n_from_the_sdram;
  wire    [ 15: 0] zs_dq_to_and_from_the_sdram;
  wire    [  1: 0] zs_dqm_from_the_sdram;
  wire             zs_ras_n_from_the_sdram;
  wire             zs_we_n_from_the_sdram;


// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
//  add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>

  //Set us up the Dut
  CORE_SOPC DUT
    (
      .MISO_to_the_spi_touch                 (MISO_to_the_spi_touch),
      .MOSI_from_the_spi_touch               (MOSI_from_the_spi_touch),
      .SCLK_from_the_spi_touch               (SCLK_from_the_spi_touch),
      .SS_n_from_the_spi_touch               (SS_n_from_the_spi_touch),
      .bidir_port_to_and_from_the_lcd32_data (bidir_port_to_and_from_the_lcd32_data),
      .clk                                   (clk),
      .data0_to_the_epcs                     (data0_to_the_epcs),
      .dclk_from_the_epcs                    (dclk_from_the_epcs),
      .in_port_to_the_touch_irq              (in_port_to_the_touch_irq),
      .out_port_from_the_bl_n                (out_port_from_the_bl_n),
      .out_port_from_the_bl_p                (out_port_from_the_bl_p),
      .out_port_from_the_lcd_cs              (out_port_from_the_lcd_cs),
      .out_port_from_the_lcd_rd              (out_port_from_the_lcd_rd),
      .out_port_from_the_lcd_rs              (out_port_from_the_lcd_rs),
      .out_port_from_the_lcd_wr              (out_port_from_the_lcd_wr),
      .out_port_from_the_reset               (out_port_from_the_reset),
      .out_port_from_the_touch_cs            (out_port_from_the_touch_cs),
      .reset_n                               (reset_n),
      .sce_from_the_epcs                     (sce_from_the_epcs),
      .sdo_from_the_epcs                     (sdo_from_the_epcs),
      .zs_addr_from_the_sdram                (zs_addr_from_the_sdram),
      .zs_ba_from_the_sdram                  (zs_ba_from_the_sdram),
      .zs_cas_n_from_the_sdram               (zs_cas_n_from_the_sdram),
      .zs_cke_from_the_sdram                 (zs_cke_from_the_sdram),
      .zs_cs_n_from_the_sdram                (zs_cs_n_from_the_sdram),
      .zs_dq_to_and_from_the_sdram           (zs_dq_to_and_from_the_sdram),
      .zs_dqm_from_the_sdram                 (zs_dqm_from_the_sdram),
      .zs_ras_n_from_the_sdram               (zs_ras_n_from_the_sdram),
      .zs_we_n_from_the_sdram                (zs_we_n_from_the_sdram)
    );

  initial
    clk = 1'b0;
  always
    #10 clk <= ~clk;
  
  initial 
    begin
      reset_n <= 0;
      #200 reset_n <= 1;
    end

endmodule


//synthesis translate_on