{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 157 04/27/2011 SJ Full Version " "Info: Version 11.0 Build 157 04/27/2011 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 25 14:49:17 2013 " "Info: Processing started: Mon Feb 25 14:49:17 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LED_hello_world -c LED_hello_world " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LED_hello_world -c LED_hello_world" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "LED_4.v(15) " "Warning (10268): Verilog HDL information at LED_4.v(15): always construct contains both blocking and non-blocking assignments" {  } { { "../../verilog/LED/LED_4.v" "" { Text "E:/Program/EP4CE10/verilog/LED/LED_4.v" 15 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/program/ep4ce10/verilog/led/led_4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /program/ep4ce10/verilog/led/led_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 LED_4 " "Info: Found entity 1: LED_4" {  } { { "../../verilog/LED/LED_4.v" "" { Text "E:/Program/EP4CE10/verilog/LED/LED_4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led_hello_world.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file led_hello_world.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 LED_hello_world " "Info: Found entity 1: LED_hello_world" {  } { { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "LED_hello_world " "Info: Elaborating entity \"LED_hello_world\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "pll.v 1 1 " "Warning: Using design file pll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 PLL " "Info: Found entity 1: PLL" {  } { { "pll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/pll.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL PLL:inst1 " "Info: Elaborating entity \"PLL\" for hierarchy \"PLL:inst1\"" {  } { { "LED_hello_world.bdf" "inst1" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 64 152 392 232 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL:inst1\|altpll:altpll_component\"" {  } { { "pll.v" "altpll_component" { Text "E:/Program/EP4CE10/nios/LCD32/pll.v" 94 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "PLL:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"PLL:inst1\|altpll:altpll_component\"" {  } { { "pll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/pll.v" 94 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "PLL:inst1\|altpll:altpll_component " "Info: Instantiated megafunction \"PLL:inst1\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Info: Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Info: Parameter \"clk0_divide_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1 " "Info: Parameter \"clk0_multiply_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Info: Parameter \"clk1_divide_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Info: Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 1 " "Info: Parameter \"clk1_multiply_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -5556 " "Info: Parameter \"clk1_phase_shift\" = \"-5556\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Info: Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Info: Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=PLL " "Info: Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=PLL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Info: Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Info: Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Info: Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Info: Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Info: Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Info: Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Info: Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Info: Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Info: Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Info: Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Info: Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Info: Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Info: Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Info: Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Info: Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Info: Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Info: Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Info: Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Info: Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Info: Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Info: Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Info: Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Info: Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Info: Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Info: Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Info: Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Info: Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Info: Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Info: Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Info: Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Info: Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Info: Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Info: Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Info: Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Info: Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Info: Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Info: Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Info: Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Info: Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Info: Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Info: Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Info: Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Info: Parameter \"width_clock\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "pll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/pll.v" 94 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL_altpll " "Info: Found entity 1: PLL_altpll" {  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL_altpll PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated " "Info: Elaborating entity \"PLL_altpll\" for hierarchy \"PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "core_sopc.v 22 22 " "Warning: Using design file core_sopc.v, which is not specified as a design file for the current project, but contains definitions for 22 design units and 22 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 bl_n_s1_arbitrator " "Info: Found entity 1: bl_n_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 bl_p_s1_arbitrator " "Info: Found entity 2: bl_p_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 297 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 cpu_jtag_debug_module_arbitrator " "Info: Found entity 3: cpu_jtag_debug_module_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 568 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 cpu_data_master_arbitrator " "Info: Found entity 4: cpu_data_master_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 1009 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 cpu_instruction_master_arbitrator " "Info: Found entity 5: cpu_instruction_master_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 1439 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 epcs_epcs_control_port_arbitrator " "Info: Found entity 6: epcs_epcs_control_port_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 1737 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 jtag_uart_avalon_jtag_slave_arbitrator " "Info: Found entity 7: jtag_uart_avalon_jtag_slave_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 2184 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "8 lcd32_data_s1_arbitrator " "Info: Found entity 8: lcd32_data_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 2493 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "9 lcd_cs_s1_arbitrator " "Info: Found entity 9: lcd_cs_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 2764 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "10 lcd_rd_s1_arbitrator " "Info: Found entity 10: lcd_rd_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 3035 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "11 lcd_rs_s1_arbitrator " "Info: Found entity 11: lcd_rs_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 3306 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "12 lcd_wr_s1_arbitrator " "Info: Found entity 12: lcd_wr_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 3577 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "13 reset_s1_arbitrator " "Info: Found entity 13: reset_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 3848 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "14 rdv_fifo_for_cpu_data_master_to_sdram_s1_module " "Info: Found entity 14: rdv_fifo_for_cpu_data_master_to_sdram_s1_module" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 4119 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "15 rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module " "Info: Found entity 15: rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 4470 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "16 sdram_s1_arbitrator " "Info: Found entity 16: sdram_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 4821 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "17 spi_touch_spi_control_port_arbitrator " "Info: Found entity 17: spi_touch_spi_control_port_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 5336 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "18 sysid_control_slave_arbitrator " "Info: Found entity 18: sysid_control_slave_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 5643 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "19 touch_cs_s1_arbitrator " "Info: Found entity 19: touch_cs_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 5894 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "20 touch_irq_s1_arbitrator " "Info: Found entity 20: touch_irq_s1_arbitrator" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6165 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "21 CORE_SOPC_reset_clk_domain_synch_module " "Info: Found entity 21: CORE_SOPC_reset_clk_domain_synch_module" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6416 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "22 CORE_SOPC " "Info: Found entity 22: CORE_SOPC" {  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6464 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CORE_SOPC CORE_SOPC:inst " "Info: Elaborating entity \"CORE_SOPC\" for hierarchy \"CORE_SOPC:inst\"" {  } { { "LED_hello_world.bdf" "inst" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bl_n_s1_arbitrator CORE_SOPC:inst\|bl_n_s1_arbitrator:the_bl_n_s1 " "Info: Elaborating entity \"bl_n_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|bl_n_s1_arbitrator:the_bl_n_s1\"" {  } { { "core_sopc.v" "the_bl_n_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6861 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "bl_n.v 1 1 " "Warning: Using design file bl_n.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 bl_n " "Info: Found entity 1: bl_n" {  } { { "bl_n.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/bl_n.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bl_n CORE_SOPC:inst\|bl_n:the_bl_n " "Info: Elaborating entity \"bl_n\" for hierarchy \"CORE_SOPC:inst\|bl_n:the_bl_n\"" {  } { { "core_sopc.v" "the_bl_n" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6873 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bl_p_s1_arbitrator CORE_SOPC:inst\|bl_p_s1_arbitrator:the_bl_p_s1 " "Info: Elaborating entity \"bl_p_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|bl_p_s1_arbitrator:the_bl_p_s1\"" {  } { { "core_sopc.v" "the_bl_p_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6896 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "bl_p.v 1 1 " "Warning: Using design file bl_p.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 bl_p " "Info: Found entity 1: bl_p" {  } { { "bl_p.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/bl_p.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bl_p CORE_SOPC:inst\|bl_p:the_bl_p " "Info: Elaborating entity \"bl_p\" for hierarchy \"CORE_SOPC:inst\|bl_p:the_bl_p\"" {  } { { "core_sopc.v" "the_bl_p" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6908 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module_arbitrator CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module " "Info: Elaborating entity \"cpu_jtag_debug_module_arbitrator\" for hierarchy \"CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\"" {  } { { "core_sopc.v" "the_cpu_jtag_debug_module" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6946 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_data_master_arbitrator CORE_SOPC:inst\|cpu_data_master_arbitrator:the_cpu_data_master " "Info: Elaborating entity \"cpu_data_master_arbitrator\" for hierarchy \"CORE_SOPC:inst\|cpu_data_master_arbitrator:the_cpu_data_master\"" {  } { { "core_sopc.v" "the_cpu_data_master" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7066 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_instruction_master_arbitrator CORE_SOPC:inst\|cpu_instruction_master_arbitrator:the_cpu_instruction_master " "Info: Elaborating entity \"cpu_instruction_master_arbitrator\" for hierarchy \"CORE_SOPC:inst\|cpu_instruction_master_arbitrator:the_cpu_instruction_master\"" {  } { { "core_sopc.v" "the_cpu_instruction_master" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7100 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.v 25 25 " "Info: Found 25 design units, including 25 entities, in source file cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_ic_data_module " "Info: Found entity 1: cpu_ic_data_module" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 cpu_ic_tag_module " "Info: Found entity 2: cpu_ic_tag_module" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 86 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 cpu_bht_module " "Info: Found entity 3: cpu_bht_module" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 152 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 cpu_register_bank_a_module " "Info: Found entity 4: cpu_register_bank_a_module" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 218 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 cpu_register_bank_b_module " "Info: Found entity 5: cpu_register_bank_b_module" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 281 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 cpu_nios2_oci_debug " "Info: Found entity 6: cpu_nios2_oci_debug" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 344 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 cpu_ociram_lpm_dram_bdp_component_module " "Info: Found entity 7: cpu_ociram_lpm_dram_bdp_component_module" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 472 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "8 cpu_nios2_ocimem " "Info: Found entity 8: cpu_nios2_ocimem" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 565 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "9 cpu_nios2_avalon_reg " "Info: Found entity 9: cpu_nios2_avalon_reg" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 711 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "10 cpu_nios2_oci_break " "Info: Found entity 10: cpu_nios2_oci_break" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 805 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "11 cpu_nios2_oci_xbrk " "Info: Found entity 11: cpu_nios2_oci_xbrk" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1099 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "12 cpu_nios2_oci_dbrk " "Info: Found entity 12: cpu_nios2_oci_dbrk" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1359 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "13 cpu_nios2_oci_itrace " "Info: Found entity 13: cpu_nios2_oci_itrace" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1547 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "14 cpu_nios2_oci_td_mode " "Info: Found entity 14: cpu_nios2_oci_td_mode" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1846 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "15 cpu_nios2_oci_dtrace " "Info: Found entity 15: cpu_nios2_oci_dtrace" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1913 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "16 cpu_nios2_oci_compute_tm_count " "Info: Found entity 16: cpu_nios2_oci_compute_tm_count" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2007 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "17 cpu_nios2_oci_fifowp_inc " "Info: Found entity 17: cpu_nios2_oci_fifowp_inc" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2078 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "18 cpu_nios2_oci_fifocount_inc " "Info: Found entity 18: cpu_nios2_oci_fifocount_inc" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2120 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "19 cpu_nios2_oci_fifo " "Info: Found entity 19: cpu_nios2_oci_fifo" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2166 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "20 cpu_nios2_oci_pib " "Info: Found entity 20: cpu_nios2_oci_pib" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2671 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "21 cpu_traceram_lpm_dram_bdp_component_module " "Info: Found entity 21: cpu_traceram_lpm_dram_bdp_component_module" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2739 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "22 cpu_nios2_oci_im " "Info: Found entity 22: cpu_nios2_oci_im" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2828 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "23 cpu_nios2_performance_monitors " "Info: Found entity 23: cpu_nios2_performance_monitors" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2965 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "24 cpu_nios2_oci " "Info: Found entity 24: cpu_nios2_oci" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2981 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "25 cpu " "Info: Found entity 25: cpu" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3484 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "cpu.v(1814) " "Warning (10037): Verilog HDL or VHDL warning at cpu.v(1814): conditional expression evaluates to a constant" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1814 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "cpu.v(1816) " "Warning (10037): Verilog HDL or VHDL warning at cpu.v(1816): conditional expression evaluates to a constant" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1816 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "cpu.v(1972) " "Warning (10037): Verilog HDL or VHDL warning at cpu.v(1972): conditional expression evaluates to a constant" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1972 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "cpu.v(2891) " "Warning (10037): Verilog HDL or VHDL warning at cpu.v(2891): conditional expression evaluates to a constant" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2891 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu CORE_SOPC:inst\|cpu:the_cpu " "Info: Elaborating entity \"cpu\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\"" {  } { { "core_sopc.v" "the_cpu" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_test_bench.v 1 1 " "Warning: Using design file cpu_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_test_bench " "Info: Found entity 1: cpu_test_bench" {  } { { "cpu_test_bench.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_test_bench.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_test_bench CORE_SOPC:inst\|cpu:the_cpu\|cpu_test_bench:the_cpu_test_bench " "Info: Elaborating entity \"cpu_test_bench\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_test_bench:the_cpu_test_bench\"" {  } { { "cpu.v" "the_cpu_test_bench" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 5541 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_ic_data_module CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data " "Info: Elaborating entity \"cpu_ic_data_module\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\"" {  } { { "cpu.v" "cpu_ic_data" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 6566 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 58 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 512 " "Info: Parameter \"numwords_a\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 512 " "Info: Parameter \"numwords_b\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 9 " "Info: Parameter \"widthad_a\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 9 " "Info: Parameter \"widthad_b\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 58 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_udd1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_udd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_udd1 " "Info: Found entity 1: altsyncram_udd1" {  } { { "db/altsyncram_udd1.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_udd1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_udd1 CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_udd1:auto_generated " "Info: Elaborating entity \"altsyncram_udd1\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_udd1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_ic_tag_module CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag " "Info: Elaborating entity \"cpu_ic_tag_module\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\"" {  } { { "cpu.v" "cpu_ic_tag" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 6632 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 123 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 123 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_ic_tag_ram.mif " "Info: Parameter \"init_file\" = \"cpu_ic_tag_ram.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 64 " "Info: Parameter \"numwords_a\" = \"64\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 64 " "Info: Parameter \"numwords_b\" = \"64\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 24 " "Info: Parameter \"width_a\" = \"24\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 24 " "Info: Parameter \"width_b\" = \"24\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 6 " "Info: Parameter \"widthad_a\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 6 " "Info: Parameter \"widthad_b\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 123 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_i2g1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_i2g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_i2g1 " "Info: Found entity 1: altsyncram_i2g1" {  } { { "db/altsyncram_i2g1.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_i2g1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_i2g1 CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_i2g1:auto_generated " "Info: Elaborating entity \"altsyncram_i2g1\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_i2g1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_bht_module CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht " "Info: Elaborating entity \"cpu_bht_module\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\"" {  } { { "cpu.v" "cpu_bht" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 6836 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 189 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 189 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_bht_ram.mif " "Info: Parameter \"init_file\" = \"cpu_bht_ram.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Info: Parameter \"numwords_b\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Info: Parameter \"width_a\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Info: Parameter \"width_b\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Info: Parameter \"widthad_b\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 189 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_bpf1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bpf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_bpf1 " "Info: Found entity 1: altsyncram_bpf1" {  } { { "db/altsyncram_bpf1.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_bpf1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_bpf1 CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\|altsyncram:the_altsyncram\|altsyncram_bpf1:auto_generated " "Info: Elaborating entity \"altsyncram_bpf1\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_bht_module:cpu_bht\|altsyncram:the_altsyncram\|altsyncram_bpf1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_register_bank_a_module CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a " "Info: Elaborating entity \"cpu_register_bank_a_module\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\"" {  } { { "cpu.v" "cpu_register_bank_a" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 6982 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 252 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 252 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_rf_ram_a.mif " "Info: Parameter \"init_file\" = \"cpu_rf_ram_a.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Info: Parameter \"numwords_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Info: Parameter \"numwords_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Info: Parameter \"widthad_a\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Info: Parameter \"widthad_b\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 252 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_b7f1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_b7f1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_b7f1 " "Info: Found entity 1: altsyncram_b7f1" {  } { { "db/altsyncram_b7f1.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_b7f1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_b7f1 CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_b7f1:auto_generated " "Info: Elaborating entity \"altsyncram_b7f1\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_b7f1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_register_bank_b_module CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b " "Info: Elaborating entity \"cpu_register_bank_b_module\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\"" {  } { { "cpu.v" "cpu_register_bank_b" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 7003 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 315 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 315 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_rf_ram_b.mif " "Info: Parameter \"init_file\" = \"cpu_rf_ram_b.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Info: Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Info: Parameter \"numwords_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Info: Parameter \"numwords_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Info: Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Info: Parameter \"widthad_a\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Info: Parameter \"widthad_b\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 315 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_c7f1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_c7f1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_c7f1 " "Info: Found entity 1: altsyncram_c7f1" {  } { { "db/altsyncram_c7f1.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_c7f1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_c7f1 CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_c7f1:auto_generated " "Info: Elaborating entity \"altsyncram_c7f1\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_c7f1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_mult_cell.v 1 1 " "Warning: Using design file cpu_mult_cell.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_mult_cell " "Info: Found entity 1: cpu_mult_cell" {  } { { "cpu_mult_cell.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_mult_cell.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_mult_cell CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell " "Info: Elaborating entity \"cpu_mult_cell\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\"" {  } { { "cpu.v" "the_cpu_mult_cell" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8526 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Info: Elaborating entity \"altmult_add\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" {  } { { "cpu_mult_cell.v" "the_altmult_add_part_1" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_mult_cell.v" 52 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" {  } { { "cpu_mult_cell.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_mult_cell.v" 52 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Info: Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Info: Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Info: Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Info: Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Info: Parameter \"input_register_a0\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Info: Parameter \"input_register_b0\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Info: Parameter \"input_source_a0\" = \"DATAA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Info: Parameter \"input_source_b0\" = \"DATAB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Info: Parameter \"intended_device_family\" = \"CYCLONEIVE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Info: Parameter \"lpm_type\" = \"altmult_add\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Info: Parameter \"multiplier1_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Info: Parameter \"multiplier_aclr0\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Info: Parameter \"multiplier_register0\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Info: Parameter \"number_of_multipliers\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Info: Parameter \"output_register\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Info: Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Info: Parameter \"port_signa\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Info: Parameter \"port_signb\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Info: Parameter \"representation_a\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Info: Parameter \"representation_b\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Info: Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Info: Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Info: Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Info: Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Info: Parameter \"signed_register_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Info: Parameter \"signed_register_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Info: Parameter \"width_a\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Info: Parameter \"width_b\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 32 " "Info: Parameter \"width_result\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_mult_cell.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_mult_cell.v" 52 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_mgr2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_mgr2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_mgr2 " "Info: Found entity 1: mult_add_mgr2" {  } { { "db/mult_add_mgr2.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/mult_add_mgr2.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_mgr2 CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_mgr2:auto_generated " "Info: Elaborating entity \"mult_add_mgr2\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_mgr2:auto_generated\"" {  } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_ks81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_ks81 " "Info: Found entity 1: ded_mult_ks81" {  } { { "db/ded_mult_ks81.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/ded_mult_ks81.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_ks81 CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_mgr2:auto_generated\|ded_mult_ks81:ded_mult1 " "Info: Elaborating entity \"ded_mult_ks81\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_mgr2:auto_generated\|ded_mult_ks81:ded_mult1\"" {  } { { "db/mult_add_mgr2.tdf" "ded_mult1" { Text "E:/Program/EP4CE10/nios/LCD32/db/mult_add_mgr2.tdf" 33 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_93c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_93c " "Info: Found entity 1: dffpipe_93c" {  } { { "db/dffpipe_93c.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/dffpipe_93c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_93c CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_mgr2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result " "Info: Elaborating entity \"dffpipe_93c\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_mgr2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result\"" {  } { { "db/ded_mult_ks81.tdf" "pre_result" { Text "E:/Program/EP4CE10/nios/LCD32/db/ded_mult_ks81.tdf" 50 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Info: Elaborating entity \"altmult_add\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" {  } { { "cpu_mult_cell.v" "the_altmult_add_part_2" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_mult_cell.v" 92 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" {  } { { "cpu_mult_cell.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_mult_cell.v" 92 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Info: Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Info: Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Info: Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Info: Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Info: Parameter \"input_register_a0\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Info: Parameter \"input_register_b0\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Info: Parameter \"input_source_a0\" = \"DATAA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Info: Parameter \"input_source_b0\" = \"DATAB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Info: Parameter \"intended_device_family\" = \"CYCLONEIVE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Info: Parameter \"lpm_type\" = \"altmult_add\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Info: Parameter \"multiplier1_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Info: Parameter \"multiplier_aclr0\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Info: Parameter \"multiplier_register0\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Info: Parameter \"number_of_multipliers\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Info: Parameter \"output_register\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Info: Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Info: Parameter \"port_signa\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Info: Parameter \"port_signb\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Info: Parameter \"representation_a\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Info: Parameter \"representation_b\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Info: Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Info: Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Info: Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Info: Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Info: Parameter \"signed_register_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Info: Parameter \"signed_register_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Info: Parameter \"width_a\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Info: Parameter \"width_b\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 16 " "Info: Parameter \"width_result\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_mult_cell.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_mult_cell.v" 92 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_ogr2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_ogr2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_ogr2 " "Info: Found entity 1: mult_add_ogr2" {  } { { "db/mult_add_ogr2.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/mult_add_ogr2.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_ogr2 CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_ogr2:auto_generated " "Info: Elaborating entity \"mult_add_ogr2\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_ogr2:auto_generated\"" {  } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci " "Info: Elaborating entity \"cpu_nios2_oci\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\"" {  } { { "cpu.v" "the_cpu_nios2_oci" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_debug CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug " "Info: Elaborating entity \"cpu_nios2_oci_debug\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\"" {  } { { "cpu.v" "the_cpu_nios2_oci_debug" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3192 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_ocimem CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem " "Info: Elaborating entity \"cpu_nios2_ocimem\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\"" {  } { { "cpu.v" "the_cpu_nios2_ocimem" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3212 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_ociram_lpm_dram_bdp_component_module CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component " "Info: Elaborating entity \"cpu_ociram_lpm_dram_bdp_component_module\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\"" {  } { { "cpu.v" "cpu_ociram_lpm_dram_bdp_component" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 678 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 526 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 526 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Info: Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Info: Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file cpu_ociram_default_contents.mif " "Info: Parameter \"init_file\" = \"cpu_ociram_default_contents.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Info: Parameter \"intended_device_family\" = \"CYCLONEIVE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Info: Parameter \"numwords_b\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Info: Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Info: Parameter \"width_b\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Info: Parameter \"width_byteena_a\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Info: Parameter \"widthad_b\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Info: Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 526 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_f572.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f572.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_f572 " "Info: Found entity 1: altsyncram_f572" {  } { { "db/altsyncram_f572.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_f572.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_f572 CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_f572:auto_generated " "Info: Elaborating entity \"altsyncram_f572\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_f572:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_avalon_reg CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg " "Info: Elaborating entity \"cpu_nios2_avalon_reg\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\"" {  } { { "cpu.v" "the_cpu_nios2_avalon_reg" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3232 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_break CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break " "Info: Elaborating entity \"cpu_nios2_oci_break\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\"" {  } { { "cpu.v" "the_cpu_nios2_oci_break" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3263 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_xbrk CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk " "Info: Elaborating entity \"cpu_nios2_oci_xbrk\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\"" {  } { { "cpu.v" "the_cpu_nios2_oci_xbrk" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3286 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_dbrk CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk " "Info: Elaborating entity \"cpu_nios2_oci_dbrk\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\"" {  } { { "cpu.v" "the_cpu_nios2_oci_dbrk" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3313 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_itrace CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace " "Info: Elaborating entity \"cpu_nios2_oci_itrace\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\"" {  } { { "cpu.v" "the_cpu_nios2_oci_itrace" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3354 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_dtrace CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace " "Info: Elaborating entity \"cpu_nios2_oci_dtrace\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace\"" {  } { { "cpu.v" "the_cpu_nios2_oci_dtrace" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3369 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_td_mode CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace\|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode " "Info: Elaborating entity \"cpu_nios2_oci_td_mode\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace\|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode\"" {  } { { "cpu.v" "cpu_nios2_oci_trc_ctrl_td_mode" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 1961 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_fifo CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo " "Info: Elaborating entity \"cpu_nios2_oci_fifo\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\"" {  } { { "cpu.v" "the_cpu_nios2_oci_fifo" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3388 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_compute_tm_count CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count " "Info: Elaborating entity \"cpu_nios2_oci_compute_tm_count\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count\"" {  } { { "cpu.v" "cpu_nios2_oci_compute_tm_count_tm_count" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2293 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_fifowp_inc CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp " "Info: Elaborating entity \"cpu_nios2_oci_fifowp_inc\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp\"" {  } { { "cpu.v" "cpu_nios2_oci_fifowp_inc_fifowp" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2303 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_fifocount_inc CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount " "Info: Elaborating entity \"cpu_nios2_oci_fifocount_inc\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount\"" {  } { { "cpu.v" "cpu_nios2_oci_fifocount_inc_fifocount" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2313 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_oci_test_bench.v 1 1 " "Warning: Using design file cpu_oci_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_oci_test_bench " "Info: Found entity 1: cpu_oci_test_bench" {  } { { "cpu_oci_test_bench.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_oci_test_bench.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_oci_test_bench CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_oci_test_bench:the_cpu_oci_test_bench " "Info: Elaborating entity \"cpu_oci_test_bench\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_oci_test_bench:the_cpu_oci_test_bench\"" {  } { { "cpu.v" "the_cpu_oci_test_bench" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2322 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_EMPTY_SHELL" "cpu_oci_test_bench " "Warning: Entity \"cpu_oci_test_bench\" contains only dangling pins" {  } { { "cpu.v" "the_cpu_oci_test_bench" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2322 0 0 } }  } 0 0 "Entity \"%1!s!\" contains only dangling pins" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_pib CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib " "Info: Elaborating entity \"cpu_nios2_oci_pib\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib\"" {  } { { "cpu.v" "the_cpu_nios2_oci_pib" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3398 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_im CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im " "Info: Elaborating entity \"cpu_nios2_oci_im\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\"" {  } { { "cpu.v" "the_cpu_nios2_oci_im" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_traceram_lpm_dram_bdp_component_module CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component " "Info: Elaborating entity \"cpu_traceram_lpm_dram_bdp_component_module\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\"" {  } { { "cpu.v" "cpu_traceram_lpm_dram_bdp_component" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Info: Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Info: Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Info: Parameter \"init_file\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Info: Parameter \"intended_device_family\" = \"CYCLONEIVE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Info: Parameter \"numwords_a\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Info: Parameter \"numwords_b\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Info: Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Info: Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Info: Parameter \"width_a\" = \"36\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Info: Parameter \"width_b\" = \"36\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Info: Parameter \"widthad_a\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Info: Parameter \"widthad_b\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Info: Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0a02.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0a02 " "Info: Found entity 1: altsyncram_0a02" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0a02 CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated " "Info: Elaborating entity \"altsyncram_0a02\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_jtag_debug_module_wrapper.v 1 1 " "Warning: Using design file cpu_jtag_debug_module_wrapper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_jtag_debug_module_wrapper " "Info: Found entity 1: cpu_jtag_debug_module_wrapper" {  } { { "cpu_jtag_debug_module_wrapper.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_wrapper.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module_wrapper CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper " "Info: Elaborating entity \"cpu_jtag_debug_module_wrapper\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\"" {  } { { "cpu.v" "the_cpu_jtag_debug_module_wrapper" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3462 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_jtag_debug_module_tck.v 1 1 " "Warning: Using design file cpu_jtag_debug_module_tck.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_jtag_debug_module_tck " "Info: Found entity 1: cpu_jtag_debug_module_tck" {  } { { "cpu_jtag_debug_module_tck.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_tck.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module_tck CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck " "Info: Elaborating entity \"cpu_jtag_debug_module_tck\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\"" {  } { { "cpu_jtag_debug_module_wrapper.v" "the_cpu_jtag_debug_module_tck" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_wrapper.v" 165 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Info: Elaborating entity \"altera_std_synchronizer\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" {  } { { "cpu_jtag_debug_module_tck.v" "the_altera_std_synchronizer" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_tck.v" 202 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" {  } { { "cpu_jtag_debug_module_tck.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_tck.v" 202 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Info: Parameter \"depth\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_jtag_debug_module_tck.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_tck.v" 202 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_jtag_debug_module_sysclk.v 1 1 " "Warning: Using design file cpu_jtag_debug_module_sysclk.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_jtag_debug_module_sysclk " "Info: Found entity 1: cpu_jtag_debug_module_sysclk" {  } { { "cpu_jtag_debug_module_sysclk.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_sysclk.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module_sysclk CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk " "Info: Elaborating entity \"cpu_jtag_debug_module_sysclk\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk\"" {  } { { "cpu_jtag_debug_module_wrapper.v" "the_cpu_jtag_debug_module_sysclk" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_wrapper.v" 188 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy " "Info: Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy\"" {  } { { "cpu_jtag_debug_module_wrapper.v" "cpu_jtag_debug_module_phy" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_wrapper.v" 218 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy\"" {  } { { "cpu_jtag_debug_module_wrapper.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_wrapper.v" 218 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Info: Parameter \"sld_auto_instance_index\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Info: Parameter \"sld_instance_index\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Info: Parameter \"sld_ir_width\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Info: Parameter \"sld_mfg_id\" = \"70\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action  " "Info: Parameter \"sld_sim_action\" = \"\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Info: Parameter \"sld_sim_n_scan\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Info: Parameter \"sld_sim_total_length\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Info: Parameter \"sld_type_id\" = \"34\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Info: Parameter \"sld_version\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu_jtag_debug_module_wrapper.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_wrapper.v" 218 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Info: Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" {  } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/11.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:cpu_jtag_debug_module_phy\"" {  } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "cpu_jtag_debug_module_wrapper.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu_jtag_debug_module_wrapper.v" 218 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs_epcs_control_port_arbitrator CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port " "Info: Elaborating entity \"epcs_epcs_control_port_arbitrator\" for hierarchy \"CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\"" {  } { { "core_sopc.v" "the_epcs_epcs_control_port" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7168 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "epcs.v 2 2 " "Warning: Using design file epcs.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 epcs_sub " "Info: Found entity 1: epcs_sub" {  } { { "epcs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 41 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 epcs " "Info: Found entity 2: epcs" {  } { { "epcs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 424 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "epcs.v(401) " "Warning (10037): Verilog HDL or VHDL warning at epcs.v(401): conditional expression evaluates to a constant" {  } { { "epcs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 401 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs CORE_SOPC:inst\|epcs:the_epcs " "Info: Elaborating entity \"epcs\" for hierarchy \"CORE_SOPC:inst\|epcs:the_epcs\"" {  } { { "core_sopc.v" "the_epcs" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7188 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs_sub CORE_SOPC:inst\|epcs:the_epcs\|epcs_sub:the_epcs_sub " "Info: Elaborating entity \"epcs_sub\" for hierarchy \"CORE_SOPC:inst\|epcs:the_epcs\|epcs_sub:the_epcs_sub\"" {  } { { "epcs.v" "the_epcs_sub" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 502 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CORE_SOPC:inst\|epcs:the_epcs\|altsyncram:the_boot_copier_rom " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CORE_SOPC:inst\|epcs:the_epcs\|altsyncram:the_boot_copier_rom\"" {  } { { "epcs.v" "the_boot_copier_rom" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 543 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|epcs:the_epcs\|altsyncram:the_boot_copier_rom " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|epcs:the_epcs\|altsyncram:the_boot_copier_rom\"" {  } { { "epcs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 543 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|epcs:the_epcs\|altsyncram:the_boot_copier_rom " "Info: Instantiated megafunction \"CORE_SOPC:inst\|epcs:the_epcs\|altsyncram:the_boot_copier_rom\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Info: Parameter \"byte_size\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file epcs_boot_rom_synth.hex " "Info: Parameter \"init_file\" = \"epcs_boot_rom_synth.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Info: Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Info: Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Info: Parameter \"width_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "epcs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 543 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sc31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sc31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sc31 " "Info: Found entity 1: altsyncram_sc31" {  } { { "db/altsyncram_sc31.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_sc31.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sc31 CORE_SOPC:inst\|epcs:the_epcs\|altsyncram:the_boot_copier_rom\|altsyncram_sc31:auto_generated " "Info: Elaborating entity \"altsyncram_sc31\" for hierarchy \"CORE_SOPC:inst\|epcs:the_epcs\|altsyncram:the_boot_copier_rom\|altsyncram_sc31:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_avalon_jtag_slave_arbitrator CORE_SOPC:inst\|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave " "Info: Elaborating entity \"jtag_uart_avalon_jtag_slave_arbitrator\" for hierarchy \"CORE_SOPC:inst\|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave\"" {  } { { "core_sopc.v" "the_jtag_uart_avalon_jtag_slave" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7220 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "jtag_uart.v 7 7 " "Warning: Using design file jtag_uart.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 jtag_uart_log_module " "Info: Found entity 1: jtag_uart_log_module" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 jtag_uart_sim_scfifo_w " "Info: Found entity 2: jtag_uart_sim_scfifo_w" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 68 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 jtag_uart_scfifo_w " "Info: Found entity 3: jtag_uart_scfifo_w" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 126 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "4 jtag_uart_drom_module " "Info: Found entity 4: jtag_uart_drom_module" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 211 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "5 jtag_uart_sim_scfifo_r " "Info: Found entity 5: jtag_uart_sim_scfifo_r" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 365 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "6 jtag_uart_scfifo_r " "Info: Found entity 6: jtag_uart_scfifo_r" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 453 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "7 jtag_uart " "Info: Found entity 7: jtag_uart" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 540 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart CORE_SOPC:inst\|jtag_uart:the_jtag_uart " "Info: Elaborating entity \"jtag_uart\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\"" {  } { { "core_sopc.v" "the_jtag_uart" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7236 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_scfifo_w CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w " "Info: Elaborating entity \"jtag_uart_scfifo_w\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\"" {  } { { "jtag_uart.v" "the_jtag_uart_scfifo_w" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 628 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo " "Info: Elaborating entity \"scfifo\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\"" {  } { { "jtag_uart.v" "wfifo" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 186 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\"" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 186 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo " "Info: Instantiated megafunction \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Info: Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Info: Parameter \"lpm_numwords\" = \"64\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Info: Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Info: Parameter \"lpm_type\" = \"scfifo\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Info: Parameter \"lpm_width\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Info: Parameter \"lpm_widthu\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Info: Parameter \"overflow_checking\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Info: Parameter \"underflow_checking\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Info: Parameter \"use_eab\" = \"ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 186 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Info: Found entity 1: scfifo_jr21" {  } { { "db/scfifo_jr21.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/scfifo_jr21.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Info: Elaborating entity \"scfifo_jr21\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/11.0/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Info: Found entity 1: a_dpfifo_q131" {  } { { "db/a_dpfifo_q131.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/a_dpfifo_q131.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Info: Elaborating entity \"a_dpfifo_q131\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" {  } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "E:/Program/EP4CE10/nios/LCD32/db/scfifo_jr21.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Info: Found entity 1: a_fefifo_7cf" {  } { { "db/a_fefifo_7cf.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/a_fefifo_7cf.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Info: Elaborating entity \"a_fefifo_7cf\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" {  } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "E:/Program/EP4CE10/nios/LCD32/db/a_dpfifo_q131.tdf" 42 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Info: Found entity 1: cntr_do7" {  } { { "db/cntr_do7.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/cntr_do7.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Info: Elaborating entity \"cntr_do7\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" {  } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "E:/Program/EP4CE10/nios/LCD32/db/a_fefifo_7cf.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Info: Found entity 1: dpram_nl21" {  } { { "db/dpram_nl21.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/dpram_nl21.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Info: Elaborating entity \"dpram_nl21\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" {  } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "E:/Program/EP4CE10/nios/LCD32/db/a_dpfifo_q131.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Info: Found entity 1: altsyncram_r1m1" {  } { { "db/altsyncram_r1m1.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_r1m1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Info: Elaborating entity \"altsyncram_r1m1\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" {  } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "E:/Program/EP4CE10/nios/LCD32/db/dpram_nl21.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Info: Found entity 1: cntr_1ob" {  } { { "db/cntr_1ob.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/cntr_1ob.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Info: Elaborating entity \"cntr_1ob\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" {  } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "E:/Program/EP4CE10/nios/LCD32/db/a_dpfifo_q131.tdf" 44 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_scfifo_r CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r " "Info: Elaborating entity \"jtag_uart_scfifo_r\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r\"" {  } { { "jtag_uart.v" "the_jtag_uart_scfifo_r" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 642 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic " "Info: Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\"" {  } { { "jtag_uart.v" "jtag_uart_alt_jtag_atlantic" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 777 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\"" {  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 777 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic " "Info: Instantiated megafunction \"CORE_SOPC:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Info: Parameter \"INSTANCE_ID\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Info: Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Info: Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Info: Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 777 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd32_data_s1_arbitrator CORE_SOPC:inst\|lcd32_data_s1_arbitrator:the_lcd32_data_s1 " "Info: Elaborating entity \"lcd32_data_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|lcd32_data_s1_arbitrator:the_lcd32_data_s1\"" {  } { { "core_sopc.v" "the_lcd32_data_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7259 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "lcd32_data.v 1 1 " "Warning: Using design file lcd32_data.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lcd32_data " "Info: Found entity 1: lcd32_data" {  } { { "lcd32_data.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/lcd32_data.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd32_data CORE_SOPC:inst\|lcd32_data:the_lcd32_data " "Info: Elaborating entity \"lcd32_data\" for hierarchy \"CORE_SOPC:inst\|lcd32_data:the_lcd32_data\"" {  } { { "core_sopc.v" "the_lcd32_data" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7271 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_cs_s1_arbitrator CORE_SOPC:inst\|lcd_cs_s1_arbitrator:the_lcd_cs_s1 " "Info: Elaborating entity \"lcd_cs_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|lcd_cs_s1_arbitrator:the_lcd_cs_s1\"" {  } { { "core_sopc.v" "the_lcd_cs_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7294 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "lcd_cs.v 1 1 " "Warning: Using design file lcd_cs.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_cs " "Info: Found entity 1: lcd_cs" {  } { { "lcd_cs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/lcd_cs.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_cs CORE_SOPC:inst\|lcd_cs:the_lcd_cs " "Info: Elaborating entity \"lcd_cs\" for hierarchy \"CORE_SOPC:inst\|lcd_cs:the_lcd_cs\"" {  } { { "core_sopc.v" "the_lcd_cs" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7306 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_rd_s1_arbitrator CORE_SOPC:inst\|lcd_rd_s1_arbitrator:the_lcd_rd_s1 " "Info: Elaborating entity \"lcd_rd_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|lcd_rd_s1_arbitrator:the_lcd_rd_s1\"" {  } { { "core_sopc.v" "the_lcd_rd_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7329 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "lcd_rd.v 1 1 " "Warning: Using design file lcd_rd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_rd " "Info: Found entity 1: lcd_rd" {  } { { "lcd_rd.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/lcd_rd.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_rd CORE_SOPC:inst\|lcd_rd:the_lcd_rd " "Info: Elaborating entity \"lcd_rd\" for hierarchy \"CORE_SOPC:inst\|lcd_rd:the_lcd_rd\"" {  } { { "core_sopc.v" "the_lcd_rd" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7341 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_rs_s1_arbitrator CORE_SOPC:inst\|lcd_rs_s1_arbitrator:the_lcd_rs_s1 " "Info: Elaborating entity \"lcd_rs_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|lcd_rs_s1_arbitrator:the_lcd_rs_s1\"" {  } { { "core_sopc.v" "the_lcd_rs_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7364 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "lcd_rs.v 1 1 " "Warning: Using design file lcd_rs.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_rs " "Info: Found entity 1: lcd_rs" {  } { { "lcd_rs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/lcd_rs.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_rs CORE_SOPC:inst\|lcd_rs:the_lcd_rs " "Info: Elaborating entity \"lcd_rs\" for hierarchy \"CORE_SOPC:inst\|lcd_rs:the_lcd_rs\"" {  } { { "core_sopc.v" "the_lcd_rs" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7376 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_wr_s1_arbitrator CORE_SOPC:inst\|lcd_wr_s1_arbitrator:the_lcd_wr_s1 " "Info: Elaborating entity \"lcd_wr_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|lcd_wr_s1_arbitrator:the_lcd_wr_s1\"" {  } { { "core_sopc.v" "the_lcd_wr_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7399 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "lcd_wr.v 1 1 " "Warning: Using design file lcd_wr.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_wr " "Info: Found entity 1: lcd_wr" {  } { { "lcd_wr.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/lcd_wr.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_wr CORE_SOPC:inst\|lcd_wr:the_lcd_wr " "Info: Elaborating entity \"lcd_wr\" for hierarchy \"CORE_SOPC:inst\|lcd_wr:the_lcd_wr\"" {  } { { "core_sopc.v" "the_lcd_wr" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7411 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset_s1_arbitrator CORE_SOPC:inst\|reset_s1_arbitrator:the_reset_s1 " "Info: Elaborating entity \"reset_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|reset_s1_arbitrator:the_reset_s1\"" {  } { { "core_sopc.v" "the_reset_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7434 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "reset.v 1 1 " "Warning: Using design file reset.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 reset " "Info: Found entity 1: reset" {  } { { "reset.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/reset.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset CORE_SOPC:inst\|reset:the_reset " "Info: Elaborating entity \"reset\" for hierarchy \"CORE_SOPC:inst\|reset:the_reset\"" {  } { { "core_sopc.v" "the_reset" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7446 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_s1_arbitrator CORE_SOPC:inst\|sdram_s1_arbitrator:the_sdram_s1 " "Info: Elaborating entity \"sdram_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|sdram_s1_arbitrator:the_sdram_s1\"" {  } { { "core_sopc.v" "the_sdram_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7488 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_cpu_data_master_to_sdram_s1_module CORE_SOPC:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1 " "Info: Elaborating entity \"rdv_fifo_for_cpu_data_master_to_sdram_s1_module\" for hierarchy \"CORE_SOPC:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\"" {  } { { "core_sopc.v" "rdv_fifo_for_cpu_data_master_to_sdram_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 5105 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module CORE_SOPC:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1 " "Info: Elaborating entity \"rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module\" for hierarchy \"CORE_SOPC:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\"" {  } { { "core_sopc.v" "rdv_fifo_for_cpu_instruction_master_to_sdram_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 5143 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "sdram.v 2 2 " "Warning: Using design file sdram.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_input_efifo_module " "Info: Found entity 1: sdram_input_efifo_module" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 sdram " "Info: Found entity 2: sdram" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 158 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "sdram.v(316) " "Warning (10037): Verilog HDL or VHDL warning at sdram.v(316): conditional expression evaluates to a constant" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 316 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "sdram.v(326) " "Warning (10037): Verilog HDL or VHDL warning at sdram.v(326): conditional expression evaluates to a constant" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 326 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "sdram.v(336) " "Warning (10037): Verilog HDL or VHDL warning at sdram.v(336): conditional expression evaluates to a constant" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 336 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "sdram.v(680) " "Warning (10037): Verilog HDL or VHDL warning at sdram.v(680): conditional expression evaluates to a constant" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 680 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram CORE_SOPC:inst\|sdram:the_sdram " "Info: Elaborating entity \"sdram\" for hierarchy \"CORE_SOPC:inst\|sdram:the_sdram\"" {  } { { "core_sopc.v" "the_sdram" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7512 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_input_efifo_module CORE_SOPC:inst\|sdram:the_sdram\|sdram_input_efifo_module:the_sdram_input_efifo_module " "Info: Elaborating entity \"sdram_input_efifo_module\" for hierarchy \"CORE_SOPC:inst\|sdram:the_sdram\|sdram_input_efifo_module:the_sdram_input_efifo_module\"" {  } { { "sdram.v" "the_sdram_input_efifo_module" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 296 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_touch_spi_control_port_arbitrator CORE_SOPC:inst\|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port " "Info: Elaborating entity \"spi_touch_spi_control_port_arbitrator\" for hierarchy \"CORE_SOPC:inst\|spi_touch_spi_control_port_arbitrator:the_spi_touch_spi_control_port\"" {  } { { "core_sopc.v" "the_spi_touch_spi_control_port" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7543 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "spi_touch.v 1 1 " "Warning: Using design file spi_touch.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 spi_touch " "Info: Found entity 1: spi_touch" {  } { { "spi_touch.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/spi_touch.v" 41 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "spi_touch.v(401) " "Warning (10037): Verilog HDL or VHDL warning at spi_touch.v(401): conditional expression evaluates to a constant" {  } { { "spi_touch.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/spi_touch.v" 401 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_touch CORE_SOPC:inst\|spi_touch:the_spi_touch " "Info: Elaborating entity \"spi_touch\" for hierarchy \"CORE_SOPC:inst\|spi_touch:the_spi_touch\"" {  } { { "core_sopc.v" "the_spi_touch" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7563 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysid_control_slave_arbitrator CORE_SOPC:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave " "Info: Elaborating entity \"sysid_control_slave_arbitrator\" for hierarchy \"CORE_SOPC:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave\"" {  } { { "core_sopc.v" "the_sysid_control_slave" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7581 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "sysid.v 1 1 " "Warning: Using design file sysid.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sysid " "Info: Found entity 1: sysid" {  } { { "sysid.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sysid.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysid CORE_SOPC:inst\|sysid:the_sysid " "Info: Elaborating entity \"sysid\" for hierarchy \"CORE_SOPC:inst\|sysid:the_sysid\"" {  } { { "core_sopc.v" "the_sysid" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7589 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "touch_cs_s1_arbitrator CORE_SOPC:inst\|touch_cs_s1_arbitrator:the_touch_cs_s1 " "Info: Elaborating entity \"touch_cs_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|touch_cs_s1_arbitrator:the_touch_cs_s1\"" {  } { { "core_sopc.v" "the_touch_cs_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7612 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "touch_cs.v 1 1 " "Warning: Using design file touch_cs.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 touch_cs " "Info: Found entity 1: touch_cs" {  } { { "touch_cs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/touch_cs.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "touch_cs CORE_SOPC:inst\|touch_cs:the_touch_cs " "Info: Elaborating entity \"touch_cs\" for hierarchy \"CORE_SOPC:inst\|touch_cs:the_touch_cs\"" {  } { { "core_sopc.v" "the_touch_cs" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7624 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "touch_irq_s1_arbitrator CORE_SOPC:inst\|touch_irq_s1_arbitrator:the_touch_irq_s1 " "Info: Elaborating entity \"touch_irq_s1_arbitrator\" for hierarchy \"CORE_SOPC:inst\|touch_irq_s1_arbitrator:the_touch_irq_s1\"" {  } { { "core_sopc.v" "the_touch_irq_s1" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7642 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "touch_irq.v 1 1 " "Warning: Using design file touch_irq.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 touch_irq " "Info: Found entity 1: touch_irq" {  } { { "touch_irq.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/touch_irq.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "touch_irq CORE_SOPC:inst\|touch_irq:the_touch_irq " "Info: Elaborating entity \"touch_irq\" for hierarchy \"CORE_SOPC:inst\|touch_irq:the_touch_irq\"" {  } { { "core_sopc.v" "the_touch_irq" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7651 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CORE_SOPC_reset_clk_domain_synch_module CORE_SOPC:inst\|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch " "Info: Elaborating entity \"CORE_SOPC_reset_clk_domain_synch_module\" for hierarchy \"CORE_SOPC:inst\|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch\"" {  } { { "core_sopc.v" "CORE_SOPC_reset_clk_domain_synch" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7660 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Warning: Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Warning: Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 43 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 77 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 111 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 145 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 179 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 213 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 281 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 315 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 349 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 383 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 417 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 451 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 485 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 519 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 553 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 587 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 621 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 655 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 689 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 723 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 757 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 791 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 825 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 859 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 893 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 927 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 961 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 995 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 1029 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 1063 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 1097 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 1131 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 1165 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 1199 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\] " "Warning (14320): Synthesized away node \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\]\"" {  } { { "db/altsyncram_0a02.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/altsyncram_0a02.tdf" 1233 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2790 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 2951 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 3419 0 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8578 0 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 7129 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 96 600 1008 784 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1}  } {  } 0 0 "Synthesized away the following node(s):" 0 0 "" 0 -1}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "CORE_SOPC:inst\|cpu:the_cpu\|Add10 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"CORE_SOPC:inst\|cpu:the_cpu\|Add10\"" {  } { { "cpu.v" "Add10" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 7434 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CORE_SOPC:inst\|cpu:the_cpu\|lpm_add_sub:Add10 " "Info: Elaborated megafunction instantiation \"CORE_SOPC:inst\|cpu:the_cpu\|lpm_add_sub:Add10\"" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 7434 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CORE_SOPC:inst\|cpu:the_cpu\|lpm_add_sub:Add10 " "Info: Instantiated megafunction \"CORE_SOPC:inst\|cpu:the_cpu\|lpm_add_sub:Add10\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Info: Parameter \"LPM_WIDTH\" = \"33\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION DEFAULT " "Info: Parameter \"LPM_DIRECTION\" = \"DEFAULT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 7434 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qvi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qvi " "Info: Found entity 1: add_sub_qvi" {  } { { "db/add_sub_qvi.tdf" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/add_sub_qvi.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "Warning: 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 0 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "epcs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 242 -1 0 } } { "epcs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 131 -1 0 } } { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 440 -1 0 } } { "spi_touch.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/spi_touch.v" 242 -1 0 } } { "spi_touch.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/spi_touch.v" 131 -1 0 } } { "epcs.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/epcs.v" 252 -1 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 4490 -1 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 2058 -1 0 } } { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 354 -1 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 1138 -1 0 } } { "spi_touch.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/spi_touch.v" 252 -1 0 } } { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 606 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 284 -1 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 877 -1 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 5198 -1 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 4139 -1 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 5079 -1 0 } } { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 304 -1 0 } } { "jtag_uart.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/jtag_uart.v" 561 -1 0 } } { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 4967 -1 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 5432 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 223 -1 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 5464 -1 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 5423 -1 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 8103 -1 0 } } { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 788 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 -1}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "CKE VCC " "Warning (13410): Pin \"CKE\" is stuck at VCC" {  } { { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 536 1008 1184 552 "CKE" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Info: Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 0 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "78 78 " "Info: 78 registers lost all their fanouts during netlist optimizations. The first 78 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[0\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[1\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[2\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[3\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[4\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[5\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[6\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[7\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[8\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[9\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[10\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[11\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[12\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[13\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[14\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[15\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[16\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[17\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[18\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[19\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[20\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[21\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[22\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[23\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[24\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[25\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[26\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[26\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[27\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[27\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[28\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[28\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[29\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[29\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[30\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[30\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[31\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[31\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[34\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[33\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[32\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[32\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[35\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\|itm\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[0\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[16\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[15\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[14\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[13\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[12\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[11\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[10\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[9\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[8\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[7\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[6\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[5\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[4\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[3\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[2\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[1\] " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|trc_jtag_addr\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|epcs_epcs_control_port_arb_share_counter\[0\] " "Info: Register \"CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|epcs_epcs_control_port_arb_share_counter\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port " "Info: Register \"CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|last_cycle_cpu_instruction_master_granted_slave_epcs_epcs_control_port\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port " "Info: Register \"CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|last_cycle_cpu_data_master_granted_slave_epcs_epcs_control_port\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module " "Info: Register \"CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module " "Info: Register \"CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|epcs_epcs_control_port_reg_firsttransfer " "Info: Register \"CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|epcs_epcs_control_port_reg_firsttransfer\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|epcs_epcs_control_port_saved_chosen_master_vector\[1\] " "Info: Register \"CORE_SOPC:inst\|epcs_epcs_control_port_arbitrator:the_epcs_epcs_control_port\|epcs_epcs_control_port_saved_chosen_master_vector\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_arb_share_counter\[0\] " "Info: Register \"CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_arb_share_counter\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_reg_firsttransfer " "Info: Register \"CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_reg_firsttransfer\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_saved_chosen_master_vector\[1\] " "Info: Register \"CORE_SOPC:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_saved_chosen_master_vector\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|m_next~9 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|m_next~9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|m_next~10 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|m_next~10\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|m_next~13 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|m_next~13\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|m_next~14 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|m_next~14\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|m_next~16 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|m_next~16\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_next~4 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|i_next~4\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_next~5 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|i_next~5\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_next~6 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|i_next~6\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_state~14 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|i_state~14\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_state~15 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|i_state~15\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_state~16 " "Info: Register \"CORE_SOPC:inst\|sdram:the_sdram\|i_state~16\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|DRsize~3 " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|DRsize~3\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|DRsize~4 " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|DRsize~4\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|DRsize~5 " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|DRsize~5\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|DRsize.101 " "Info: Register \"CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck\|DRsize.101\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.map.smsg " "Info: Generated suppressed messages file E:/Program/EP4CE10/nios/LCD32/LED_hello_world.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info: Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1 " "Info: Adding node \"PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4421 " "Info: Implemented 4421 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "38 " "Info: Implemented 38 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "32 " "Info: Implemented 32 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "4135 " "Info: Implemented 4135 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "202 " "Info: Implemented 202 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 PLLs" {  } {  } 0 0 "Implemented %1!d! PLLs" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Info: Implemented 4 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 65 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 65 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 25 14:49:45 2013 " "Info: Processing ended: Mon Feb 25 14:49:45 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Info: Total CPU time (on all processors): 00:00:26" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 157 04/27/2011 SJ Full Version " "Info: Version 11.0 Build 157 04/27/2011 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 25 14:49:46 2013 " "Info: Processing started: Mon Feb 25 14:49:46 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off LED_hello_world -c LED_hello_world " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LED_hello_world -c LED_hello_world" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "LED_hello_world EP4CE10F17C8 " "Info: Selected device EP4CE10F17C8 for design \"LED_hello_world\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Info: Implemented PLL \"PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[0\] 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[0\] port" {  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[1\] 1 1 -100 -5556 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -100 degrees (-5556 ps) for PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[1\] port" {  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 77 -1 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Info: Device EP4CE6F17C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Info: Device EP4CE15F17C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Info: Device EP4CE22F17C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "Info: DATA\[0\] dual-purpose pin not reserved" {  } {  } 0 0 "DATA\[0\] dual-purpose pin not reserved" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_IGNORED_SPI_RESERVE_PIN_ASSIGNMENT" "DCLK " "Warning: Ignored reserve pin assignment to SPI programming pin DCLK" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { EPCS_CLK } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "EPCS_CLK" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 232 1008 1184 248 "EPCS_CLK" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPCS_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 183 5573 6591 0}  }  } }  } 0 0 "Ignored reserve pin assignment to SPI programming pin %1!s!" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "3 74 " "Critical Warning: No exact pin location assignment(s) for 3 pins of 74 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "out_port_from_the_bl_n " "Info: Pin out_port_from_the_bl_n not assigned to an exact location on the device" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { out_port_from_the_bl_n } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 168 1008 1224 184 "out_port_from_the_bl_n" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { out_port_from_the_bl_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 195 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "out_port_from_the_bl_p " "Info: Pin out_port_from_the_bl_p not assigned to an exact location on the device" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { out_port_from_the_bl_p } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 200 1008 1224 216 "out_port_from_the_bl_p" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { out_port_from_the_bl_p } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 196 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SS_n_from_the_spi_touch " "Info: Pin SS_n_from_the_spi_touch not assigned to an exact location on the device" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { SS_n_from_the_spi_touch } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 680 1008 1237 696 "SS_n_from_the_spi_touch" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { SS_n_from_the_spi_touch } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 204 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Info: Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Info: Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "Info: set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "cpu.sdc " "Info: Reading SDC File: 'cpu.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLK " "Warning: Node: CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1}  } {  } 1 0 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Info: Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " "Info:  100.000 altera_reserved_tck" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2) " "Info: Automatically promoted node PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 77 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 4903 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C1 of PLL_2) " "Info: Automatically promoted node PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C1 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 77 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:inst1|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 4903 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 5109 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CORE_SOPC:inst\|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch\|data_out  " "Info: Automatically promoted node CORE_SOPC:inst\|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|active_cs_n~0 " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|active_cs_n~0" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 210 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|active_cs_n~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 5754 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|active_rnw~1 " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|active_rnw~1" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 213 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|active_rnw~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 5763 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|jtag_break~1 " "Info: Destination node CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|jtag_break~1" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 393 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 6601 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[0\] " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[0\]" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 354 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|i_refs[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 608 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[2\] " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[2\]" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 354 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|i_refs[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 606 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[1\] " "Info: Destination node CORE_SOPC:inst\|sdram:the_sdram\|i_refs\[1\]" {  } { { "sdram.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/sdram.v" 354 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|sdram:the_sdram|i_refs[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 607 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|resetlatch~0 " "Info: Destination node CORE_SOPC:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|resetlatch~0" {  } { { "cpu.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/cpu.v" 376 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetlatch~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 8092 5573 6591 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6427 -1 0 } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CORE_SOPC:inst\|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch\|data_out" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|CORE_SOPC_reset_clk_domain_synch_module:CORE_SOPC_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 253 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CORE_SOPC:inst\|reset_n_sources~0  " "Info: Automatically promoted node CORE_SOPC:inst\|reset_n_sources~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "core_sopc.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/core_sopc.v" 6777 -1 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORE_SOPC:inst|reset_n_sources~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 5677 5573 6591 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 0 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Warning" "WFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS" "" "Warning: Ignoring some wildcard destinations of fast I/O register assignments" { { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[8\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[8\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[0\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[1\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[2\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[0\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[10\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[10\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[11\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[11\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[12\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[12\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[13\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[13\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[14\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[14\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[15\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[15\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[1\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[2\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[3\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[3\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[4\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[4\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[5\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[5\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[6\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[6\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[7\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[7\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[9\] " "Info: Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[9\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Enable Register ON oe " "Info: Wildcard assignment \"Fast Output Enable Register=ON\" to \"oe\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" {  } {  } 0 0 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1}  } {  } 0 0 "Ignoring some wildcard destinations of fast I/O register assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "10 EC " "Extra Info: Packed 10 registers into blocks of type EC" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Extra Info: Packed 64 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 I/O Input Buffer " "Extra Info: Packed 16 registers into blocks of type I/O Input Buffer" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "53 I/O Output Buffer " "Extra Info: Packed 53 registers into blocks of type I/O Output Buffer" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "66 " "Extra Info: Created 66 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 3.3V 0 3 0 " "Info: Number of I/O pins in group: 3 (unused VREF, 3.3V VCCIO, 0 input, 3 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 8 13 " "Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used --  13 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 12 7 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 12 total pin(s) used --  7 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 20 6 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 21 6 " "Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 21 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 11 14 " "Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 11 total pin(s) used --  14 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 3 11 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1 clk\[1\] S_CLK~output " "Warning: PLL \"PLL:inst1\|altpll:altpll_component\|PLL_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"S_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/pll_altpll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/db/pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/11.0/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll.v" "" { Text "E:/Program/EP4CE10/nios/LCD32/pll.v" 94 0 0 } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 64 152 392 232 "inst1" "" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 56 536 712 72 "S_CLK" "" } } } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:06 " "Info: Fitter preparation operations ending: elapsed time is 00:00:06" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "14 " "Info: Router estimated average interconnect usage is 14% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X11_Y0 X22_Y11 " "Info: Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" {  } {  } 0 0 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Info: Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 0 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_FIOMGR_MUST_USE_EXTERNAL_CLAMPING_DIODE_TOP_LEVEL" "1 " "Warning: Following 1 pins must use external clamping diodes." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "EPCS_DATA0 3.3-V LVTTL H2 " "Info: Pin EPCS_DATA0 uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { EPCS_DATA0 } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 304 320 496 320 "EPCS_DATA0" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPCS_DATA0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 185 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins must use external clamping diodes." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "36 Cyclone IV E " "Warning: 36 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[15\] 3.3-V LVTTL T7 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[15\] uses I/O standard 3.3-V LVTTL at T7" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[15] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[15\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 132 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[14\] 3.3-V LVTTL R6 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[14\] uses I/O standard 3.3-V LVTTL at R6" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[14] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[14\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 133 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[13\] 3.3-V LVTTL T8 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[13\] uses I/O standard 3.3-V LVTTL at T8" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[13] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[13\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 134 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[12\] 3.3-V LVTTL R7 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[12\] uses I/O standard 3.3-V LVTTL at R7" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[12] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[12\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 135 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[11\] 3.3-V LVTTL T9 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[11\] uses I/O standard 3.3-V LVTTL at T9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[11] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[11\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 136 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[10\] 3.3-V LVTTL R8 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[10\] uses I/O standard 3.3-V LVTTL at R8" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[10] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[10\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 137 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[9\] 3.3-V LVTTL T10 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[9\] uses I/O standard 3.3-V LVTTL at T10" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[9] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[9\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 138 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[8\] 3.3-V LVTTL R9 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[8\] uses I/O standard 3.3-V LVTTL at R9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[8] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[8\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 139 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[7\] 3.3-V LVTTL T11 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[7\] uses I/O standard 3.3-V LVTTL at T11" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[7] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[7\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 140 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[6\] 3.3-V LVTTL R10 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[6\] uses I/O standard 3.3-V LVTTL at R10" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[6] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[6\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 141 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[5\] 3.3-V LVTTL N9 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[5\] uses I/O standard 3.3-V LVTTL at N9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[5] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[5\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 142 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[4\] 3.3-V LVTTL P9 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[4\] uses I/O standard 3.3-V LVTTL at P9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[4] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[4\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 143 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[3\] 3.3-V LVTTL N11 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[3\] uses I/O standard 3.3-V LVTTL at N11" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[3] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[3\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 144 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[2\] 3.3-V LVTTL P11 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[2\] uses I/O standard 3.3-V LVTTL at P11" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[2] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[2\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 145 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[1\] 3.3-V LVTTL N12 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[1\] uses I/O standard 3.3-V LVTTL at N12" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[1] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[1\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 146 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "bidir_port_to_and_from_the_lcd32_data\[0\] 3.3-V LVTTL R11 " "Info: Pin bidir_port_to_and_from_the_lcd32_data\[0\] uses I/O standard 3.3-V LVTTL at R11" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { bidir_port_to_and_from_the_lcd32_data[0] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_lcd32_data\[0\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 296 1008 1332 312 "bidir_port_to_and_from_the_lcd32_data" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_lcd32_data[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 147 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[15\] 3.3-V LVTTL G15 " "Info: Pin DQ\[15\] uses I/O standard 3.3-V LVTTL at G15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[15] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[15\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 148 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[14\] 3.3-V LVTTL J15 " "Info: Pin DQ\[14\] uses I/O standard 3.3-V LVTTL at J15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[14] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[14\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 149 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[13\] 3.3-V LVTTL J16 " "Info: Pin DQ\[13\] uses I/O standard 3.3-V LVTTL at J16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[13] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[13\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 150 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[12\] 3.3-V LVTTL K15 " "Info: Pin DQ\[12\] uses I/O standard 3.3-V LVTTL at K15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[12] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[12\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 151 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[11\] 3.3-V LVTTL K16 " "Info: Pin DQ\[11\] uses I/O standard 3.3-V LVTTL at K16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[11] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[11\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 152 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[10\] 3.3-V LVTTL L15 " "Info: Pin DQ\[10\] uses I/O standard 3.3-V LVTTL at L15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[10] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[10\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 153 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[9\] 3.3-V LVTTL L16 " "Info: Pin DQ\[9\] uses I/O standard 3.3-V LVTTL at L16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[9] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[9\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 154 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[8\] 3.3-V LVTTL N15 " "Info: Pin DQ\[8\] uses I/O standard 3.3-V LVTTL at N15" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[8] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[8\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 155 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[7\] 3.3-V LVTTL P1 " "Info: Pin DQ\[7\] uses I/O standard 3.3-V LVTTL at P1" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[7] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[7\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 156 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[6\] 3.3-V LVTTL P2 " "Info: Pin DQ\[6\] uses I/O standard 3.3-V LVTTL at P2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[6] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[6\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 157 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[5\] 3.3-V LVTTL N1 " "Info: Pin DQ\[5\] uses I/O standard 3.3-V LVTTL at N1" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[5] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[5\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 158 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[4\] 3.3-V LVTTL N2 " "Info: Pin DQ\[4\] uses I/O standard 3.3-V LVTTL at N2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[4] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[4\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 159 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[3\] 3.3-V LVTTL L1 " "Info: Pin DQ\[3\] uses I/O standard 3.3-V LVTTL at L1" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[3] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[3\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 160 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[2\] 3.3-V LVTTL L2 " "Info: Pin DQ\[2\] uses I/O standard 3.3-V LVTTL at L2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[2] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[2\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 161 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[1\] 3.3-V LVTTL K1 " "Info: Pin DQ\[1\] uses I/O standard 3.3-V LVTTL at K1" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[1] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[1\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 162 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DQ\[0\] 3.3-V LVTTL K2 " "Info: Pin DQ\[0\] uses I/O standard 3.3-V LVTTL at K2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { DQ[0] } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DQ\[0\]" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 568 1008 1184 584 "DQ" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 163 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLK 3.3-V LVTTL E16 " "Info: Pin CLK uses I/O standard 3.3-V LVTTL at E16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { CLK } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 120 -32 136 136 "CLK" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 182 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "RESET 3.3-V LVTTL B16 " "Info: Pin RESET uses I/O standard 3.3-V LVTTL at B16" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { RESET } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "RESET" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 272 -72 96 288 "RESET" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 184 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_port_to_the_touch_irq 3.3-V LVTTL T4 " "Info: Pin in_port_to_the_touch_irq uses I/O standard 3.3-V LVTTL at T4" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { in_port_to_the_touch_irq } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "in_port_to_the_touch_irq" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 744 376 600 760 "in_port_to_the_touch_irq" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { in_port_to_the_touch_irq } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 187 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "MISO_to_the_spi_touch 3.3-V LVTTL K9 " "Info: Pin MISO_to_the_spi_touch uses I/O standard 3.3-V LVTTL at K9" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { MISO_to_the_spi_touch } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "MISO_to_the_spi_touch" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 648 384 600 664 "MISO_to_the_spi_touch" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO_to_the_spi_touch } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 186 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_FOR_CONFIGURATION_PIN_TOP_LEVEL" "1 " "Warning: PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "EPCS_DATA0 3.3-V LVTTL H2 " "Info: Pin EPCS_DATA0 uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { EPCS_DATA0 } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } { "LED_hello_world.bdf" "" { Schematic "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.bdf" { { 304 320 496 320 "EPCS_DATA0" "" } } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPCS_DATA0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/Program/EP4CE10/nios/LCD32/" { { 0 { 0 ""} 0 185 5573 6591 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "PCI-clamp diode is not supported in this mode. The following %1!d! pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Program/EP4CE10/nios/LCD32/LED_hello_world.fit.smsg " "Info: Generated suppressed messages file E:/Program/EP4CE10/nios/LCD32/LED_hello_world.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 18 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "357 " "Info: Peak virtual memory: 357 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 25 14:50:05 2013 " "Info: Processing ended: Mon Feb 25 14:50:05 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Info: Total CPU time (on all processors): 00:00:20" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 157 04/27/2011 SJ Full Version " "Info: Version 11.0 Build 157 04/27/2011 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 25 14:50:06 2013 " "Info: Processing started: Mon Feb 25 14:50:06 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off LED_hello_world -c LED_hello_world " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off LED_hello_world -c LED_hello_world" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 157 04/27/2011 SJ Full Version " "Info: Version 11.0 Build 157 04/27/2011 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 25 14:50:06 2013 " "Info: Processing started: Mon Feb 25 14:50:06 2013" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta LED_hello_world -c LED_hello_world " "Info: Command: quartus_sta LED_hello_world -c LED_hello_world" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Info: Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\]  " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read_write1*\}\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|td_shift\[0\]*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\] " "Info: set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "Info: set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Info: Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "Info: set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "226 " "Info: Peak virtual memory: 226 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 25 14:50:08 2013 " "Info: Processing ended: Mon Feb 25 14:50:08 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "cpu.sdc " "Info: Reading SDC File: 'cpu.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLK " "Warning: Node: CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1}  } {  } 1 0 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 45.521 " "Info: Worst-case setup slack is 45.521" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   45.521         0.000 altera_reserved_tck  " "Info:    45.521         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Info: Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.452         0.000 altera_reserved_tck  " "Info:     0.452         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.519 " "Info: Worst-case recovery slack is 47.519" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   47.519         0.000 altera_reserved_tck  " "Info:    47.519         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.128 " "Info: Worst-case removal slack is 1.128" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.128         0.000 altera_reserved_tck  " "Info:     1.128         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.456 " "Info: Worst-case minimum pulse width slack is 49.456" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.456         0.000 altera_reserved_tck  " "Info:    49.456         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Info: Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Info: Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Info: Number of Synchronizer Chains Found: 2" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 195.084 ns " "Info: Worst Case Available Settling Time: 195.084 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLK " "Warning: Node: CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1}  } {  } 1 0 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 45.953 " "Info: Worst-case setup slack is 45.953" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   45.953         0.000 altera_reserved_tck  " "Info:    45.953         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Info: Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.401         0.000 altera_reserved_tck  " "Info:     0.401         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.841 " "Info: Worst-case recovery slack is 47.841" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   47.841         0.000 altera_reserved_tck  " "Info:    47.841         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.028 " "Info: Worst-case removal slack is 1.028" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.028         0.000 altera_reserved_tck  " "Info:     1.028         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.326 " "Info: Worst-case minimum pulse width slack is 49.326" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.326         0.000 altera_reserved_tck  " "Info:    49.326         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Info: Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Info: Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Info: Number of Synchronizer Chains Found: 2" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 195.340 ns " "Info: Worst Case Available Settling Time: 195.340 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLK " "Warning: Node: CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Warning: Node: inst1\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 0 "From %1!s! to %2!s! (%3!s!)" 0 0 "" 0 -1}  } {  } 1 0 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.454 " "Info: Worst-case setup slack is 48.454" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.454         0.000 altera_reserved_tck  " "Info:    48.454         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.184 " "Info: Worst-case hold slack is 0.184" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.184         0.000 altera_reserved_tck  " "Info:     0.184         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 49.204 " "Info: Worst-case recovery slack is 49.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.204         0.000 altera_reserved_tck  " "Info:    49.204         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.493 " "Info: Worst-case removal slack is 0.493" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.493         0.000 altera_reserved_tck  " "Info:     0.493         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.294 " "Info: Worst-case minimum pulse width slack is 49.294" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.294         0.000 altera_reserved_tck  " "Info:    49.294         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Info: Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Info: Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Info: Number of Synchronizer Chains Found: 2" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.953 ns " "Info: Worst Case Available Settling Time: 197.953 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 24 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Info: Peak virtual memory: 277 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 25 14:50:13 2013 " "Info: Processing ended: Mon Feb 25 14:50:13 2013" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Warning" "WFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 0 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "" 0 -1}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 108 s " "Info: Quartus II Full Compilation was successful. 0 errors, 108 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
