Release Notes for STM32L4xx CMSIS

Back to Release page

# Release Notes for STM32L4xx CMSIS

Copyright 2016 STMicroelectronics

## Update History

### V1.1.1 / 29-April-2016

Main Changes

- All device register description files enriched with _Pos and _Msk defines to be used with _VAL2FLD(field, value) and _FLD2VAL(field, value) from CMSIS Core (previous defines are kept for compatibility)
- stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files

- Update DFSDM peripheral instance and register definitions (named DFSDM1 peripheral from now instead of DFSDM)

- Rename DFSDMx_IRQn to DFSDM1_FLTx_IRQn for x=0,1,2 and 3 (filters)

- Rename DFSDM channels and filters to refer to DFSDM1 peripheral instance with DFSDM1 prefix

- DFSDM1_Channel0, DFSDM1_Channel1, ... DFSDM1_Channel7

- DFSDM1_Filter0, DFSDM1_Filter1, ..., DFSDM1_Filter3

- Rename registers in DFSDM_Filter_TypeDef to use FLT prefix for filter

- FLTCR1, FLTCR2, FLTISR, FLTICR, FLTJCHGR, FLTFCR, FLTJDATAR, FLTRDATAR, FLTAWHTR, FLTAWLTR, FLTAWSR, FLTAWCFR, FLTEXMAX, FLTEXMIN, FLTCNVTIMR

- Rename register in DFSDM_Filter_TypeDef to use CH prefix for channel

- CHAWSCDR

- Update RCC definitions for DFSDM1

- Rename RCC_APB2RSTR_DFSDMRST to RCC_APB2RSTR_DFSDM1RST

- Rename RCC_APB2ENR_DFSDMEN to RCC_APB2ENR_DFSDM1EN

- Rename RCC_APB2SMENR_DFSDMSMEN to RCC_APB2SMENR_DFSDM1SMEN

- Rename RCC_CCIPR_DFSDMSEL to RCC_CCIPR_DFSDM1SEL

- Update TIM definitions for DFSDM1

- Rename TIM1_OR2_BKDFBK0E to TIM1_OR2_BKDF1BK0E

- Rename TIM1_OR3_BK2DFBK1E to TIM1_OR3_BK2DF1BK1E

- Rename TIM8_OR2_BKDFBK2E to TIM8_OR2_BKDF1BK2E

- Rename TIM8_OR3_BK2DFBK3E to TIM8_OR3_BK2DF1BK3E

- Rename TIM15_OR2_BKDFBK0E to TIM15_OR2_BKDF1BK0E

- Rename TIM16_OR2_BKDFBK1E to TIM16_OR2_BKDF1BK1E

- Rename TIM17_OR2_BKDFBK2E to TIM17_OR2_BKDF1BK2E

- FMC

- Add FMC_BWTRx_BUSTURN register bit definition

- startup_stm32l471xx.s, startup_stm32l475xx.s, startup_stm32l476xx.s, startup_stm32l485xx.s and startup_stm32l486xx.s

- Rename DFSDMx_IRQHandler function entry points to DFSDM1_FLTx_IRQHandler for x=0,1,2 and 3 (filters)

### V1.1.0 / 26-February-2016

Main Changes

- Add the support of STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx devices

- Add stm32l431xx.h, stm32l432xx.h, stm32l433xx.h, stm32l442xx.h and stm32l443xx.h device description files
- Add startup files startup_stm32l431xx.s, startup_stm32l432xx.s, startup_stm32l433xx.s, startup_stm32l442xx.s and startup_stm32l443xx.s for EWARM, MDK-ARM and SW4STM32 toolchains
- Add linker files stm32l431xx_flash.icf, stm32l431xx_sram.icf, stm32l432xx_flash.icf, stm32l432xx_sram.icf, stm32l433xx_flash.icf, stm32l433xx_sram.icf, stm32l442xx_flash.icf, stm32l442xx_sram.icf, stm32l443xx_flash.icf and stm32l443xx_sram.icf used within EWARM workspaces

- stm32l4xx.h

- Add the following device defines:

- "#define STM32L431xx" for all STM32L431xx devices

- "#define STM32L432xx" for all STM32L432xx devices

- "#define STM32L433xx" for all STM32L433xx devices

- "#define STM32L442xx" for all STM32L442xx devices

- "#define STM32L443xx" for all STM32L443xx devices

- stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files

- DFSDM - alignment with registers & bits naming used in documentation

- Rename DFSDM_AWSCDR_WDATA to DFSDM_CHWDATR_WDATA
- Rename DFSDM_AWSCDR_INDAT0 to DFSDM_CHDATINR_INDAT0
- Rename DFSDM_AWSCDR_INDAT0 to DFSDM_CHDATINR_INDAT0

### V1.0.3 / 29-January-2016

Main Changes

- stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files

- Apply MISRA C 2004 rule 10.6 ('U' suffix added)
- Add PACKAGE_BASE, UID_BASE and FLASHSIZE_BASE base address definitions
- ADC

- Update ADC_CSR register bit definition

- LPUART

- Add IS_LPUART_INSTANCE() to check USART instance with low power capatibility

- system_stm32l4xx.h/.c

- Add declaration of APB Prescaler table values (const uint8_t APBPrescTable[8])

### V1.0.2 / 25-November-2015

Main Changes

- stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files

- GPIO

- Align GPIO register bit definitions with RM0351 (legacy definitions preserved for compatibility)

- FMC

- Remove FMC_BCR1_WFDIS bit definition (write fifo feature not available)

- PWR

- Stop 0 mode introduction

- PWR_CR1_LPMS_STOP1MR renamed to PWR_CR1_LPMS_STOP0
- PWR_CR1_LPMS_STOP1LPR renamed to PWR_CR1_LPMS_STOP1

- RCC
  - Align RCC register bit definitions with RM0351 (legacy definitions preserved for compatibility)
- TIM

- Add IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE() to check timer instance capability for hall sensor interface

- system_stm32l4xx.c

- Fix PLLCFGR default value in SystemInit()

### V1.0.1 / 16-September-2015

Main Changes

- stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files

- DBGMCU

- Fix DBGMCU_IDCODE_DEV_ID mask definition

- FLASH

- Add FLASH_OPTR_nRST_SHDW bit definition

- I2C

- Fix naming I2C_CR1_DNF instead of I2C_CR1_DFN

- TIM

- Add TIM16_OR2_BKDFBK1E bit definition

- Add TIM17_OR2_BKDFBK2E bit definition

- system_stm32l4xx.c

- SystemCoreClockUpdate() corrected for SystemCoreClock computation when PLL is enabled

### V1.0.0 / 26-June-2015

Main Changes

- First official release for STM32L471xx, STM32L475xx, STM32L476xx, STM32L485xx and STM32L486xx devices

## License

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived

from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

For complete documentation on STM32 Microcontrollers visit www.st.com/STM32